[网络驱动]：优化 phy_init() 函数
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* File : fsl_phy_fire.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* Change Logs:
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* Date Author Notes
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* 2018-05-21 zylx first version
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*/
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#include "fsl_phy_fire.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the timeout macro. */
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#include <rtthread.h>
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "[PHY]"
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#define DBG_COLOR
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the ENET instance from peripheral base address.
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*
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* @param base ENET peripheral base address.
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* @return ENET instance.
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*/
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extern uint32_t ENET_GetInstance(ENET_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to enet clocks for each instance. */
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@ -66,12 +48,12 @@ extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
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status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
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{
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uint32_t bssReg;
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uint32_t i;
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uint32_t counter = PHY_TIMEOUT_COUNT;
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uint32_t idReg = 0;
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status_t result = kStatus_Success;
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uint32_t instance = ENET_GetInstance(base);
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uint32_t timeDelay;
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// uint32_t ctlReg = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Set SMI first. */
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@ -83,7 +65,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
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while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
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{
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PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
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counter --;
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counter --;
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}
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if (!counter)
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@ -96,53 +78,51 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result == kStatus_Success)
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{
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//#if 0//defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
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// uint32_t data = 0;
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// result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
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// if ( result != kStatus_Success)
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// {
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// return result;
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// }
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// result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
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// if (result != kStatus_Success)
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// {
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// return result;
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// }
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//#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
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/* Set the negotiation. */
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result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
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PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
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if (result == kStatus_Success)
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for (i = 0x10000; i > 0; i--)
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{
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
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(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg);
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if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK))
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{
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break;
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}
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}
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if (i != 0)
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{
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/* Set the negotiation. */
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result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
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PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
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if (result == kStatus_Success)
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{
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/* Check auto negotiation complete. */
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while (counter --)
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
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(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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if (result == kStatus_Success)
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{
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
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if ( result == kStatus_Success)
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/* Check auto negotiation complete. */
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while (counter --)
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{
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//PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg);&& (ctlReg & PHY_LINK_READY_MASK)
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if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) )
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
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if (result == kStatus_Success)
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{
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/* Wait a moment for Phy status stable. */
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for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
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if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0))
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{
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__ASM("nop");
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rt_thread_delay(1);
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}
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else
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{
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dbg_log(DBG_LOG, "auto negotiation complete success\n");
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break;
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}
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break;
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}
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}
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if (!counter)
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{
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dbg_log(DBG_LOG, "auto negotiation complete falied\n");
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return kStatus_PHY_AutoNegotiateFail;
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}
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}
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}
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}
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@ -234,9 +214,9 @@ status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode,
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}
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else
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{
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data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
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return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
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}
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else
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{
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@ -329,7 +309,8 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *
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*speed = kPHY_Speed100M;
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}
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else
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{ /* 10M speed. */
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{
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/* 10M speed. */
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*speed = kPHY_Speed10M;
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}
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}
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@ -63,6 +63,7 @@
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#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
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#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
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#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
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#define PHY_BCTL_POWER_DOWN_MASK 0x800U /*!< The PHY Power Down mask. */
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/*!@brief Defines the mask flag of operation mode in control two register*/
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#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
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