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Merge pull request #3468 from bigmagic123/aarch64_cache_api 

Aarch64 cache api
This commit is contained in:
Bernard Xiong 2020-03-19 02:11:34 +08:00 committed by GitHub
parent f70d14ef93 e6600dbf10
commit 9c544e069c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 743 additions and 1180 deletions
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51
bsp/raspberry-pi/raspi3-64/.config
View File

@ -148,7 +148,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_I2C=y
CONFIG_RT_I2C_DEBUG=y
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
@ -163,7 +166,12 @@ CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
CONFIG_RT_SDIO_DEBUG=y
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@ -420,36 +428,6 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
# CONFIG_PKG_USING_ZBAR is not set
CONFIG_BCM2836_SOC=y
# CONFIG_BSP_SUPPORT_FPU is not set
@ -468,8 +446,13 @@ CONFIG_BSP_USING_CORETIMER=y
CONFIG_BSP_USING_SYSTIMER=y
CONFIG_RT_USING_SYSTIMER1=y
CONFIG_RT_USING_SYSTIMER3=y
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_SPI is not set
CONFIG_BSP_USING_I2C=y
# CONFIG_BSP_USING_I2C0 is not set
CONFIG_BSP_USING_I2C1=y
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI0_BUS=y
CONFIG_BSP_USING_SPI0_DEVICE0=y
# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
CONFIG_BSP_USING_WDT=y
# CONFIG_BSP_USING_RTC is not set
CONFIG_BSP_USING_SDIO=y

15
bsp/raspberry-pi/raspi3-64/driver/Kconfig
View File

@ -63,12 +63,17 @@ menu "Hardware Drivers Config"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0"
if BSP_USING_SPI
config BSP_USING_SPI0_BUS
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1"
config BSP_USING_SPI0_DEVICE0
bool "Enable SPI0 DEVICE0"
select BSP_USING_SPI0_BUS
default n
config BSP_USING_SPI0_DEVICE1
bool "Enable SPI0 DEVICE1"
select BSP_USING_SPI0_BUS
default n
endif

2
bsp/raspberry-pi/raspi3-64/driver/board.c
View File

@ -100,6 +100,8 @@ void rt_hw_board_init(void)
armv8_map(0x40000000, 0x40000000, 0x1000, MEM_ATTR_IO);//core timer
armv8_map(0x3F300000, 0x3F300000, 0x1000, MEM_ATTR_IO);//sdio
armv8_map(0xc00000, 0xc00000, 0x1000, MEM_ATTR_IO);//mbox
armv8_map(0x3f804000, 0x3f804000, 0x1000, MEM_ATTR_IO);//i2c0
armv8_map(0x3f205000, 0x3f205000, 0x1000, MEM_ATTR_IO);//i2c1
mmu_enable();
/* initialize hardware interrupt */

257
bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,56 +8,104 @@
* 2019-07-29 zdzn first version
*/
#include "raspi.h"
#include "drv_i2c.h"
#if defined (BSP_USING_I2C0)
#define I2C1BUS_NAME "i2c0"
#endif /*BSP_USING_I2C0*/
//Maybe redefined
typedef unsigned long rt_ubase_t;
typedef rt_ubase_t rt_size_t;
#if defined (BSP_USING_I2C1)
#define I2C2BUS_NAME "i2c1"
#endif /*BSP_USING_I2C1*/
static int i2c_byte_wait_us = 0;
#ifdef BSP_USING_I2C0
static struct raspi_i2c_bus raspi_i2c0 =
rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
{
.device_name = I2C1BUS_NAME,
};
rt_uint32_t status;
rt_uint32_t remaining = len;
rt_uint32_t i = 0;
rt_uint8_t reason = BCM283X_I2C_REASON_OK;
static struct raspi_master_config_t raspi_i2c0_cfg =
/* Clear FIFO */
BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
/* Clear Status */
BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
/* Set Data Length */
BCM283X_BSC_DLEN(base) = len;
if (flag)
{
/* Start read */
BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
/* wait for transfer to complete */
while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
{
/* we must empty the FIFO as it is populated and not use any delay */
while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
{
/* Read from FIFO, no barrier */
buf[i] = BCM283X_BSC_FIFO(base);
i++;
remaining--;
}
}
/* transfer has finished - grab any remaining stuff in FIFO */
while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
{
/* Read from FIFO, no barrier */
buf[i] = BCM283X_BSC_FIFO(base);
i++;
remaining--;
}
}
else
{
/* pre populate FIFO with max buffer */
while (remaining && (i < BSC_FIFO_SIZE))
{
BCM283X_BSC_FIFO(base) = buf[i];
i++;
remaining--;
}
/* Enable device and start transfer */
BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
/* Transfer is over when BCM2835_BSC_S_DONE */
while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
{
while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD))
{
/* Write to FIFO */
BCM283X_BSC_FIFO(base) = buf[i];
i++;
remaining--;
}
}
}
status = BCM283X_BSC_S(base);
if (status & BSC_S_ERR)
{
reason = BCM283X_I2C_REASON_ERROR_NACK;
}
else if (status & BSC_S_CLKT)
{
reason = BCM283X_I2C_REASON_ERROR_CLKT;
}
else if (remaining)
{
reason = BCM283X_I2C_REASON_ERROR_DATA;
}
BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
return reason;
}
struct raspi_i2c_hw_config
{
.sdl_pin = BCM_GPIO_PIN_0,
.scl_pin = BCM_GPIO_PIN_1,
.sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.slave_address = 8,
.bsc_base = (PER_BASE + BCM283X_BSC0_BASE),
.clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
rt_uint8_t bsc_num;
rt_uint8_t sdl_pin;
rt_uint8_t scl_pin;
rt_uint8_t sdl_mode;
rt_uint8_t scl_mode;
};
#endif /* RT_USING_HW_I2C1 */
#ifdef BSP_USING_I2C1
static struct raspi_i2c_bus raspi_i2c1 =
{
.device_name = I2C2BUS_NAME,
};
static struct raspi_master_config_t raspi_i2c1_cfg =
{
.sdl_pin = BCM_GPIO_PIN_2,
.scl_pin = BCM_GPIO_PIN_3,
.sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.slave_address = 9,
.bsc_base = (PER_BASE + BCM283X_BSC1_BASE),
.clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
};
#endif /* RT_USING_HW_I2C2 */
#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
@ -70,58 +118,32 @@ static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t,
rt_uint32_t);
void i2c_master_init(struct raspi_master_config_t *cfg)
{
volatile rt_uint32_t addr;
rt_uint32_t data;
bcm283x_gpio_fsel(cfg->sdl_pin, cfg->sdl_pin_mode); /* SDA */
bcm283x_gpio_fsel(cfg->scl_pin, cfg->scl_pin_mode); /* SCL */
addr = cfg->bsc_base + BCM283X_BSC_DIV;
data = bcm283x_peri_read(addr);
i2c_byte_wait_us = ( data * 1000000 / BCM283X_CORE_CLK_HZ) * 9;
addr = cfg->bsc_base + BCM283X_BSC_DIV;
bcm283x_peri_write(addr, cfg->clk_div);
//update
i2c_byte_wait_us = (cfg->clk_div * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
}
static rt_uint32_t i2c_byte_wait_us = 0;
static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
volatile rt_uint32_t addr;
struct raspi_i2c_bus *raspi_i2c;
rt_size_t i;
rt_uint8_t reason;
RT_ASSERT(bus != RT_NULL);
raspi_i2c = (struct raspi_i2c_bus *) bus;
raspi_i2c->msg = msgs;
raspi_i2c->msg_ptr = 0;
raspi_i2c->msg_cnt = num;
raspi_i2c->dptr = 0;
addr = raspi_i2c->cfg->bsc_base + BCM283X_BSC_A;
bcm283x_peri_write(addr, msgs->addr);
volatile rt_base_t base = (volatile rt_base_t)(bus->parent.user_data);
if (bus->addr == 0)
base = BCM283X_BSC0_BASE;
else
base = BCM283X_BSC1_BASE;
BCM283X_BSC_A(base) = msgs->addr;
for (i = 0; i < num; i++)
{
if ( raspi_i2c->msg[i].flags & RT_I2C_RD )
{
bcm283x_i2c_read(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
}
if (msgs[i].flags & RT_I2C_RD)
reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1);
else
{
bcm283x_i2c_write(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
}
reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0);
}
raspi_i2c->msg = RT_NULL;
raspi_i2c->msg_ptr = 0;
raspi_i2c->msg_cnt = 0;
raspi_i2c->dptr = 0;
return i;
return (reason == 0)? i : 0;
}
static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
@ -134,7 +156,7 @@ static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t cmd,
rt_uint32_t arg)
{
return RT_ERROR;
return RT_EOK;
}
static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
@ -144,33 +166,72 @@ static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
.i2c_bus_control = raspi_i2c_bus_control,
};
static rt_err_t raspi_i2c_configure(struct raspi_i2c_bus *bus, struct raspi_master_config_t *cfg)
static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
{
RT_ASSERT(bus != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
bus->device.ops = &raspi_i2c_ops;
bus->cfg = cfg;
volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE;
GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */
GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */
/* use 0xFFFE mask to limit a max value and round down any odd number */
rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE;
BCM283X_BSC_DIV(base) = (rt_uint16_t) divider;
i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
i2c_master_init(cfg);
return RT_EOK;
}
#endif
#if defined (BSP_USING_I2C0)
#define I2C0_BUS_NAME "i2c0"
static struct raspi_i2c_hw_config hw_device0 =
{
.bsc_num = 0,
.sdl_pin = RPI_GPIO_P1_27,
.scl_pin = RPI_GPIO_P1_28,
.sdl_mode = BCM283X_GPIO_FSEL_ALT0,
.scl_mode = BCM283X_GPIO_FSEL_ALT0,
};
struct rt_i2c_bus_device device0 =
{
.ops = &raspi_i2c_ops,
.addr = 0,
};
#endif
#if defined (BSP_USING_I2C1)
#define I2C1_BUS_NAME "i2c1"
static struct raspi_i2c_hw_config hw_device1 =
{
.bsc_num = 1,
.sdl_pin = RPI_GPIO_P1_03,
.scl_pin = RPI_GPIO_P1_05,
.sdl_mode = BCM283X_GPIO_FSEL_ALT0,
.scl_mode = BCM283X_GPIO_FSEL_ALT0,
};
struct rt_i2c_bus_device device1 =
{
.ops = &raspi_i2c_ops,
.addr = 1,
};
#endif
int rt_hw_i2c_init(void)
{
#if defined(BSP_USING_I2C0)
raspi_i2c_configure(&raspi_i2c0 , &raspi_i2c0_cfg);
rt_i2c_bus_device_register(&raspi_i2c0.device, raspi_i2c0.device_name);
#endif /* BSP_USING_I2C1 */
raspi_i2c_configure(&hw_device0);
rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
#endif
#if defined(BSP_USING_I2C1)
raspi_i2c_configure(&raspi_i2c1 , &raspi_i2c1_cfg);
rt_i2c_bus_device_register(&raspi_i2c1.device, raspi_i2c1.device_name);
#endif /* BSP_USING_I2C2 */
raspi_i2c_configure(&hw_device1);
rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
#endif
return 0;
}

6
bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -11,10 +11,10 @@
#ifndef __DRV_I2C_H__
#define __DRV_I2C_H__
#include <rthw.h>
#include <rtdevice.h>
#include <rtthread.h>
#include "bcm283x.h"
#include "board.h"
struct raspi_master_config_t
{

505
bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
View File

@ -7,446 +7,281 @@
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include "drv_spi.h"
#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1)
#ifdef RT_USING_SPI
#undef RT_USING_SPI
#endif
#endif
#include "raspi.h"
#ifdef RT_USING_SPI
struct rpi_pin_index
{
rt_uint8_t phy_id;
rt_uint8_t bcm_id;
rt_uint8_t signal_name;
rt_uint8_t magic;
};
//raspi phy id and bcm id
static struct rpi_pin_index phypin_index[] =
{
{0, 0, 0, 0},
{1, 0, 0, 0},
{2, 0, 0, 0},
{3, BCM_GPIO_PIN_2, RPI_SDA1, PIN_MAGIC},
{4, 0, 0, 0},
{5, BCM_GPIO_PIN_3, RPI_SCL1, PIN_MAGIC},
{6, 0, 0, 0},
{7, BCM_GPIO_PIN_4, RPI_GPIO_GCLK, PIN_MAGIC},
{8, BCM_GPIO_PIN_14, RPI_TXD0, PIN_MAGIC},
{9, 0, 0, 0},
{10, BCM_GPIO_PIN_15, RPI_RXD0, PIN_MAGIC},
{11, BCM_GPIO_PIN_17, RPI_GPIO_GEN0, PIN_MAGIC},
{12, BCM_GPIO_PIN_18, RPI_GPIO_GEN1, PIN_MAGIC},
{13, BCM_GPIO_PIN_27, RPI_GPIO_GEN2, PIN_MAGIC},
{14, 0, 0, 0},
{15, BCM_GPIO_PIN_22, RPI_GPIO_GEN3, PIN_MAGIC},
{16, BCM_GPIO_PIN_23, RPI_GPIO_GEN4, PIN_MAGIC},
{17, 0, 0, 0},
{18, BCM_GPIO_PIN_24, RPI_GPIO_GEN5, PIN_MAGIC},
{19, BCM_GPIO_PIN_10, RPI_SPI_MOSI, PIN_MAGIC},
{20, 0, 0, 0},
{21, BCM_GPIO_PIN_9, RPI_SPI_MISO, PIN_MAGIC},
{22, BCM_GPIO_PIN_25, RPI_GPIO_GEN6, PIN_MAGIC},
{23, BCM_GPIO_PIN_11, RPI_SPI_SCLK, PIN_MAGIC},
{24, BCM_GPIO_PIN_8, RPI_SPI_CE0_N, PIN_MAGIC},
{25, 0, 0, 0},
{26, BCM_GPIO_PIN_7, RPI_SPI_CE1_N, PIN_MAGIC},
{27, BCM_GPIO_PIN_0, RPI_SDA0, PIN_MAGIC},
{28, BCM_GPIO_PIN_1, RPI_SCL0, PIN_MAGIC},
{29, BCM_GPIO_PIN_5, RPI_CAM_CLK, PIN_MAGIC},
{30, 0, 0, 0},
{31, BCM_GPIO_PIN_6, RPI_LAN_RUN, PIN_MAGIC},
{32, BCM_GPIO_PIN_12, 0, PIN_MAGIC},
{33, BCM_GPIO_PIN_13, 0, PIN_MAGIC},
{34, 0, 0, 0},
{35, BCM_GPIO_PIN_19, 0, PIN_MAGIC},
{36, BCM_GPIO_PIN_16, RPI_STATUS_LED_N, PIN_MAGIC},
{37, BCM_GPIO_PIN_26, 0, PIN_MAGIC},
{38, BCM_GPIO_PIN_20, 0, PIN_MAGIC},
{39, 0, 0, 0},
{40, BCM_GPIO_PIN_21, RPI_CAM_GPIO, PIN_MAGIC},
};
static rt_uint8_t bcm2835_spi_bit_order = BCM283X_SPI_BIT_ORDER_MSBFIRST;
static rt_uint8_t bcm2835_byte_reverse_table[] =
{
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
};
#define RPI_CORE_CLK_HZ 250000000
#define BSP_SPI_MAX_HZ (30* 1000 *1000)
#define SPITIMEOUT 0x0FFF
struct rt_spi_hw_config
void spi_gpio_write(rt_uint8_t pin, rt_uint8_t val)
{
rt_int8_t sclk_pin;
rt_int8_t sclk_mode;
rt_int8_t mosi_pin;
rt_int8_t mosi_mode;
rt_int8_t miso_pin;
rt_int8_t miso_mode;
rt_int8_t cs_pin;
rt_int8_t cs_mode;
rt_uint32_t spi_base;
rt_uint32_t clk_div;
if (val)
BCM283X_GPIO_GPSET((pin / 32)) = 1 << (pin % 32);
else
BCM283X_GPIO_GPCLR((pin / 32)) = 1 << (pin % 32);
}
struct raspi_spi_hw_config
{
rt_uint8_t spi_num;
raspi_gpio_pin sclk_pin;
raspi_pin_select sclk_mode;
raspi_gpio_pin mosi_pin;
raspi_pin_select mosi_mode;
raspi_gpio_pin miso_pin;
raspi_pin_select miso_mode;
#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0)
raspi_gpio_pin ce0_pin;
raspi_pin_select ce0_mode;
#endif
#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1)
raspi_gpio_pin ce1_pin;
raspi_pin_select ce1_mode;
#endif
#if defined (BSP_USING_SPI1_DEVICE2)
raspi_gpio_pin ce2_pin;
raspi_pin_select ce2_mode;
#endif
};
struct rt_sw_spi_cs
{
rt_uint32_t pin;
};
struct rt_spi
struct raspi_spi_device
{
char *device_name;
struct rt_spi_bus *spi_bus;
struct rt_spi_hw_config *hwcfg;
struct rt_spi_configuration *cfg;
struct rt_spi_device *spi_device;
raspi_gpio_pin cs_pin;
};
static rt_err_t raspi_hostspi_init(struct rt_spi_configuration *cfg)
{
volatile rt_uint32_t addr = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_CS;
//volatile rt_uint32_t fifo = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_FIFO;
// spi clear fifo
bcm283x_peri_set_bits(addr, BCM283X_SPI0_CS_CLEAR, BCM283X_SPI0_CS_CLEAR);
// /* Set TA = 1 */
// bcm2835_peri_set_bits(addr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA);
/* Mask in the CPO and CPHA bits of CS */
bcm283x_peri_set_bits(addr, (rt_uint32_t)(cfg->mode << 2), BCM283X_SPI0_CS_CPOL | BCM283X_SPI0_CS_CPHA);
//chipSelect
bcm283x_peri_set_bits(addr, BCM283X_SPI_CS0, BCM283X_SPI0_CS_CS);
rt_uint8_t shift = 21 + BCM283X_SPI_CS0;
/* Mask in the appropriate CSPOLn bit */
bcm283x_peri_set_bits(addr, LOW << shift, 1 << shift);
if(cfg->max_hz > BSP_SPI_MAX_HZ)
{
cfg->max_hz = BSP_SPI_MAX_HZ;
}
volatile rt_uint32_t clk_addr = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_CLK;
bcm283x_peri_write(clk_addr, cfg->max_hz);
return RT_EOK;
}
static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
{
RT_ASSERT(cfg != RT_NULL);
RT_ASSERT(device != RT_NULL);
rt_uint16_t divider;
struct rt_spi *hspi = (struct rt_spi *)&device->bus->parent;
hspi->cfg = cfg;
// spi clear fifo
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CLEAR;
raspi_hostspi_init(cfg);
if (cfg->mode & RT_SPI_CPOL)
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CPOL;
if (cfg->mode & RT_SPI_CPHA)
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CPHA;
if (cfg->mode & RT_SPI_CS_HIGH)
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CSPOL;
//set clk
if (cfg->max_hz > BSP_SPI_MAX_HZ)
cfg->max_hz = BSP_SPI_MAX_HZ;
divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz);
divider &= 0xFFFE;
BCM283X_SPI0_CLK(BCM283X_SPI0_BASE) = divider;
return RT_EOK;
}
rt_uint8_t correct_order(rt_uint8_t b)
rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag)
{
if (bcm2835_spi_bit_order == BCM283X_SPI_BIT_ORDER_LSBFIRST)
return bcm2835_byte_reverse_table[b];
if (flag)
return raspi_byte_reverse_table[b];
else
return b;
}
static rt_err_t spi_transfernb(rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len)
static rt_err_t spi_transfernb(rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag)
{
volatile rt_uint32_t paddr = SPI0_BASE_ADDR + BCM283X_SPI0_CS;
volatile rt_uint32_t fifo = SPI0_BASE_ADDR + BCM283X_SPI0_FIFO;
rt_uint32_t TXCnt=0;
rt_uint32_t RXCnt=0;
/* Clear TX and RX fifos */
bcm283x_peri_set_bits(paddr, BCM283X_SPI0_CS_CLEAR, BCM283X_SPI0_CS_CLEAR);
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (BCM283X_SPI0_CS_CLEAR & BCM283X_SPI0_CS_CLEAR);
/* Set TA = 1 */
bcm283x_peri_set_bits(paddr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA);
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (BCM283X_SPI0_CS_TA & BCM283X_SPI0_CS_TA);
/* Use the FIFO's to reduce the interbyte times */
while ((TXCnt < len) || (RXCnt < len))
{
/* TX fifo not full, so add some more bytes */
while (((bcm283x_peri_read(paddr) & BCM283X_SPI0_CS_TXD)) && (TXCnt < len))
while (((BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_TXD)) && (TXCnt < len))
{
bcm283x_peri_write_nb(fifo, correct_order(tbuf[TXCnt]));
BCM283X_SPI0_FIFO(BCM283X_SPI0_BASE) = correct_order(tbuf[TXCnt],flag);
TXCnt++;
}
/* Rx fifo not empty, so get the next received bytes */
while (((bcm283x_peri_read(paddr) & BCM283X_SPI0_CS_RXD)) && (RXCnt < len))
while (((BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_RXD)) && (RXCnt < len))
{
rbuf[RXCnt] = correct_order(bcm283x_peri_read_nb(fifo));
rbuf[RXCnt] = correct_order(BCM283X_SPI0_FIFO(BCM283X_SPI0_BASE),flag);
RXCnt++;
}
}
/* Wait for DONE to be set */
while (!(bcm283x_peri_read_nb(paddr) & BCM283X_SPI0_CS_DONE));
while (!(BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_DONE));
/* Set TA = 0, and also set the barrier */
bcm283x_peri_set_bits(paddr, 0, BCM283X_SPI0_CS_TA);
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (0 & BCM283X_SPI0_CS_TA);
return RT_EOK;
}
static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
rt_err_t res;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(device->parent.user_data != RT_NULL);
RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
struct rt_spi *hspi = (struct rt_spi *)&device->bus->parent;
/* only send data */
if (message->recv_buf == RT_NULL)
{
if (message->cs_take)
{
bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0);
}
res = spi_transfernb((rt_uint8_t *)message->send_buf, RT_NULL,(rt_int32_t)message->length);
if (message->cs_release)
{
bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1);
rt_err_t res;
rt_uint8_t flag;
struct rt_spi_configuration config = device->config;
raspi_gpio_pin cs_pin = (raspi_gpio_pin)device->parent.user_data;
}
if (res != RT_EOK)
return RT_ERROR;
}
/* only receive data */
if (message->send_buf == RT_NULL)
{
if (message->cs_take)
{
bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0);
}
res = spi_transfernb(RT_NULL,(rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length);
if (message->cs_release)
{
bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
/* send & receive */
if (config.mode & RT_SPI_MSB)
flag = 0;
else
{
if (message->cs_take)
{
bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0);
}
res = spi_transfernb((rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
(rt_int32_t)message->length);
if (message->cs_release)
{
bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
flag = 1;
if (message->cs_take);
// (config.mode & RT_SPI_CS_HIGH)?
// spi_gpio_write(cs_pin, 1):
// spi_gpio_write(cs_pin, 0);
/* deal data */
res = spi_transfernb((rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
(rt_int32_t)message->length, flag);
if (message->cs_release)
(config.mode & RT_SPI_CS_HIGH)?
spi_gpio_write(cs_pin, 0):
spi_gpio_write(cs_pin, 1);
if (res != RT_EOK)
return RT_ERROR;
return message->length;
}
rt_err_t raspi_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device)
{
rt_err_t ret;
rt_int16_t gpio_pin;
struct rt_spi_device *spi_device;
struct rt_sw_spi_cs *cs_pin;
gpio_pin = phypin_index[pin].bcm_id;
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
cs_pin = (struct rt_sw_spi_cs *)rt_malloc(sizeof(struct rt_sw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
cs_pin->pin = gpio_pin;
ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
RT_ASSERT(device != RT_NULL);
ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device->cs_pin));
return ret;
}
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
rt_uint16_t spi_clockdivider(rt_uint32_t speed_hz)
rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg)
{
rt_uint16_t divider;
GPIO_FSEL(hwcfg->sclk_pin, hwcfg->sclk_mode);
GPIO_FSEL(hwcfg->miso_pin, hwcfg->miso_mode);
GPIO_FSEL(hwcfg->mosi_pin, hwcfg->mosi_mode);
if (speed_hz < (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MIN)
{
speed_hz = (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MIN;
}
else if (speed_hz > (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MAX)
{
speed_hz = (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MAX;
}
#if defined (BSP_USING_SPI0_DEVICE0)
GPIO_FSEL(hwcfg->ce0_pin, hwcfg->ce0_mode);
#endif
divider = (rt_uint16_t) DIV_ROUND_UP(BCM283X_CORE_CLK_HZ, 2 * speed_hz) - 1;
#if defined (BSP_USING_SPI0_DEVICE1)
GPIO_FSEL(hwcfg->ce1_pin, hwcfg->ce1_mode);
#endif
if (divider > (rt_uint16_t) BCM283X_AUX_SPI_CNTL0_SPEED_MAX)
{
return (rt_uint16_t) BCM283X_AUX_SPI_CNTL0_SPEED_MAX;
}
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) = 0;
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) = BCM283X_SPI0_CS_CLEAR;
return divider;
}
//enable chip select
#if defined (BSP_USING_SPI0_DEVICE0)
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= 0;
#endif
rt_err_t raspi_spi_hw_init(struct rt_spi_hw_config *hwcfg)
{
volatile rt_uint32_t enable = PER_BASE + BCM283X_AUX_BASE + BCM283X_AUX_ENABLE;
volatile rt_uint32_t cntl0 = PER_BASE + BCM283X_SPI1_BASE + BCM283X_AUX_SPI_CNTL0;
volatile rt_uint32_t cntl1 = PER_BASE + BCM283X_SPI1_BASE + BCM283X_AUX_SPI_CNTL1;
bcm283x_gpio_fsel(hwcfg->sclk_pin, hwcfg->sclk_mode);
bcm283x_gpio_fsel(hwcfg->miso_pin, hwcfg->miso_mode);
bcm283x_gpio_fsel(hwcfg->mosi_pin, hwcfg->mosi_mode);
bcm283x_gpio_fsel(hwcfg->cs_pin, hwcfg->cs_mode);
hwcfg->clk_div = spi_clockdivider(1000000); // Default 1MHz SPI
bcm283x_peri_write(enable, BCM283X_AUX_ENABLE_SPI0);
bcm283x_peri_write(cntl1, 0);
bcm283x_peri_write(cntl0, BCM283X_AUX_SPI_CNTL0_CLEARFIFO);
#if defined (BSP_USING_SPI0_DEVICE1)
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= 0x2;
#endif
#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CS;
#endif
return RT_EOK;
}
const static struct rt_spi_ops raspi_spi_ops =
static struct rt_spi_ops raspi_spi_ops =
{
.configure = raspi_spi_configure,
.xfer = raspi_spi_xfer
};
#if defined (BSP_USING_SPI0)
#define SPI0BUS_NAME "spi0.0"
#if defined (BSP_USING_SPI0_BUS)
#define SPI0_BUS_NAME "spi0"
#define SPI0_DEVICE0_NAME "spi0.0"
#define SPI0_DEVICE1_NAME "spi0.1"
struct rt_spi spi0;
struct rt_spi_bus raspi_spi0_bus =
{
.ops = &raspi_spi_ops,
.parent.user_data = &spi0
};
struct rt_spi_bus spi0_bus;
struct rt_spi_hw_config raspi_spi0_hw =
#if defined (BSP_USING_SPI0_DEVICE0)
struct rt_spi_device spi0_device0;
#endif
#if defined (BSP_USING_SPI0_DEVICE1)
static struct rt_spi_device spi0_device1;
#endif
struct raspi_spi_hw_config raspi_spi0_hw =
{
.sclk_pin = BCM_GPIO_PIN_11,
.spi_num = 0,
.sclk_pin = RPI_GPIO_P1_23,
.sclk_mode = BCM283X_GPIO_FSEL_ALT0,
.mosi_pin = BCM_GPIO_PIN_10,
.mosi_pin = RPI_GPIO_P1_19,
.mosi_mode = BCM283X_GPIO_FSEL_ALT0,
.miso_pin = BCM_GPIO_PIN_9,
.miso_pin = RPI_GPIO_P1_21,
.miso_mode = BCM283X_GPIO_FSEL_ALT0,
.cs_pin = BCM_GPIO_PIN_8,
.cs_mode = BCM283X_GPIO_FSEL_ALT0,
.spi_base = (PER_BASE + BCM283X_SPI0_BASE),
.clk_div = 0,
};
struct rt_spi spi0 =
{
.device_name = SPI0BUS_NAME,
.spi_bus = &raspi_spi0_bus,
.hwcfg = &raspi_spi0_hw,
};
#if defined (BSP_USING_SPI0_DEVICE0)
.ce0_pin = RPI_GPIO_P1_24,
.ce0_mode = BCM283X_GPIO_FSEL_ALT0,
#endif
#if defined (BSP_USING_SPI1)
#define SPI1BUS_NAME "spi0.1"
struct rt_spi spi1;
struct rt_spi_bus raspi_spi1_bus =
{
.ops = &raspi_spi_ops,
.parent.user_data = &spi1
};
struct rt_spi_hw_config raspi_spi1_hw =
{
.sclk_pin = BCM_GPIO_PIN_11,
.sclk_mode = BCM283X_GPIO_FSEL_ALT0,
.mosi_pin = BCM_GPIO_PIN_10,
.mosi_mode = BCM283X_GPIO_FSEL_ALT0,
.miso_pin = BCM_GPIO_PIN_9,
.miso_mode = BCM283X_GPIO_FSEL_ALT0,
.cs_pin = BCM_GPIO_PIN_7,
.cs_mode = BCM283X_GPIO_FSEL_ALT0,
.spi_base = (PER_BASE + BCM283X_SPI0_BASE),
.clk_div = 0,
};
struct rt_spi spi1 =
{
.device_name = SPI1BUS_NAME,
.spi_bus = &raspi_spi1_bus,
.hwcfg = &raspi_spi1_hw,
#if defined (BSP_USING_SPI0_DEVICE1)
.ce1_pin = RPI_GPIO_P1_26,
.ce1_mode = BCM283X_GPIO_FSEL_ALT0,
#endif
};
#endif
int rt_hw_spi_bus_init(void)
int rt_hw_spi_init(void)
{
#if defined (BSP_USING_SPI0)
raspi_spi_hw_init(spi0.hwcfg);
rt_spi_bus_register(spi0.spi_bus, spi0.device_name, spi0.spi_bus->ops);
#if defined (BSP_USING_SPI0_BUS)
raspi_spi_hw_init(&raspi_spi0_hw);
rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops);
#if defined (BSP_USING_SPI0_DEVICE0)
struct raspi_spi_device raspi_spi0_device0 =
{
.device_name = SPI0_DEVICE0_NAME,
.spi_bus = &spi0_bus,
.spi_device = &spi0_device0,
.cs_pin = raspi_spi0_hw.ce0_pin,
};
raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0);
#endif
#if defined (BSP_USING_SPI1)
raspi_spi_hw_init(spi1.hwcfg);
rt_spi_bus_register(spi1.spi_bus, spi1.device_name, spi1.spi_bus->ops);
#if defined (BSP_USING_SPI0_DEVICE1)
struct raspi_spi_device raspi_spi0_device1 =
{
.device_name = SPI0_DEVICE1_NAME,
.spi_bus = &spi0_bus,
.spi_device = &spi0_device1,
.cs_pin = raspi_spi0_hw.ce1_pin,
};
raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1);
#endif
#endif
return RT_EOK;
}
INIT_PREV_EXPORT(rt_hw_spi_bus_init);
INIT_DEVICE_EXPORT(rt_hw_spi_init);
#endif

128
bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
View File

@ -12,57 +12,91 @@
#define __DRV_SPI_H__
#include <rtthread.h>
#include <rthw.h>
#include "bcm283x.h"
#include <rtdevice.h>
#include <drivers/spi.h>
#include "raspi.h"
//#include <drivers/spi.h>
#include "board.h"
#define SPI0_BASE_ADDR (PER_BASE + BCM283X_SPI0_BASE)
#define SPI_CORE_CLK 250000000U
#define SPI_CS 0x00
#define SPI_CS_LEN_LONG (1 << 25)
#define SPI_CS_DMA_LEN (1 << 24)
#define SPI_CS_CSPOL2 (1 << 23)
#define SPI_CS_CSPOL1 (1 << 22)
#define SPI_CS_CSPOL0 (1 << 21)
#define SPI_CS_RXF (1 << 20)
#define SPI_CS_RXR (1 << 19)
#define SPI_CS_TXD (1 << 18)
#define SPI_CS_RXD (1 << 17)
#define SPI_CS_DONE (1 << 16)
#define SPI_CS_LEN (1 << 13)
#define SPI_CS_REN (1 << 12)
#define SPI_CS_ADCS (1 << 11)
#define SPI_CS_INTR (1 << 10)
#define SPI_CS_INTD (1 << 9)
#define SPI_CS_DMAEN (1 << 8)
#define SPI_CS_TA (1 << 7)
#define SPI_CS_CSPOL (1 << 6)
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
#define SPI_CS_CPOL (1 << 3)
#define SPI_CS_CPHA (1 << 2)
#define SPI_CS_MASK 0x3
#define SPI_FIFO 0x04
#define SPI_CLK 0x08
#define SPI_CLK_MASK 0xffff
#define SPI_DLEN 0x0c
#define SPI_DLEN_MASK 0xffff
#define SPI_LTOH 0x10
#define SPI_LTOH_MASK 0xf
#define SPI_DC 0x14
#define SPI_DC_RPANIC_SHIFT 24
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
#define SPI_DC_RDREQ_SHIFT 16
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
#define SPI_DC_TPANIC_SHIFT 8
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
#define SPI_DC_TDREQ_SHIFT 0
#define SPI_DC_TDREQ_MASK 0xff
static rt_uint8_t raspi_byte_reverse_table[] =
{
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
};
int rt_hw_spi_bus_init(void);
#define SPI_CORE_CLK 250000000U
#define SPI_CS 0x00
#define SPI_CS_LEN_LONG (1 << 25)
#define SPI_CS_DMA_LEN (1 << 24)
#define SPI_CS_CSPOL2 (1 << 23)
#define SPI_CS_CSPOL1 (1 << 22)
#define SPI_CS_CSPOL0 (1 << 21)
#define SPI_CS_RXF (1 << 20)
#define SPI_CS_RXR (1 << 19)
#define SPI_CS_TXD (1 << 18)
#define SPI_CS_RXD (1 << 17)
#define SPI_CS_DONE (1 << 16)
#define SPI_CS_LEN (1 << 13)
#define SPI_CS_REN (1 << 12)
#define SPI_CS_ADCS (1 << 11)
#define SPI_CS_INTR (1 << 10)
#define SPI_CS_INTD (1 << 9)
#define SPI_CS_DMAEN (1 << 8)
#define SPI_CS_TA (1 << 7)
#define SPI_CS_CSPOL (1 << 6)
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
#define SPI_CS_CPOL (1 << 3)
#define SPI_CS_CPHA (1 << 2)
#define SPI_CS_MASK 0x3
#define SPI_FIFO 0x04
#define SPI_CLK 0x08
#define SPI_CLK_MASK 0xffff
#define SPI_DLEN 0x0c
#define SPI_DLEN_MASK 0xffff
#define SPI_LTOH 0x10
#define SPI_LTOH_MASK 0xf
#define SPI_DC 0x14
#define SPI_DC_RPANIC_SHIFT 24
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
#define SPI_DC_RDREQ_SHIFT 16
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
#define SPI_DC_TPANIC_SHIFT 8
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
#define SPI_DC_TDREQ_SHIFT 0
#define SPI_DC_TDREQ_MASK 0xff
int rt_hw_spi_init(void);
#endif

15
bsp/raspberry-pi/raspi3-64/rtconfig.h
View File

@ -102,6 +102,9 @@
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_HWTIMER
#define RT_USING_I2C
#define RT_I2C_DEBUG
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 2048
@ -110,6 +113,7 @@
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_SDIO_DEBUG
#define RT_USING_SPI
#define RT_USING_WDT
/* Using USB */
@ -179,12 +183,6 @@
/* samples: kernel and components samples */
/* Privated Packages of RealThread */
/* Network Utilities */
#define BCM2836_SOC
/* Hardware Drivers Config */
@ -198,6 +196,11 @@
#define BSP_USING_SYSTIMER
#define RT_USING_SYSTIMER1
#define RT_USING_SYSTIMER3
#define BSP_USING_I2C
#define BSP_USING_I2C1
#define BSP_USING_SPI
#define BSP_USING_SPI0_BUS
#define BSP_USING_SPI0_DEVICE0
#define BSP_USING_WDT
#define BSP_USING_SDIO
#define BSP_USING_SDIO0

1
libcpu/aarch64/cortex-a53/SConscript
View File

@ -7,6 +7,7 @@ context_gcc.S
vector_gcc.S
entry_point.S
cpu_gcc.S
cache.S
''')
CPPPATH = [cwd]

151
libcpu/aarch64/cortex-a53/cache.S Normal file
View File

@ -0,0 +1,151 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-03-17 bigmagic first version
*/
/*
* void __asm_dcache_level(level)
*
* flush or invalidate one level cache.
*
* x0: cache level
* x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
.globl __asm_dcache_level
__asm_dcache_level:
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
clz w5, w3 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
/* x4 <- number of cache sets - 1 */
/* x5 <- bit position of #ways */
loop_set:
mov x6, x3 /* x6 <- working copy of #ways */
loop_way:
lsl x7, x6, x5
orr x9, x12, x7 /* map way and level to cisw value */
lsl x7, x4, x2
orr x9, x9, x7 /* map set number to cisw value */
tbz w1, #0, 1f
dc isw, x9
b 2f
1: dc cisw, x9 /* clean & invalidate by set/way */
2: subs x6, x6, #1 /* decrement the way */
b.ge loop_way
subs x4, x4, #1 /* decrement the set */
b.ge loop_set
ret
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
* x0: 0 clean & invalidate, 1 invalidate only
*
* flush or invalidate all data cache by SET/WAY.
*/
.globl __asm_dcache_all
__asm_dcache_all:
mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
lsr x11, x10, #24
and x11, x11, #0x7 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
/* x0 <- cache level */
/* x10 <- clidr_el1 */
/* x11 <- loc */
/* x15 <- return address */
loop_level:
lsl x12, x0, #1
add x12, x12, x0 /* x0 <- tripled cache level */
lsr x12, x10, x12
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
b.lt skip /* skip if no cache or icache */
bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
b.gt loop_level
mov x0, #0
msr csselr_el1, x0 /* restore csselr_el1 */
dsb sy
isb
mov lr, x15
finished:
ret
.globl __asm_flush_dcache_all
__asm_flush_dcache_all:
mov x0, #0
b __asm_dcache_all
.globl __asm_invalidate_dcache_all
__asm_invalidate_dcache_all:
mov x0, #0x1
b __asm_dcache_all
/*
* void __asm_flush_dcache_range(start, end)
*
* clean & invalidate data cache in the range
*
* x0: start address
* x1: end address
*/
.globl __asm_flush_dcache_range
__asm_flush_dcache_range:
mrs x3, ctr_el0
lsr x3, x3, #16
and x3, x3, #0xf
mov x2, #4
lsl x2, x2, x3 /* cache line size */
/* x2 <- minimal cache line size in cache system */
sub x3, x2, #1
bic x0, x0, x3
1: dc civac, x0 /* clean & invalidate data or unified cache */
add x0, x0, x2
cmp x0, x1
b.lo 1b
dsb sy
ret
/*
* void __asm_invalidate_icache_all(void)
*
* invalidate all tlb entries.
*/
.globl __asm_invalidate_icache_all
__asm_invalidate_icache_all:
ic ialluis
isb sy
ret
.globl __asm_flush_l3_cache
__asm_flush_l3_cache:
mov x0, #0 /* return status as success */
ret

94
libcpu/aarch64/cortex-a53/mmu.c
View File

@ -9,6 +9,7 @@
*/
#include <mmu.h>
#include <stddef.h>
#include <rthw.h>
#define TTBR_CNP 1
@ -35,6 +36,13 @@ static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
int free_idx = 1;
void __asm_invalidate_icache_all(void);
void __asm_flush_dcache_all(void);
int __asm_flush_l3_cache(void);
void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
void __asm_invalidate_dcache_all(void);
void __asm_invalidate_icache_all(void);
void mmu_memset(char *dst, char v, size_t len)
{
while (len--)
@ -50,6 +58,20 @@ static unsigned long get_free_page(void)
return (unsigned long)(main_tbl + __page_off);
}
static inline unsigned int get_sctlr(void)
{
unsigned int val;
asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
return val;
}
static inline void set_sctlr(unsigned int val)
{
asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
asm volatile("isb");
}
void mmu_init(void)
{
unsigned long val64;
@ -101,6 +123,9 @@ void mmu_enable(void)
__asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
val32 |= 0x1005; //enable mmu, I C M
__asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
rt_hw_icache_enable();
rt_hw_dcache_enable();
}
static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr)
@ -271,3 +296,72 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned
map_region(va, pa, size, attr);
}
void rt_hw_dcache_enable(void)
{
if (!(get_sctlr() & CR_M))
{
rt_kprintf("please init mmu!\n");
}
else
{
set_sctlr(get_sctlr() | CR_C);
}
}
void rt_hw_dcache_flush_all(void)
{
int ret;
__asm_flush_dcache_all();
ret = __asm_flush_l3_cache();
if (ret)
{
rt_kprintf("flushing dcache returns 0x%x\n", ret);
}
else
{
rt_kprintf("flushing dcache successfully.\n");
}
}
void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
{
__asm_flush_dcache_range(start_addr, start_addr + size);
}
void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
{
__asm_flush_dcache_range(start_addr, start_addr + size);
}
void rt_hw_dcache_invalidate_all(void)
{
__asm_invalidate_dcache_all();
}
void rt_hw_dcache_disable(void)
{
/* if cache isn't enabled no need to disable */
if(!(get_sctlr() & CR_C))
{
rt_kprintf("need enable cache!\n");
return;
}
set_sctlr(get_sctlr() & ~CR_C);
}
//icache
void rt_hw_icache_enable(void)
{
__asm_invalidate_icache_all();
set_sctlr(get_sctlr() | CR_I);
}
void rt_hw_icache_invalidate_all(void)
{
__asm_invalidate_icache_all();
}
void rt_hw_icache_disable(void)
{
set_sctlr(get_sctlr() & ~CR_I);
}

47
libcpu/aarch64/cortex-a53/mmu.h
View File

@ -11,6 +11,37 @@
#ifndef __MMU_H__
#define __MMU_H__
/*
* CR1 bits (CP#15 CR1)
*/
#define CR_M (1 << 0) /* MMU enable */
#define CR_A (1 << 1) /* Alignment abort enable */
#define CR_C (1 << 2) /* Dcache enable */
#define CR_W (1 << 3) /* Write buffer enable */
#define CR_P (1 << 4) /* 32-bit exception handler */
#define CR_D (1 << 5) /* 32-bit data address range */
#define CR_L (1 << 6) /* Implementation defined */
#define CR_B (1 << 7) /* Big endian */
#define CR_S (1 << 8) /* System MMU protection */
#define CR_R (1 << 9) /* ROM MMU protection */
#define CR_F (1 << 10) /* Implementation defined */
#define CR_Z (1 << 11) /* Implementation defined */
#define CR_I (1 << 12) /* Icache enable */
#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
#define CR_RR (1 << 14) /* Round Robin cache replacement */
#define CR_L4 (1 << 15) /* LDR pc can set T bit */
#define CR_DT (1 << 16)
#define CR_IT (1 << 18)
#define CR_ST (1 << 19)
#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
#define CR_U (1 << 22) /* Unaligned access operation */
#define CR_XP (1 << 23) /* Extended page tables */
#define CR_VE (1 << 24) /* Vectored interrupts */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
#define CR_TRE (1 << 28) /* TEX remap enable */
#define CR_AFE (1 << 29) /* Access flag enable */
#define CR_TE (1 << 30) /* Thumb exception enable */
#define MMU_LEVEL_MASK 0x1ffUL
#define MMU_MAP_ERROR_VANOTALIGN -1
#define MMU_MAP_ERROR_PANOTALIGN -2
@ -20,7 +51,7 @@
#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000)
#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000)
void mmu_init(void);
@ -30,4 +61,18 @@ int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long at
void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
//dcache
void rt_hw_dcache_enable(void);
void rt_hw_dcache_flush_all(void);
void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
void rt_hw_dcache_invalidate_all(void);
void rt_hw_dcache_disable(void);
//icache
void rt_hw_icache_enable(void);
void rt_hw_icache_invalidate_all(void);
void rt_hw_icache_disable(void);
#endif /*__MMU_H__*/

168
libcpu/arm/cortex-a53/cp15.h
View File

@ -1,168 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
*/
#include "raspi.h"
#ifndef __CP15_H__
#define __CP15_H__
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#define __WFI() __asm__ volatile ("wfi":::"memory")
#define __WFE() __asm__ volatile ("wfe":::"memory")
#define __SEV() __asm__ volatile ("sev")
__STATIC_FORCEINLINE void __ISB(void)
{
__asm__ volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__asm__ volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__asm__ volatile ("dmb 0xF":::"memory");
}
#ifdef RT_USING_SMP
static inline void send_ipi_msg(int cpu, int ipi_vector)
{
IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
}
static inline void setup_bootstrap_addr(int cpu, int addr)
{
CORE_MAILBOX3_SET(cpu) = addr;
}
static inline void enable_cpu_ipi_intr(int cpu)
{
COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
}
static inline void enable_cpu_timer_intr(int cpu)
{
CORETIMER_INTCTL(cpu) = 0x8;
}
static inline void enable_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 1;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline void disable_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 0;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline void mask_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 2;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline void unmask_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 1;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline rt_uint64_t read_cntvct(void)
{
rt_uint32_t val,val1;
asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
return (val);
}
static inline rt_uint64_t read_cntvoff(void)
{
rt_uint64_t val;
asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
return (val);
}
static inline rt_uint32_t read_cntv_tval(void)
{
rt_uint32_t val;
asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
return val;
}
static inline void write_cntv_tval(rt_uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
return;
}
static inline rt_uint32_t read_cntfrq(void)
{
rt_uint32_t val;
asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
return val;
}
static inline rt_uint32_t read_cntctrl(void)
{
rt_uint32_t val;
asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
return val;
}
static inline uint32_t write_cntctrl(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
return val;
}
#endif
unsigned long rt_cpu_get_smp_id(void);
void rt_cpu_mmu_disable(void);
void rt_cpu_mmu_enable(void);
void rt_cpu_tlb_set(volatile unsigned long*);
void rt_cpu_dcache_clean_flush(void);
void rt_cpu_icache_flush(void);
void rt_cpu_vector_set_base(unsigned int addr);
void rt_hw_mmu_init(void);
void rt_hw_vector_init(void);
void set_timer_counter(unsigned int counter);
void set_timer_control(unsigned int control);
#endif

91
libcpu/arm/cortex-a53/cpu.c
View File

@ -1,91 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
* 2019-07-28 zdzn add smp support
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#include "cp15.h"
int rt_hw_cpu_id(void)
{
int cpu_id;
__asm__ volatile (
"mrc p15, 0, %0, c0, c0, 5"
:"=r"(cpu_id)
);
cpu_id &= 0xf;
return cpu_id;
};
#ifdef RT_USING_SMP
void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
{
lock->slock = 0;
}
void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
{
unsigned long tmp;
unsigned long newval;
rt_hw_spinlock_t lockval;
__asm__ __volatile__(
"pld [%0]"
::"r"(&lock->slock)
);
__asm__ __volatile__(
"1: ldrex %0, [%3]\n"
" add %1, %0, %4\n"
" strex %2, %1, [%3]\n"
" teq %2, #0\n"
" bne 1b"
: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
: "r" (&lock->slock), "I" (1 << 16)
: "cc");
while (lockval.tickets.next != lockval.tickets.owner)
{
__WFE();
lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
}
__DMB();
}
void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
{
__DMB();
lock->tickets.owner++;
__DSB();
__SEV();
}
#endif /*RT_USING_SMP*/
/**
* @addtogroup ARM CPU
*/
/*@{*/
/** shutdown CPU */
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/

186
libcpu/arm/cortex-a53/interrupt.c
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@ -1,186 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/3 Bernard first version
* 2019-07-28 zdzn add smp support
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
*/
#include <rthw.h>
#include <rtthread.h>
#include "cp15.h"
#include <board.h>
#define MAX_HANDLERS 72
#ifdef RT_USING_SMP
#define rt_interrupt_nest rt_cpu_self()->irq_nest
#else
extern volatile rt_uint8_t rt_interrupt_nest;
#endif
const unsigned int VECTOR_BASE = 0x00;
extern void rt_cpu_vector_set_base(unsigned int addr);
extern int system_vectors;
void rt_hw_vector_init(void)
{
rt_cpu_vector_set_base((unsigned int)&system_vectors);
}
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
extern int system_vectors;
static void default_isr_handler(int vector, void *param)
{
#ifdef RT_USING_SMP
rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
#else
rt_kprintf("unhandled irq: %d\n",vector);
#endif
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_uint32_t index;
/* mask all of interrupts */
IRQ_DISABLE_BASIC = 0x000000ff;
IRQ_DISABLE1 = 0xffffffff;
IRQ_DISABLE2 = 0xffffffff;
for (index = 0; index < MAX_HANDLERS; index ++)
{
isr_table[index].handler = default_isr_handler;
isr_table[index].param = NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
isr_table[index].counter = 0;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
if (vector < 32)
{
IRQ_DISABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_DISABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_DISABLE_BASIC = (1 << vector);
}
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
if (vector < 32)
{
IRQ_ENABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_ENABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_ENABLE_BASIC = (1 << vector);
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
{
__DSB();
if (cpu_mask & 0x1)
{
send_ipi_msg(0, ipi_vector);
}
if (cpu_mask & 0x2)
{
send_ipi_msg(1, ipi_vector);
}
if (cpu_mask & 0x4)
{
send_ipi_msg(2, ipi_vector);
}
if (cpu_mask & 0x8)
{
send_ipi_msg(3, ipi_vector);
}
__DSB();
}
#endif
#ifdef RT_USING_SMP
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
}
#endif

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libcpu/arm/cortex-a53/interrupt.h
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#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <board.h>
#define INT_IRQ 0x00
#define INT_FIQ 0x01
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#endif

188
libcpu/arm/cortex-a53/mmu.c
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-01-10 bernard porting to AM1808
* 2019-07-28 zdzn add smp support
*/
#include "mmu.h"
/* dump 2nd level page table */
void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
{
int i;
int fcnt = 0;
for (i = 0; i < 256; i++)
{
rt_uint32_t pte2 = ptb[i];
if ((pte2 & 0x3) == 0)
{
if (fcnt == 0)
rt_kprintf(" ");
rt_kprintf("%04x: ", i);
fcnt++;
if (fcnt == 16)
{
rt_kprintf("fault\n");
fcnt = 0;
}
continue;
}
if (fcnt != 0)
{
rt_kprintf("fault\n");
fcnt = 0;
}
rt_kprintf(" %04x: %x: ", i, pte2);
if ((pte2 & 0x3) == 0x1)
{
rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
((pte2 >> 7) | (pte2 >> 4))& 0xf,
(pte2 >> 15) & 0x1,
((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
}
else
{
rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
}
}
}
void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
{
int i;
int fcnt = 0;
rt_kprintf("page table@%p\n", ptb);
for (i = 0; i < 1024*4; i++)
{
rt_uint32_t pte1 = ptb[i];
if ((pte1 & 0x3) == 0)
{
rt_kprintf("%03x: ", i);
fcnt++;
if (fcnt == 16)
{
rt_kprintf("fault\n");
fcnt = 0;
}
continue;
}
if (fcnt != 0)
{
rt_kprintf("fault\n");
fcnt = 0;
}
rt_kprintf("%03x: %08x: ", i, pte1);
if ((pte1 & 0x3) == 0x3)
{
rt_kprintf("LPAE\n");
}
else if ((pte1 & 0x3) == 0x1)
{
rt_kprintf("pte,ns:%d,domain:%d\n",
(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
/*
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
* - 0x80000000 + 0xC0000000));
*/
}
else if (pte1 & (1 << 18))
{
rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
(pte1 >> 19) & 0x1,
((pte1 >> 13) | (pte1 >> 10))& 0xf,
(pte1 >> 4) & 0x1,
((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
}
else
{
rt_kprintf("section,ns:%d,ap:%x,"
"xn:%d,texcb:%02x,domain:%d\n",
(pte1 >> 19) & 0x1,
((pte1 >> 13) | (pte1 >> 10))& 0xf,
(pte1 >> 4) & 0x1,
(((pte1 & (0x7 << 12)) >> 10) |
((pte1 & 0x0c) >> 2)) & 0x1f,
(pte1 >> 5) & 0xf);
}
}
}
/* level1 page table, each entry for 1MB memory. */
volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
rt_uint32_t vaddrEnd,
rt_uint32_t paddrStart,
rt_uint32_t attr)
{
volatile rt_uint32_t *pTT;
volatile int i, nSec;
pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
for (i = 0; i <= nSec; i++)
{
*pTT = attr | (((paddrStart >> 20) + i) << 20);
pTT++;
}
}
unsigned long rt_hw_set_domain_register(unsigned long domain_val)
{
unsigned long old_domain;
asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
return old_domain;
}
void rt_hw_init_mmu_table()
{
/* set page table */
/* 4G 1:1 memory */
rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
/* IO memory region */
rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
}
void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
rt_uint32_t size,
rt_uint32_t paddrStart, rt_uint32_t attr)
{
rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
#ifndef RT_USING_SMP
rt_cpu_dcache_clean_flush();
rt_cpu_icache_flush();
#endif
}
void rt_hw_mmu_init(void)
{
rt_cpu_dcache_clean_flush();
rt_cpu_icache_flush();
rt_hw_cpu_dcache_disable();
rt_hw_cpu_icache_disable();
rt_cpu_mmu_disable();
/*rt_hw_cpu_dump_page_table(MMUTable);*/
rt_hw_set_domain_register(0x55555555);
rt_cpu_tlb_set(MMUTable);
rt_cpu_mmu_enable();
rt_hw_cpu_icache_enable();
rt_hw_cpu_dcache_enable();
}