Merge pull request #748 from TanekLiang/master
[bsp] update RCC initial for system
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commit
9c44022502
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@ -40,20 +40,6 @@ void NVIC_Configuration(void)
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// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
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// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
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}
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}
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/**
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* @brief Inserts a delay time.
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* @param nCount: specifies the delay time length.
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* @retval None
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*/
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static void Delay(__IO uint32_t nCount)
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{
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/* Decrement nCount value */
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while (nCount != 0)
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{
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nCount--;
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}
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}
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/**
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/**
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* This RCC initial for system.
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* This RCC initial for system.
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* use HSE clock source
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* use HSE clock source
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@ -63,32 +49,39 @@ static void Delay(__IO uint32_t nCount)
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*/
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*/
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static void RCC_Configuration(void)
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static void RCC_Configuration(void)
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{
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{
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RCC_ClkInitTypeDef ClkInit = {0};
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RCC_OscInitTypeDef OscInit;
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RCC_OscInitTypeDef OscInit = {0};
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HAL_RCC_DeInit();
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HAL_RCC_DeInit();
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/* Enable HSI Oscillator and Activate PLL with HSI as source */
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OscInit.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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OscInit.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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OscInit.HSIState = RCC_HSI_ON;
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OscInit.HSIState = RCC_HSI_ON;
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OscInit.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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OscInit.PLL.PLLState = RCC_PLL_ON;
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OscInit.PLL.PLLState = RCC_PLL_ON;
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OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
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OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
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OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
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OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
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OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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HAL_RCC_OscConfig(&OscInit);
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if (HAL_RCC_OscConfig(&OscInit) != HAL_OK)
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{
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RT_ASSERT(RT_NULL);
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}
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RCC_ClkInitTypeDef ClkInit;
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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ClkInit.ClockType = RCC_CLOCKTYPE_SYSCLK |
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ClkInit.ClockType = RCC_CLOCKTYPE_SYSCLK |
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RCC_CLOCKTYPE_HCLK |
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RCC_CLOCKTYPE_HCLK |
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RCC_CLOCKTYPE_PCLK1 |
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RCC_CLOCKTYPE_PCLK1 |
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RCC_CLOCKTYPE_PCLK2;
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RCC_CLOCKTYPE_PCLK2;
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ClkInit.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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ClkInit.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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ClkInit.AHBCLKDivider = 0;
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ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1;
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ClkInit.APB1CLKDivider = 0;
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ClkInit.APB1CLKDivider = RCC_HCLK_DIV1;
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ClkInit.APB2CLKDivider = 0;
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ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_ClockConfig(&ClkInit, 1);
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if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK)
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{
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Delay(0x3FFFF);
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RT_ASSERT(RT_NULL);
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/* Update SystemCoreClock value from RCC configure */
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}
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SystemCoreClockUpdate();
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}
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}
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#ifdef PRINT_RCC_FREQ_INFO
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#ifdef PRINT_RCC_FREQ_INFO
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