From f537194d0146182510bdc14d60a236846c8507af Mon Sep 17 00:00:00 2001 From: tanek liang Date: Tue, 13 Jun 2017 23:44:45 +0800 Subject: [PATCH 1/5] [bsp] update RCC initial for system * set internal oscillator trimming value to default * replace integer constant by macro from HAL library * remove SystemCoreClockUpdate() because "SystemCoreClock" updated in HAL_RCC_ClockConfig() * remove delay() --- bsp/stm32l072/board/board.c | 40 +++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 3e029d722b..963ea5bbe9 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -40,18 +40,10 @@ void NVIC_Configuration(void) // NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); } -/** -* @brief Inserts a delay time. -* @param nCount: specifies the delay time length. -* @retval None -*/ -static void Delay(__IO uint32_t nCount) +void error_handler(void) { - /* Decrement nCount value */ - while (nCount != 0) - { - nCount--; - } + rt_kprintf("error_handler\n"); + while(1); } /** @@ -63,32 +55,36 @@ static void Delay(__IO uint32_t nCount) */ static void RCC_Configuration(void) { - - RCC_OscInitTypeDef OscInit; + RCC_ClkInitTypeDef ClkInit = {0}; + RCC_OscInitTypeDef OscInit = {0}; + HAL_RCC_DeInit(); + + /* Enable HSI Oscillator and Activate PLL with HSI as source */ OscInit.OscillatorType = RCC_OSCILLATORTYPE_HSI; OscInit.HSIState = RCC_HSI_ON; + OscInit.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; OscInit.PLL.PLLState = RCC_PLL_ON; OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; HAL_RCC_OscConfig(&OscInit); - RCC_ClkInitTypeDef ClkInit; + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ ClkInit.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; ClkInit.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - ClkInit.AHBCLKDivider = 0; - ClkInit.APB1CLKDivider = 0; - ClkInit.APB2CLKDivider = 0; - HAL_RCC_ClockConfig(&ClkInit, 1); - - Delay(0x3FFFF); - /* Update SystemCoreClock value from RCC configure */ - SystemCoreClockUpdate(); + ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1; + ClkInit.APB1CLKDivider = RCC_HCLK_DIV1; + ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) + { + error_handler(); + } } #ifdef PRINT_RCC_FREQ_INFO From 4978e340a901f89207bb45c2262afd772786a636 Mon Sep 17 00:00:00 2001 From: tanek liang Date: Wed, 14 Jun 2017 16:41:23 +0800 Subject: [PATCH 2/5] [bsp] replace error_handler() by RT_ASSERT(RT_NULL) --- bsp/stm32l072/board/board.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 963ea5bbe9..2d0b2841b7 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -66,9 +66,12 @@ static void RCC_Configuration(void) OscInit.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; OscInit.PLL.PLLState = RCC_PLL_ON; OscInit.PLL.PLLDIV = RCC_PLLDIV_2; - OscInit.PLL.PLLMUL = RCC_PLLMUL_4; + OscInit.PLL.PLLMUL = RCC_PLLMUL_48; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; - HAL_RCC_OscConfig(&OscInit); + if (HAL_RCC_OscConfig(&OscInit) != HAL_OK) + { + RT_ASSERT(RT_NULL); + } /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ @@ -83,7 +86,7 @@ static void RCC_Configuration(void) ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) { - error_handler(); + RT_ASSERT(RT_NULL); } } From 81fce5d00096f89829e27ffa699c3d23774edf0b Mon Sep 17 00:00:00 2001 From: tanek liang Date: Wed, 14 Jun 2017 16:41:23 +0800 Subject: [PATCH 3/5] [bsp] replace error_handler() by RT_ASSERT(RT_NULL) --- bsp/stm32l072/board/board.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 963ea5bbe9..80c7946a04 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -68,7 +68,10 @@ static void RCC_Configuration(void) OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; - HAL_RCC_OscConfig(&OscInit); + if (HAL_RCC_OscConfig(&OscInit) != HAL_OK) + { + RT_ASSERT(RT_NULL); + } /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ @@ -83,7 +86,7 @@ static void RCC_Configuration(void) ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) { - error_handler(); + RT_ASSERT(RT_NULL); } } From 1d6c38f42fb86587888af3cae083d247fa2ff437 Mon Sep 17 00:00:00 2001 From: tanek liang Date: Wed, 14 Jun 2017 17:07:08 +0800 Subject: [PATCH 4/5] [bsp] remove RT_ASSERT() because UART not work now --- bsp/stm32l072/board/board.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 80c7946a04..92411be737 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -68,10 +68,7 @@ static void RCC_Configuration(void) OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; - if (HAL_RCC_OscConfig(&OscInit) != HAL_OK) - { - RT_ASSERT(RT_NULL); - } + HAL_RCC_OscConfig(&OscInit); /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ @@ -84,10 +81,7 @@ static void RCC_Configuration(void) ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1; ClkInit.APB1CLKDivider = RCC_HCLK_DIV1; ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) - { - RT_ASSERT(RT_NULL); - } + HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1); } #ifdef PRINT_RCC_FREQ_INFO From 761a793a4bbe1e02aafc901ff4da73c71173ee2c Mon Sep 17 00:00:00 2001 From: tanek liang Date: Wed, 14 Jun 2017 17:25:42 +0800 Subject: [PATCH 5/5] [bsp] remove error_handler() and resume RT_ASSERT() --- bsp/stm32l072/board/board.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 92411be737..e12b284cb1 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -40,12 +40,6 @@ void NVIC_Configuration(void) // NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); } -void error_handler(void) -{ - rt_kprintf("error_handler\n"); - while(1); -} - /** * This RCC initial for system. * use HSE clock source @@ -68,7 +62,10 @@ static void RCC_Configuration(void) OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; - HAL_RCC_OscConfig(&OscInit); + if (HAL_RCC_OscConfig(&OscInit) != HAL_OK) + { + RT_ASSERT(RT_NULL); + } /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ @@ -81,7 +78,10 @@ static void RCC_Configuration(void) ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1; ClkInit.APB1CLKDivider = RCC_HCLK_DIV1; ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1); + if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) + { + RT_ASSERT(RT_NULL); + } } #ifdef PRINT_RCC_FREQ_INFO