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[bsp/stm32/rmc] revise code format.

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This commit is contained in:
crazt 2021-07-01 14:16:56 +08:00
parent 6175a594e2
commit 976b28660c
5 changed files with 152 additions and 152 deletions
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2
bsp/stm32/stm32f407-robomaster-c/applications/main.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
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@ -145,7 +145,7 @@
/** /**
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ #define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U #define USE_RTOS 0U
#define PREFETCH_ENABLE 1U #define PREFETCH_ENABLE 1U

296
bsp/stm32/stm32f407-robomaster-c/board/CubeMX_Config/Src/system_stm32f4xx.c
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@ -4,16 +4,16 @@
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): This function is called at startup just after reset and * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file. * the "startup_stm32f4xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
@ -39,8 +39,8 @@
/** @addtogroup stm32f4xx_system /** @addtogroup stm32f4xx_system
* @{ * @{
*/ */
/** @addtogroup STM32F4xx_System_Private_Includes /** @addtogroup STM32F4xx_System_Private_Includes
* @{ * @{
*/ */
@ -48,7 +48,7 @@
#include "stm32f4xx.h" #include "stm32f4xx.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
@ -80,7 +80,7 @@
/* #define DATA_IN_ExtSRAM */ /* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */ STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */ /* #define DATA_IN_ExtSDRAM */
@ -90,7 +90,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
/******************************************************************************/ /******************************************************************************/
@ -112,7 +112,7 @@
/* This variable is updated in three ways: /* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
@ -129,7 +129,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
*/ */
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/** /**
@ -142,7 +142,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory * Initialize the FPU setting, vector table location and External memory
* configuration. * configuration.
* @param None * @param None
* @retval None * @retval None
@ -155,7 +155,7 @@ void SystemInit(void)
#endif #endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
@ -171,41 +171,41 @@ void SystemInit(void)
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE * depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function * is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result. * may have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* *
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -221,10 +221,10 @@ void SystemCoreClockUpdate(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P SYSCLK = PLL_VCO / PLL_P
*/ */
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0) if (pllsource != 0)
{ {
/* HSE used as PLL clock source */ /* HSE used as PLL clock source */
@ -273,79 +273,79 @@ void SystemInit_ExtMemCtl(void)
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC; GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A; GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */ /* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF; GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A; GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */ /* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF; GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA; GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */ /* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA; GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA; GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */ /* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA; GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */ /* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC; GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */ /* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0; GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */ /* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0; GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */ /* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000; GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */ /* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000; GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */ /* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0; GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */ /* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA; GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */ /* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA; GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */ /* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000; GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */ /* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000; GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration -------------------------------------------------------*/ /*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */ /* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
@ -353,50 +353,50 @@ void SystemInit_ExtMemCtl(void)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4; FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351; FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */ /* SDRAM initialization sequence */
/* Clock enable command */ /* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011; FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Delay */ /* Delay */
for (index = 0; index<1000; index++); for (index = 0; index<1000; index++);
/* PALL command */ /* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012; FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Auto refresh command */ /* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073; FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* MRD register program */ /* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014; FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Set refresh count */ /* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR; tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */ /* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0]; tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
@ -404,7 +404,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx) #if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */ /* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091; FMC_Bank1->BTCR[2] = 0x00001091;
@ -412,7 +412,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */ #endif /* STM32F469xx || STM32F479xx */
(void)(tmp); (void)(tmp);
} }
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
@ -438,13 +438,13 @@ void SystemInit_ExtMemCtl(void)
clock */ clock */
RCC->AHB1ENR |= 0x0000007D; RCC->AHB1ENR |= 0x0000007D;
#else #else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */ clock */
RCC->AHB1ENR |= 0x000001F8; RCC->AHB1ENR |= 0x000001F8;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx) #if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */ /* Connect PAx pins to FMC Alternate function */
GPIOA->AFR[0] |= 0xC0000000; GPIOA->AFR[0] |= 0xC0000000;
@ -474,78 +474,78 @@ void SystemInit_ExtMemCtl(void)
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC; GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A; GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */ /* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A; GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A; GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */ /* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A; GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA; GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */ /* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA; GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA; GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */ /* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA; GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */ /* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC; GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */ /* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0; GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */ /* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0; GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */ /* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000; GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */ /* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000; GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */ /* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0; GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */ /* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA; GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */ /* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA; GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */ /* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000; GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */ /* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000; GPIOI->PUPDR = 0x00000000;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/ /*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */ /* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
@ -555,65 +555,65 @@ void SystemInit_ExtMemCtl(void)
/* Configure and enable SDRAM bank1 */ /* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954; FMC_Bank5_6->SDCR[0] = 0x00001954;
#else #else
FMC_Bank5_6->SDCR[0] = 0x000019E4; FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351; FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */ /* SDRAM initialization sequence */
/* Clock enable command */ /* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011; FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Delay */ /* Delay */
for (index = 0; index<1000; index++); for (index = 0; index<1000; index++);
/* PALL command */ /* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012; FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Auto refresh command */ /* Auto refresh command */
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3; FMC_Bank5_6->SDCMR = 0x000000F3;
#else #else
FMC_Bank5_6->SDCMR = 0x00000073; FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* MRD register program */ /* MRD register program */
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014; FMC_Bank5_6->SDCMR = 0x00044014;
#else #else
FMC_Bank5_6->SDCMR = 0x00046014; FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */ #endif /* STM32F446xx */
timeout = 0xFFFF; timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0)) while((tmpreg != 0) && (timeout-- > 0))
{ {
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
} }
/* Set refresh count */ /* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR; tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx) #if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else #else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif /* STM32F446xx */ #endif /* STM32F446xx */
/* Disable write protection */ /* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0]; tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
@ -628,55 +628,55 @@ void SystemInit_ExtMemCtl(void)
RCC->AHB1ENR |= 0x00000078; RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC; GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */ /* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A; GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */ /* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF; GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */ /* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000; GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */ /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000; GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC; GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */ /* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A; GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */ /* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF; GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */ /* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000; GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */ /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000; GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000; GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */ /* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA; GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */ /* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF; GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */ /* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000; GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */ /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000; GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0; GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */ /* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA; GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */ /* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF; GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */ /* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000; GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */ /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000; GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/ /*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */ /* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
@ -688,7 +688,7 @@ void SystemInit_ExtMemCtl(void)
FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff; FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx) #if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
@ -709,8 +709,8 @@ void SystemInit_ExtMemCtl(void)
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp); (void)(tmp);
} }
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/** /**

2
bsp/stm32/stm32f407-robomaster-c/board/board.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/stm32/stm32f407-robomaster-c/board/board.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *