FIX: Merged ljt8015's patch, add DM9161 support.
NOTE: The project.uv2 left not modified. git-svn-id: https://rt-thread.googlecode.com/svn/trunk@546 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
mbbill
parent
eb2cc84a6d
commit
9592d89769
@ -10,6 +10,7 @@
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* Change Logs:
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* Date Author Notes
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* 2006-08-23 Bernard first implementation
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* 2010-03-09 ljt8015 Fix a bug in rt_hw_console_init()
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*/
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#include <rtthread.h>
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@ -128,8 +129,9 @@ static void rt_hw_console_init()
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{
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/* Enable Clock for USART0 */
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
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/* Enable RxD0 and TxDO Pin */
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AT91C_BASE_PIOA->PIO_PDR = (1 << 5) | (1 << 6);
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/* Enable RxD0 and TxD0 Pin */
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//AT91C_BASE_PIOA->PIO_PDR = (1 << 5) | (1 << 6);
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AT91C_BASE_PIOA->PIO_PDR = 1 | (1 << 1);//fix bug 2010-3-9
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AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */
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AT91C_US_RSTTX | /* Reset Transmitter */
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@ -116,7 +116,7 @@
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<Simulator>
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<UseSimulator>1</UseSimulator>
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<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
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<RunToMain>1</RunToMain>
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<RunToMain>0</RunToMain>
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<RestoreBreakpoints>1</RestoreBreakpoints>
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<RestoreWatchpoints>1</RestoreWatchpoints>
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<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
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@ -343,7 +343,7 @@
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<uThumb>0</uThumb>
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<VariousControls>
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<MiscControls></MiscControls>
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<Define></Define>
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<Define>RT_DEBUG</Define>
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<Undefine></Undefine>
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<IncludePath>.;..\..\include;..\sam7x;..\..\finsh;..\..\net\lwip\src\include;..\..\net\lwip\src;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include</IncludePath>
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</VariousControls>
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@ -7,6 +7,27 @@
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#include "lwipopts.h"
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#define MAX_ADDR_LEN 6
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#ifdef DM9161
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#define EMAC_PIO_CFG (AT91C_PB8_EMDC | \
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AT91C_PB9_EMDIO | \
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AT91C_PB2_ETX0 | \
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AT91C_PB3_ETX1 | \
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AT91C_PB10_ETX2 | \
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AT91C_PB11_ETX3 | \
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AT91C_PB1_ETXEN | \
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AT91C_PB0_ETXCK_EREFCK | \
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AT91C_PB15_ERXDV_ECRSDV | \
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AT91C_PB5_ERX0 | \
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AT91C_PB6_ERX1 | \
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AT91C_PB12_ETXER | \
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AT91C_PB13_ERX2 | \
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AT91C_PB14_ERX3 | \
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AT91C_PB17_ERXCK | \
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AT91C_PB16_ECOL | \
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AT91C_PB4_ECRS | \
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AT91C_PB7_ERXER)
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#else
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#define EMAC_PIO_CFG (AT91C_PB0_ETXCK_EREFCK | \
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AT91C_PB1_ETXEN | \
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AT91C_PB2_ETX0 | \
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@ -25,6 +46,7 @@
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AT91C_PB15_ERXDV_ECRSDV| \
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AT91C_PB16_ECOL | \
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AT91C_PB17_ERXCK)
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#endif
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#define RB_BUFFER_SIZE 8 /* max number of receive buffers */
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#define ETH_RX_BUF_SIZE 128
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@ -61,7 +83,6 @@ rt_inline void write_phy(rt_uint8_t addr, rt_uint32_t value)
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{
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AT91C_BASE_EMAC->EMAC_MAN = ((0x01<<30) | (2 << 16) | (1 << 28) |
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(AT91C_PHY_ADDR << 23) | (addr << 18)) | value;
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/* Wait until IDLE bit in Network Status register is cleared */
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while (!(AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE));
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}
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@ -83,7 +104,7 @@ rt_inline void sam7xether_reset_tx_desc(void)
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if(tb_descriptors[index].status & TxDESC_STATUS_USED)
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{
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while(!tb_descriptors[index].status & TxDESC_STATUS_LAST_BUF)
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while(!(tb_descriptors[index].status & TxDESC_STATUS_LAST_BUF))
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{
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index ++;
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if(index >= TB_BUFFER_SIZE)index = 0;
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@ -96,6 +117,7 @@ rt_inline void sam7xether_reset_tx_desc(void)
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}
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}
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/* interrupt service routing */
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static void sam7xether_isr(int irq)
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{
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@ -128,15 +150,81 @@ static void sam7xether_isr(int irq)
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rt_inline void linksetup(void)
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{
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rt_uint32_t value;
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rt_uint32_t value, tout, id1, id2;
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#ifdef DM9161
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rt_uint32_t ulBMSR,ulBMCR,i;
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#endif
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/* Check if this is a RTL8201 PHY. */
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rt_uint16_t id1 = read_phy(PHY_REG_PHYID1);
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rt_uint16_t id2 = read_phy(PHY_REG_PHYID2);
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#ifdef DM9161
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//PHY has internal pull down : disable MII isolate
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tout = read_phy(PHY_REG_BMCR);
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tout = read_phy(PHY_REG_BMCR);
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tout &= ~BMCR_ISOLATE;
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write_phy(PHY_REG_BMCR, tout);
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/* Check if this is a RTL8201 or DM9161 PHY. */
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id1 = read_phy(PHY_REG_PHYID1);
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id2 = read_phy(PHY_REG_PHYID2);
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if (((id1 << 16) | (id2 & 0xfff0)) == MII_DM9161_ID)
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{
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rt_kprintf("read MII_DM9161_ID ok!\n");
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tout = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
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DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
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write_phy(PHY_REG_ANAR, tout);
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// Wait for PHY auto negotiation completed
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i = 0;
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do {
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ulBMSR = read_phy(PHY_REG_BMSR);
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ulBMSR = read_phy(PHY_REG_BMSR);
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i++;
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if(i >= 0xffff)
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break;
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}while (!(ulBMSR & BMSR_ANEGCOMPLETE));
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if(i >= 0xffff)
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rt_kprintf("PHY No Link!\n");
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else
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rt_kprintf("PHY auto negotiation completed!\n");
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/* Update the MAC register NCFGR. */
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AT91C_BASE_EMAC->EMAC_NCFGR = 0;
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ulBMCR = read_phy(PHY_REG_BMCR);
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if (ulBMCR & BMCR_ANENABLE)
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{
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/* AutoNegotiation is enabled. */
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if(!(ulBMSR & BMSR_ANEGCOMPLETE))
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{
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/* Auto-negotitation in progress. */
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rt_kprintf("Auto-negotitation in progress!\n");
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return;
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}
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if (ulBMCR & BMCR_SPEED100)
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{
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/* Speed 100Mbit is enabled. */
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD;
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}
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if (ulBMCR & BMCR_FULLDPLX)
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{
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/* Full duplex is enabled. */
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD;
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}
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}
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}
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#else
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/* Check if this is a RTL8201 or DM9161 PHY. */
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id1 = read_phy(PHY_REG_PHYID1);
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id2 = read_phy(PHY_REG_PHYID2);
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if (((id2 << 16) | (id1 & 0xfff0)) == MII_RTL8201_ID)
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{
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rt_uint32_t tout;
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rt_kprintf("read MII_RTL8201_ID ok!\n");
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/* Configure the PHY device */
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/* Use autonegotiation about the link speed. */
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@ -156,7 +244,6 @@ rt_inline void linksetup(void)
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if (value & BMSR_LINKST) break; /* Link is on. */
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}
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}
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value = read_phy (PHY_REG_ANLPAR);
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/* Update the MAC register NCFGR. */
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@ -166,6 +253,7 @@ rt_inline void linksetup(void)
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if (value & 0xA000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_FD;
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/* set speed */
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if (value & 0xC000) AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_SPD;
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#endif
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}
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/*
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@ -214,6 +302,8 @@ rt_inline void sam7xether_desc_init()
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/* initialize the interface */
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rt_err_t sam7xether_init(rt_device_t dev)
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{
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rt_uint32_t i;
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/* enable peripheral clock for EMAC and PIO B */
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB | 1 << AT91C_ID_EMAC;
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@ -240,10 +330,21 @@ rt_err_t sam7xether_init(rt_device_t dev)
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AT91C_BASE_RSTC->RSTC_RMR = 0xA5000000 | (0x08 << 8) ;
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AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;
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while(!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
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i = 0;
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while(!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))
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{
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i++;
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if(i >= 0xfffff)
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break;
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}
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for(i=0; i<0xfffff; i++);//* 等待一段指定的时间，使PHY就绪
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linksetup();
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rt_kprintf("linksetup ok!\n");
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/* Disable management port in MAC control register. */
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AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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@ -262,13 +363,16 @@ rt_err_t sam7xether_init(rt_device_t dev)
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AT91C_EMAC_RLES| AT91C_EMAC_COL | AT91C_EMAC_UBR);
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/* Configure EMAC operation mode. */
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AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_BIG | AT91C_EMAC_DRFCS);
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//AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_BIG | AT91C_EMAC_DRFCS);
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// 复制所有有效帧到接收缓冲区 *不复制FCS字段 不接收广播帧 不接收1526字节长帧
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF |AT91C_EMAC_DRFCS | AT91C_EMAC_NBC | AT91C_EMAC_BIG;
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AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
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/* update MAC address */
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update_mac_address(sam7x_dev);
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/* enable interrupt */
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AT91C_BASE_EMAC->EMAC_IDR = 0x3fff;
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AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
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/* setup interrupt */
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@ -496,12 +600,13 @@ struct pbuf *sam7xether_rx(rt_device_t dev)
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if (pkt_len > 0) break;
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index ++;
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if (index > RB_BUFFER_SIZE) index = 0;
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if (index >= RB_BUFFER_SIZE) index = 0;
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}
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if (pkt_len)
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{
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p = pbuf_alloc(PBUF_LINK, pkt_len, PBUF_RAM);
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//p = pbuf_alloc(PBUF_LINK, pkt_len, PBUF_RAM);
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p = pbuf_alloc(PBUF_RAW, pkt_len, PBUF_POOL);
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if(p != RT_NULL)
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{
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sam7xether_read_frame(RT_NULL, 0, pkt_len);
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@ -1,7 +1,19 @@
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#ifndef __SAM7X_EMAC_H__
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#define __SAM7X_EMAC_H__
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//#define DM9161
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#define RTL8201
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#ifdef DM9161
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#define AT91C_PHY_ADDR 31
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#else
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#define AT91C_PHY_ADDR 0x01
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#endif
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#define MII_DM9161_ID 0x0181b8a0
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#define MII_RTL8201_ID 0x82010000
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/* RTL8201 PHY registers. */
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@ -22,6 +34,18 @@
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#define PHY_REG_DISCR 0x17 /* Disconnect Counter register */
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#define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State reg. */
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/* Basic mode control register. */
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#define BMCR_RESV 0x007f /* Unused... */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
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#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
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#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
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@ -59,6 +83,31 @@
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#define TxDESC_STATUS_WRAP (1U << 30)
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#define TxDESC_STATUS_USED (1U << 31)
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//----dm9161 define----
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#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
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#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
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#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
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#define DM9161_AUTONEG (1 << 12) // Auto-negotiation Enable
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#define DM9161_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
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#define DM9161_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
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#define DM9161_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
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#define DM9161_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
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#define DM9161_COLLISION_TEST (1 << 7) // 1 = Collision test enabled 0 = Normal operation
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#define DM9161_NP (1 << 15) // Next page Indication
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#define DM9161_ACK (1 << 14) // Acknowledge
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#define DM9161_RF (1 << 13) // Remote Fault
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// Reserved 12 to 11 // Write as 0, ignore on read
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#define DM9161_FCS (1 << 10) // Flow Control Support
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#define DM9161_T4 (1 << 9) // 100BASE-T4 Support
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#define DM9161_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
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#define DM9161_TX_HDX (1 << 7) // 100BASE-TX Support
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#define DM9161_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
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#define DM9161_10_HDX (1 << 5) // 10BASE-T Support
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// Selector 4 to 0 // Protocol Selection Bits
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#define DM9161_AN_IEEE_802_3 0x0001
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int sam7xether_register(char *name);
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#endif
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@ -12,6 +12,7 @@
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* 2006-08-23 Bernard first version
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* 2009-05-14 Bernard add RT-THread device interface
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* 2010-03-14 MingBai US_IMR is read-only.
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* 2010-03-16 MingBai Changed interrupt source mode to level sensitive.
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*/
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#include <rthw.h>
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@ -148,12 +149,14 @@ static rt_err_t rt_serial_init (rt_device_t dev)
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if (serial->peripheral_id == AT91C_ID_US0)
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{
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/* set pinmux */
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AT91C_PIO_PDR = (1 << 5) | (1 << 6);
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//AT91C_PIO_PDR = (1 << 5) | (1 << 6);
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AT91C_PIO_PDR = 1 | (1 << 1); //fix bug 2010-3-9
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}
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else if (serial->peripheral_id == AT91C_ID_US1)
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{
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/* set pinmux */
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AT91C_PIO_PDR = (1 << 21) | (1 << 22);
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//AT91C_PIO_PDR = (1 << 21) | (1 << 22);
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AT91C_PIO_PDR = (1 << 5) | (1 << 6); //fix bug 2010-3-9
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}
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serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */
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@ -200,7 +203,10 @@ static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
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/* install UART handler */
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rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL);
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AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
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// SAM7X Datasheet 30.5.3:
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// It is notrecommended to use the USART interrupt line in edge sensitive mode
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//AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
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AT91C_AIC_SMR(serial->peripheral_id) = 5;
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rt_hw_interrupt_umask(serial->peripheral_id);
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}
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@ -23,6 +23,7 @@
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#ifdef RT_USING_LWIP
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#include "sam7x_emac.h"
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extern rt_err_t eth_system_device_init(void);
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#endif
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#ifdef RT_USING_FINSH
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