update dm9000 driver
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@67 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
parent
1d08491cbf
commit
942ca4da63
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@ -8,6 +8,9 @@
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* DM9000 interrupt line is connected to PF7
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*/
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//--------------------------------------------------------
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#define DM9000_PHY 0x40 /* PHY address 0x01 */
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#define MAX_ADDR_LEN 6
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enum DM9000_PHY_mode
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{
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@ -23,13 +26,6 @@ enum DM9000_TYPE
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TYPE_DM9000B
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};
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struct dm9000_rxhdr
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{
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rt_uint8_t RxPktReady;
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rt_uint8_t RxStatus;
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rt_uint16_t RxLen;
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} __attribute__((__packed__));
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struct rt_dm9000_eth
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{
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/* inherit from ethernet device */
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@ -43,22 +39,25 @@ struct rt_dm9000_eth
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};
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static struct rt_dm9000_eth dm9000_device;
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void delay_ms(rt_uint32_t dt)
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static void delay_ms(rt_uint32_t ms)
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{
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rt_uint32_t len;
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for (;ms > 0; ms --)
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for (len = 0; len < 100; len++ );
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}
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/* Read a byte from I/O port */
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rt_inline rt_uint8_t dm9000_io_read(rt_uint16_t reg)
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{
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ETH_ADDR = reg;
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return (rt_uint8_t) ETH_DATA;
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DM9000_IO = reg;
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return (rt_uint8_t) DM9000_DATA;
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}
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/* Write a byte to I/O port */
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rt_inline void dm9000_io_write(rt_uint16_t reg, rt_uint16_t value)
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{
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ETH_ADDR = reg;
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ETH_DATA = data;
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DM9000_IO = reg;
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DM9000_DATA = value;
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}
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/* Read a word from phyxcer */
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@ -69,7 +68,9 @@ rt_inline rt_uint16_t phy_read(rt_uint16_t reg)
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/* Fill the phyxcer register into REG_0C */
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dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
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dm9000_io_write(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
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delay_ms(100); /* Wait read complete */
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dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
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@ -86,7 +87,9 @@ rt_inline void phy_write(rt_uint16_t reg, rt_uint16_t value)
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dm9000_io_write(DM9000_EPDRL, (value & 0xff));
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dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
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dm9000_io_write(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
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delay_ms(500); /* Wait write complete */
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dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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}
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@ -132,7 +135,7 @@ void rt_dm9000_isr(int irqno)
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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/* Got DM9000 interrupt status */
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int_status = ior(DM9000_ISR); /* Got ISR */
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int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
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dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
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/* Received the coming packet */
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@ -158,7 +161,7 @@ void rt_dm9000_isr(int irqno)
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}
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/* Re-enable interrupt mask */
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dm9000_io_write(DM9000_IMR, db->imr_all);
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dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
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}
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/* RT-Thread Device Interface */
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@ -203,10 +206,11 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
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dm9000_io_write(DM9000_SMCR, 0); /* Special Mode */
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dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
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dm9000_io_write(DM9000_ISR, 0x0f); /* Clear interrupt status */
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dm9000_io_write(0x2D, 0x80); /* Switch LED to mode 1 */
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/* set mac address */
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for (i = 0, oft = 0x10; i < 6; i++, oft++)
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dm9000_io_write(oft, dm9000_device->dev_addr[i]);
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dm9000_io_write(oft, dm9000_device.dev_addr[i]);
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for (i = 0, oft = 0x16; i < 8; i++, oft++)
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dm9000_io_write(oft, 0xff);
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@ -307,7 +311,7 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
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rt_uint16_t* ptr;
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/* Move data to DM9000 TX RAM */
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dm9000_io_write(DM9000_MWCMD, DM9000_IO);
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DM9000_IO = DM9000_MWCMD;
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for (q = p; q != NULL; q = q->next)
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{
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@ -317,7 +321,7 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
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/* use 16bit mode to write data to DM9000 RAM */
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while (len)
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{
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dm9000_io_write(*ptr, DM9000_DATA);
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DM9000_DATA = *ptr;
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ptr ++; len -= 2;
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}
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}
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@ -344,7 +348,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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/* Check packet ready or not */
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dm9000_io_read(DM9000_MRCMDX); /* Dummy read */
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len = dm9000_io_read(DM9000_DATA); /* Got most updated data */
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len = DM9000_DATA; /* Got most updated data */
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if (len)
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{
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rt_uint16_t rx_status, rx_len;
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@ -354,10 +358,10 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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dm9000_io_write(DM9000_ISR, 0x80); /* Stop INT request */
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/* A packet ready now & Get status/length */
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DM9000_outb(DM9000_MRCMD, DM9000_IO);
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DM9000_IO = DM9000_MRCMD;
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rx_status = dm9000_io_write(DM9000_DATA);
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rx_len = dm9000_io_write(DM9000_DATA);
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rx_status = DM9000_DATA;
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rx_len = DM9000_DATA;
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/* allocate buffer */
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p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
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@ -372,7 +376,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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while (len)
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{
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*data = dm9000_io_write(DM9000_DATA);
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*data = DM9000_DATA;
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data ++; len -= 2;
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}
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}
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@ -385,7 +389,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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data = &dummy;
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while (rx_len)
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{
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*data = dm9000_io_write(DM9000_DATA);
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*data = DM9000_DATA;
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rx_len -= 2;
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}
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}
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@ -395,19 +399,22 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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{
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if (rx_status & 0x100)
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{
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rt_printf("rx fifo error\n");
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rt_kprintf("rx fifo error\n");
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}
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if (rx_status & 0x200) {
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rt_printf("rx crc error\n");
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rt_kprintf("rx crc error\n");
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}
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if (rx_status & 0x8000)
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{
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rt_printf("rx length error\n");
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rt_kprintf("rx length error\n");
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}
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if (rx_len > DM9000_PKT_MAX)
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{
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rt_printf("rx length too big\n");
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dm9000_reset();
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rt_kprintf("rx length too big\n");
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/* RESET device */
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dm9000_io_write(DM9000_NCR, NCR_RST);
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delay_ms(1000); /* delay 1ms */
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}
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/* it issues an error, release pbuf */
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@ -423,65 +430,19 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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return p;
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}
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{
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u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
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u16 RxStatus, RxLen = 0;
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u32 tmplen, i;
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/* Status check: this byte must be 0 or 1 */
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if (rxbyte > 1) {
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DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
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DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
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DM9000_DBG("rx status check: %d\n", rxbyte);
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}
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/* A packet ready now & Get status/length */
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DM9000_outb(DM9000_MRCMD, DM9000_IO);
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RxStatus = DM9000_inw(DM9000_DATA);
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RxLen = DM9000_inw(DM9000_DATA);
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/* Read received packet from RX SRAM */
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tmplen = (RxLen + 1) / 2;
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for (i = 0; i < tmplen; i++)
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((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
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if ((RxStatus & 0xbf00) || (RxLen < 0x40)
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|| (RxLen > DM9000_PKT_MAX))
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{
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if (RxStatus & 0x100)
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{
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rt_printf("rx fifo error\n");
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}
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if (RxStatus & 0x200) {
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rt_printf("rx crc error\n");
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}
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if (RxStatus & 0x8000)
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{
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rt_printf("rx length error\n");
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}
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if (RxLen > DM9000_PKT_MAX)
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{
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rt_printf("rx length too big\n");
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dm9000_reset();
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}
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}
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else
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{
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/* Pass to upper layer */
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DM9000_DBG("passing packet to upper layer\n");
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NetReceive(NetRxPackets[0], RxLen);
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return RxLen;
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}
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}
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void rt_hw_dm9000_init()
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{
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dm9000_device.type = TYPE_DM9000A;
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dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
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dm9000_device.dev_addr[0] = 0x01;
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dm9000_device.dev_addr[1] = 0x60;
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dm9000_device.dev_addr[2] = 0x6E;
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dm9000_device.dev_addr[3] = 0x11;
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dm9000_device.dev_addr[4] = 0x02;
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dm9000_device.dev_addr[5] = 0x0F;
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dm9000_device.parent.parent.init = rt_dm9000_init;
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dm9000_device.parent.parent.open = rt_dm9000_open;
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dm9000_device.parent.parent.close = rt_dm9000_close;
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@ -502,15 +463,14 @@ void rt_hw_dm9000_init()
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void dm9000(void)
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{
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rt_kprintf("\n");
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rt_kprintf("NCR (0x00): %02x\n", dm9000_io_read(0));
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rt_kprintf("NSR (0x01): %02x\n", dm9000_io_read(1));
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rt_kprintf("TCR (0x02): %02x\n", dm9000_io_read(2));
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rt_kprintf("TSRI (0x03): %02x\n", dm9000_io_read(3));
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rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(4));
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rt_kprintf("RCR (0x05): %02x\n", dm9000_io_read(5));
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rt_kprintf("RSR (0x06): %02x\n", dm9000_io_read(6));
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rt_kprintf("ISR (0xFE): %02x\n", dm9000_io_read(ISR));
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rt_kprintf("NCR (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
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rt_kprintf("NSR (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
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rt_kprintf("TCR (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
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rt_kprintf("TSRI (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
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rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
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rt_kprintf("RCR (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
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rt_kprintf("RSR (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
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rt_kprintf("ISR (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
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rt_kprintf("\n");
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}
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#endif
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@ -1,8 +1,9 @@
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#ifndef __DM9000_H__
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#define __DM9000_H__
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#define ETH_ADDR (*((volatile unsigned short *) 0x6C000000)) // CMD = 0
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#define ETH_DATA (*((volatile unsigned short *) 0x6C000008)) // CMD = 1
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#define DM9000_IO (*((volatile rt_uint16_t *) 0x6C000000)) // CMD = 0
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#define DM9000_DATA (*((volatile rt_uint16_t *) 0x6C000008)) // CMD = 1
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#define RST_1() GPIO_SetBits(GPIOF,GPIO_Pin_6)
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#define RST_0() GPIO_ResetBits(GPIOF,GPIO_Pin_6)
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