libs/rt-thread
libs
/
rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge pull request #1 from mysterywolf/littlefs-check 

解决没有选定FAL和littlefs软件包的问题，解决挂载顺序不合理的问题，重命名spiflash设备为spiflash0
This commit is contained in:
YJ98 2021-08-06 09:09:51 +08:00 committed by GitHub
parent addfbefeeb 963cce1e1b
commit 9422f720f2
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
25 changed files with 411 additions and 350 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.github/workflows/action.yml vendored
View File

@ -131,6 +131,7 @@ jobs:
- {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "raspberry-pi/raspi4-32", RTT_TOOL_CHAIN: "sourcery-arm"}
steps:
- uses: actions/checkout@v2
- name: Set up Python

151
bsp/raspberry-pi/raspi4-32/.config
View File

@ -23,6 +23,12 @@ CONFIG_IDLE_THREAD_STACK_SIZE=2048
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@ -67,8 +73,10 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_RT_USING_GIC_V2=y
CONFIG_ARCH_ARMV8=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -125,6 +133,11 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
@ -133,8 +146,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
@ -146,6 +157,8 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=512
# CONFIG_RT_USING_CAN is not set
@ -181,6 +194,7 @@ CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
CONFIG_RT_USING_TOUCH=y
# CONFIG_RT_TOUCH_PIN_IRQ is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
@ -203,6 +217,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
@ -212,6 +227,7 @@ CONFIG_RT_USING_POSIX=y
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# protocol stack implement
@ -238,6 +254,7 @@ CONFIG_NETDEV_IPV6=0
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP203 is not set
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@ -252,8 +269,8 @@ CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_IPADDR="192.168.111.172"
CONFIG_RT_LWIP_GWADDR="192.168.111.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
@ -307,6 +324,12 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
@ -375,8 +398,6 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
@ -390,6 +411,13 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
@ -415,6 +443,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
@ -429,6 +458,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
@ -441,6 +472,20 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
#
# system packages
@ -448,7 +493,6 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
@ -458,6 +502,9 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
@ -478,6 +525,15 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
#
# peripheral libraries and drivers
@ -486,6 +542,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
@ -534,6 +591,29 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
@ -543,6 +623,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
@ -564,64 +645,24 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_MDNS is not set
# CONFIG_PKG_USING_UPNP is not set
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_ALI_LINKKIT is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
# CONFIG_PKG_USING_ZBAR is not set
# CONFIG_PKG_USING_MCF is not set
# CONFIG_PKG_USING_URPC is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_DCM is not set
# CONFIG_PKG_USING_EMQ is not set
# CONFIG_PKG_USING_CFGM is not set
# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set
# CONFIG_PKG_USING_SMODULE is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
CONFIG_BCM2711_SOC=y
# CONFIG_BSP_SUPPORT_FPU is not set

1
bsp/raspberry-pi/raspi4-32/Kconfig
View File

@ -23,6 +23,7 @@ config BCM2711_SOC
select ARCH_ARMV8
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select RT_USING_GIC_V2
default y
source "driver/Kconfig"

283
bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
View File

@ -19,6 +19,7 @@
#include "raspi4.h"
#include "drv_eth.h"
#define DBG_LEVEL DBG_LOG
#include <rtdbg.h>
#define LOG_TAG "drv.eth"
@ -26,12 +27,14 @@
static int link_speed = 0;
static int link_flag = 0;
#define RECV_CACHE_BUF (2048)
#define SEND_CACHE_BUF (2048)
#define DMA_DISC_ADDR_SIZE (2 * 1024 *1024)
#define RECV_CACHE_BUF (1024)
#define SEND_CACHE_BUF (1024)
#define SEND_DATA_NO_CACHE (0x08200000)
#define RECV_DATA_NO_CACHE (0x08400000)
#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024)
#define RX_DESC_BASE (mac_reg_base_addr + GENET_RX_OFF)
#define TX_DESC_BASE (mac_reg_base_addr + GENET_TX_OFF)
#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF)
#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF)
#define MAX_ADDR_LEN (6)
@ -45,11 +48,11 @@ static rt_thread_t link_thread_tid = RT_NULL;
#define LINK_THREAD_PRIORITY (20)
#define LINK_THREAD_TIMESLICE (10)
static rt_uint32_t tx_index = 0;
static rt_uint32_t rx_index = 0;
static rt_uint32_t index_flag = 0;
static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF];
struct rt_eth_dev
{
@ -60,12 +63,11 @@ struct rt_eth_dev
int state;
int index;
struct rt_timer link_timer;
struct rt_timer rx_poll_timer;
void *priv;
};
static struct rt_eth_dev eth_dev;
static struct rt_semaphore send_finsh_sem_lock;
static struct rt_semaphore sem_lock;
static struct rt_semaphore link_ack;
static inline rt_uint32_t read32(void *addr)
@ -78,18 +80,12 @@ static inline void write32(void *addr, rt_uint32_t value)
(*((volatile unsigned int*)(addr))) = value;
}
static void eth_rx_irq(int irq, void *param)
{
rt_uint32_t val = 0;
val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT);
val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK);
write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val);
val = read32(MAC_REG + GENET_INTRL2_CPU_STAT);
val &= ~read32(MAC_REG + GENET_INTRL2_CPU_STAT_MASK);
write32(MAC_REG + GENET_INTRL2_CPU_CLEAR, val);
if (val & GENET_IRQ_RXDMA_DONE)
{
eth_device_ready(&eth_dev.parent);
@ -97,7 +93,7 @@ static void eth_rx_irq(int irq, void *param)
if (val & GENET_IRQ_TXDMA_DONE)
{
rt_sem_release(&send_finsh_sem_lock);
rt_sem_release(&sem_lock);
}
}
@ -109,11 +105,10 @@ static int bcmgenet_interface_set(void)
{
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_RXID:
write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
write32(MAC_REG + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
break;
default:
rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr);
rt_kprintf("unknown phy mode: %d\n", MAC_REG);
return -1;
}
return 0;
@ -122,48 +117,44 @@ static int bcmgenet_interface_set(void)
static void bcmgenet_umac_reset(void)
{
rt_uint32_t reg;
reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL);
reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL);
reg |= BIT(1);
write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
reg &= ~BIT(1);
write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
DELAY_MICROS(10);
write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), 0);
DELAY_MICROS(10);
write32(mac_reg_base_addr + UMAC_CMD, 0);
write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
write32(MAC_REG + UMAC_CMD, 0);
write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
DELAY_MICROS(2);
write32(mac_reg_base_addr + UMAC_CMD, 0);
write32(MAC_REG + UMAC_CMD, 0);
/* clear tx/rx counter */
write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0);
write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
write32(MAC_REG + UMAC_MIB_CTRL, 0);
write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
/* init rx registers, enable ip header optimization */
reg = read32(mac_reg_base_addr + RBUF_CTRL);
reg = read32(MAC_REG + RBUF_CTRL);
reg |= RBUF_ALIGN_2B;
write32(mac_reg_base_addr + RBUF_CTRL, reg);
write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1);
write32(MAC_REG + RBUF_CTRL, reg);
write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1);
}
static void bcmgenet_disable_dma(void)
{
rt_uint32_t tdma_reg = 0, rdma_reg = 0;
tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL);
tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL);
tdma_reg &= ~(1UL << DMA_EN);
write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL);
write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
rdma_reg &= ~(1UL << DMA_EN);
write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1);
write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
write32(MAC_REG + UMAC_TX_FLUSH, 1);
DELAY_MICROS(100);
write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0);
write32(MAC_REG + UMAC_TX_FLUSH, 0);
}
static void bcmgenet_enable_dma(void)
@ -172,10 +163,10 @@ static void bcmgenet_enable_dma(void)
rt_uint32_t dma_ctrl = 0;
dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL);
write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
}
static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value)
@ -183,16 +174,16 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va
int count = 10000;
rt_uint32_t val;
val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value);
write32(mac_reg_base_addr + MDIO_CMD, val);
write32(MAC_REG + MDIO_CMD, val);
rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD);
rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD);
reg_val = reg_val | MDIO_START_BUSY;
write32(mac_reg_base_addr + MDIO_CMD, reg_val);
write32(MAC_REG + MDIO_CMD, reg_val);
while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count))
while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
DELAY_MICROS(1);
reg_val = read32(mac_reg_base_addr + MDIO_CMD);
reg_val = read32(MAC_REG + MDIO_CMD);
return reg_val & 0xffff;
}
@ -204,31 +195,32 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
rt_uint32_t reg_val = 0;
val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
write32(mac_reg_base_addr + MDIO_CMD, val);
write32(MAC_REG + MDIO_CMD, val);
reg_val = read32(mac_reg_base_addr + MDIO_CMD);
reg_val = read32(MAC_REG + MDIO_CMD);
reg_val = reg_val | MDIO_START_BUSY;
write32(mac_reg_base_addr + MDIO_CMD, reg_val);
write32(MAC_REG + MDIO_CMD, reg_val);
while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count))
while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
DELAY_MICROS(1);
reg_val = read32(mac_reg_base_addr + MDIO_CMD);
reg_val = read32(MAC_REG + MDIO_CMD);
return reg_val & 0xffff;
}
static int bcmgenet_gmac_write_hwaddr(void)
{
//{0xdc,0xa6,0x32,0x28,0x22,0x50};
rt_uint8_t addr[6];
rt_uint32_t reg;
bcm271x_mbox_hardware_get_mac_address(&addr[0]);
reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
write32(mac_reg_base_addr + UMAC_MAC0, reg);
write32(MAC_REG + UMAC_MAC0, reg);
reg = addr[4] << 8 | addr[5];
write32(mac_reg_base_addr + UMAC_MAC1, reg);
write32(MAC_REG + UMAC_MAC1, reg);
return 0;
}
@ -254,8 +246,10 @@ static void bcmgenet_mdio_init(void)
rt_uint32_t ret = 0;
/*get ethernet uid*/
ret = get_ethernet_uid();
if (ret == 0) return;
if (ret == 0)
{
return;
}
/* reset phy */
bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET);
/* read control reg */
@ -282,34 +276,34 @@ static void bcmgenet_mdio_init(void)
static void rx_ring_init(void)
{
write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0);
write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0);
write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
write32(MAC_REG + RDMA_READ_PTR, 0x0);
write32(MAC_REG + RDMA_WRITE_PTR, 0x0);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0);
write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0);
write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
write32(MAC_REG + RDMA_PROD_INDEX, 0x0);
write32(MAC_REG + RDMA_CONS_INDEX, 0x0);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
}
static void tx_ring_init(void)
{
write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0);
write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0);
write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0);
write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1);
write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0);
write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_WRITE_PTR, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(MAC_REG + TDMA_PROD_INDEX, 0x0);
write32(MAC_REG + TDMA_CONS_INDEX, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1);
write32(MAC_REG + TDMA_FLOW_PERIOD, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
}
static void rx_descs_init(void)
@ -348,14 +342,14 @@ static int bcmgenet_adjust_link(void)
return -1;
}
rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL);
rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL);
//reg1 &= ~(1UL << OOB_DISABLE);
//rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE);
reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1);
write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1);
DELAY_MICROS(1000);
write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT);
write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT);
return 0;
}
@ -393,28 +387,28 @@ static int bcmgenet_gmac_eth_start(void)
}
/* wait tx index clear */
while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count))
while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count))
DELAY_MICROS(1);
tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX);
write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index);
tx_index = read32(MAC_REG + TDMA_CONS_INDEX);
write32(MAC_REG + TDMA_PROD_INDEX, tx_index);
index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX);
index_flag = read32(MAC_REG + RDMA_PROD_INDEX);
rx_index = index_flag % RX_DESCS;
write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag);
write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag);
write32(MAC_REG + RDMA_CONS_INDEX, index_flag);
write32(MAC_REG + RDMA_PROD_INDEX, index_flag);
/* Enable Rx/Tx */
rt_uint32_t rx_tx_en;
rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD);
rx_tx_en = read32(MAC_REG + UMAC_CMD);
rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en);
// eanble IRQ for TxDMA done and RxDMA done
write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
write32(MAC_REG + UMAC_CMD, rx_tx_en);
//IRQ
write32(MAC_REG + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
return 0;
}
@ -424,16 +418,17 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
{
void* desc_base;
rt_uint32_t length = 0, addr = 0;
rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX);
if(prod_index == index_flag) //no buff
rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX);
if(prod_index == index_flag)
{
cur_recv_cnt = index_flag;
index_flag = 0x7fffffff;
/* no buff */
return 0;
}
else
{
if(prev_recv_cnt == (prod_index & 0xffff)) //no new buff
if(prev_recv_cnt == prod_index & 0xffff)
{
return 0;
}
@ -446,11 +441,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
* This would actually not be needed if we don't program
* RBUF_ALIGN_2B
*/
//Convert to memory address
addr = addr + eth_recv_no_cache - RECV_DATA_NO_CACHE;
rt_hw_cpu_dcache_invalidate(addr,length);
*packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET);
rx_index = rx_index + 1;
@ -458,8 +449,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
{
rx_index = 0;
}
write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt);
write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt);
cur_recv_cnt = cur_recv_cnt + 1;
@ -469,43 +459,45 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
}
prev_recv_cnt = cur_recv_cnt;
return length - RX_BUF_OFFSET;
return length;
}
}
static int bcmgenet_gmac_eth_send(rt_uint32_t packet, int length,struct pbuf *p)
static int bcmgenet_gmac_eth_send(void *packet, int length)
{
rt_ubase_t level;
void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
pbuf_copy_partial(p, (void*)(packet + tx_index * SEND_CACHE_BUF), p->tot_len, 0);
rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
rt_uint32_t prod_index, cons;
rt_uint32_t tries = 100;
prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
rt_hw_cpu_dcache_clean((void*)(packet + tx_index * SEND_CACHE_BUF),length);
rt_uint32_t prod_index;
prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX);
write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE + tx_index * SEND_CACHE_BUF);
rt_hw_cpu_dcache_clean((void*)packet, length);
write32((desc_base + DMA_DESC_ADDRESS_LO), packet);
write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);
tx_index ++;
if(tx_index >= TX_DESCS)
{
tx_index = 0;
}
tx_index = tx_index + 1;
prod_index = prod_index + 1;
if (prod_index > 0xffff)
if (prod_index == 0xe000)
{
write32(MAC_REG + TDMA_PROD_INDEX, 0);
prod_index = 0;
}
if (tx_index >= TX_DESCS)
{
tx_index = 0;
}
/* Start Transmisson */
write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index);
write32(MAC_REG + TDMA_PROD_INDEX, prod_index);
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
return 0;
}
@ -514,10 +506,8 @@ static void link_task_entry(void *param)
struct eth_device *eth_device = (struct eth_device *)param;
RT_ASSERT(eth_device != RT_NULL);
struct rt_eth_dev *dev = &eth_dev;
//start mdio
bcmgenet_mdio_init();
//start timer link
rt_timer_init(&dev->link_timer, "link_timer",
link_irq,
@ -532,7 +522,7 @@ static void link_task_entry(void *param)
rt_timer_stop(&dev->link_timer);
//set mac
// bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_write_hwaddr();
//check link speed
@ -552,13 +542,9 @@ static void link_task_entry(void *param)
rt_kprintf("Support link mode Speed 10M\n");
}
//Convert to memory address
bcmgenet_gmac_eth_start();
rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq");
rt_hw_interrupt_umask(ETH_IRQ);
link_flag = 1;
}
@ -569,7 +555,7 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
/* Read GENET HW version */
rt_uint8_t major = 0;
hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL);
hw_reg = read32(MAC_REG + SYS_REV_CTRL);
major = (hw_reg >> 24) & 0x0f;
if (major != 6)
{
@ -589,12 +575,12 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
}
/* rbuf clear */
write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0);
write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0);
/* disable MAC while updating its registers */
write32(mac_reg_base_addr + UMAC_CMD, 0);
write32(MAC_REG + UMAC_CMD, 0);
/* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device,
LINK_THREAD_STACK_SIZE,
@ -623,44 +609,49 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
{
rt_uint32_t sendbuf = (rt_uint32_t)SEND_DATA_NO_CACHE + (rt_uint32_t)(tx_index * SEND_CACHE_BUF);
/* lock eth device */
if (link_flag == 1)
{
bcmgenet_gmac_eth_send((rt_uint32_t)eth_send_no_cache, p->tot_len,p);
rt_sem_take(&send_finsh_sem_lock,RT_WAITING_FOREVER);
pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
}
return RT_EOK;
}
struct pbuf *rt_eth_rx(rt_device_t device)
{
int recv_len = 0;
rt_uint8_t* addr_point = RT_NULL;
rt_uint8_t *addr_point = RT_NULL;
struct pbuf *pbuf = RT_NULL;
if (link_flag == 1)
{
recv_len = bcmgenet_gmac_eth_recv(&addr_point);
recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point);
if (recv_len > 0)
{
pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
if(pbuf)
{
rt_memcpy(pbuf->payload, addr_point, recv_len);
}
}
}
return pbuf;
}
int rt_hw_eth_init(void)
{
rt_uint8_t mac_addr[6];
rt_sem_init(&send_finsh_sem_lock,"send_finsh_sem_lock",TX_DESCS,RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_send_lock", TX_DESCS, RT_IPC_FLAG_FIFO);
rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
memset(&eth_dev, 0, sizeof(eth_dev));
memset((void *)eth_send_no_cache, 0, DMA_DISC_ADDR_SIZE);
memset((void *)eth_recv_no_cache, 0, DMA_DISC_ADDR_SIZE);
memset((void *)SEND_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE);
memset((void *)RECV_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE);
bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
eth_dev.iobase = mac_reg_base_addr;
eth_dev.iobase = MAC_REG;
eth_dev.name = "e0";
eth_dev.dev_addr[0] = mac_addr[0];
eth_dev.dev_addr[1] = mac_addr[1];

2
bsp/raspberry-pi/raspi4-32/link.lds
View File

@ -11,7 +11,7 @@
SECTIONS
{
. = 0x8000;
. = 0x200000;
. = ALIGN(4096);
.text :
{

29
bsp/raspberry-pi/raspi4-32/rtconfig.h
View File

@ -19,6 +19,9 @@
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 2048
/* kservice optimization */
#define RT_DEBUG
/* Inter-Thread communication */
@ -41,7 +44,8 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40003
#define RT_VER_NUM 0x40004
#define RT_USING_GIC_V2
#define ARCH_ARMV8
/* RT-Thread Components */
@ -84,6 +88,8 @@
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
@ -98,6 +104,7 @@
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 512
#define RT_USING_I2C
@ -120,12 +127,14 @@
#define RT_USING_LIBC
#define RT_USING_POSIX
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* protocol stack implement */
@ -156,8 +165,8 @@
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_IPADDR "192.168.111.172"
#define RT_LWIP_GWADDR "192.168.111.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
@ -195,6 +204,9 @@
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
@ -232,19 +244,16 @@
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* games: games run on RT-Thread console */
/* Privated Packages of RealThread */
/* Network Utilities */
/* entertainment: terminal games and other interesting software packages */
#define BCM2711_SOC

2
bsp/raspberry-pi/raspi4-32/rtconfig.py
View File

@ -37,7 +37,7 @@ if PLATFORM == 'gcc':
DEVICE = ' -march=armv8-a -mtune=cortex-a72'
CFLAGS = DEVICE + ' -Wall'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
LPATH = ''

24
bsp/stm32/libraries/HAL_Drivers/drv_eth.c
View File

@ -41,9 +41,9 @@ struct rt_stm32_eth
/* interface address info, hw address */
rt_uint8_t dev_addr[MAX_ADDR_LEN];
/* ETH_Speed */
uint32_t ETH_Speed;
rt_uint32_t ETH_Speed;
/* ETH_Duplex_Mode */
uint32_t ETH_Mode;
rt_uint32_t ETH_Mode;
};
static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
@ -167,8 +167,14 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
else return -RT_ERROR;
if (args)
{
SMEMCPY(args, stm32_eth_device.dev_addr, 6);
}
else
{
return -RT_ERROR;
}
break;
default :
@ -214,7 +220,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
{
/* Copy data to Tx buffer*/
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
SMEMCPY((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
@ -236,7 +242,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
}
/* Copy the remaining bytes */
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
SMEMCPY((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
framelength = framelength + byteslefttocopy;
}
@ -327,7 +333,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
{
/* Copy data to pbuf */
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
SMEMCPY((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
@ -338,7 +344,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
bufferoffset = 0;
}
/* Copy remaining data in pbuf */
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
SMEMCPY((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
}
}
@ -385,7 +391,9 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
rt_err_t result;
result = eth_device_ready(&(stm32_eth_device.parent));
if (result != RT_EOK)
{
LOG_I("RxCpltCallback err = %d", result);
}
}
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)

12
bsp/stm32/libraries/HAL_Drivers/drv_eth.h
View File

@ -28,13 +28,12 @@
/* The PHY ID one register */
#define PHY_ID1_REG 0x02U
/* The PHY ID two register */
#define PHY_ID2_REG 0x03U
/* The PHY auto-negotiate advertise register */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
#ifdef PHY_USING_LAN8720A
/* The PHY interrupt source flag register. */
#define PHY_INTERRUPT_FLAG_REG 0x1DU
@ -51,9 +50,8 @@
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
#endif /* PHY_USING_LAN8720A */
#ifdef PHY_USING_DM9161CEP
#elif defined(PHY_USING_DM9161CEP)
#define PHY_Status_REG 0x11U
#define PHY_10M_MASK ((1<<12) || (1<<13))
#define PHY_100M_MASK ((1<<14) || (1<<15))
@ -69,9 +67,7 @@
#define PHY_LINK_CHANGE_MASK (1<<9)
#define PHY_INT_MASK 0
#endif /* PHY_USING_DM9161CEP */
#ifdef PHY_USING_DP83848C
#elif defined(PHY_USING_DP83848C)
#define PHY_Status_REG 0x10U
#define PHY_10M_MASK (1<<1)
#define PHY_FULL_DUPLEX_MASK (1<<2)
@ -87,6 +83,6 @@
/* The PHY interrupt mask register. */
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK (1<<5)
#endif /* PHY_USING_DP83848C */
#endif
#endif /* __DRV_ETH_H__ */

3
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
View File

@ -99,6 +99,9 @@ menu "Onboard Peripheral Drivers"
select RT_USING_MTD_NOR
select BSP_USING_SPI_FLASH
select BSP_USING_FS
select PKG_USING_FAL
select FAL_USING_SFUD_PORT
select PKG_USING_LITTLEFS
select RT_USING_SYSTEM_WORKQUEUE
default n

45
bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c
View File

@ -16,7 +16,6 @@
#include <dfs_romfs.h>
#include <dfs_fs.h>
#include <dfs_posix.h>
#include <fal.h>
#if DFS_FILESYSTEMS_MAX < 4
#error "Please define DFS_FILESYSTEMS_MAX more than 4"
@ -77,55 +76,34 @@ static int onboard_sdcard_mount(void)
#endif
#ifdef BSP_USING_SPI_FLASH_LITTLEFS
#include <fal.h>
#define FS_PARTITION_NAME "spiflash0"
#define FS_PARTITION_NAME "filesystem"
static void spiflash_mount(void *parameter)
static int onboard_spiflash_mount(void)
{
struct rt_device *mtd_dev = RT_NULL;
fal_init();
mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
if (!mtd_dev)
{
LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
}
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find(FS_PARTITION_NAME) != RT_NULL)
{
if (dfs_mount(FS_PARTITION_NAME, "/flash", "lfs", 0, 0) == RT_EOK)
{
LOG_I("spi flash mount to '/flash'");
break;
}
else
{
LOG_W("spi flash mount to '/flash' failed!");
}
}
}
}
static int onboard_spiflash_mount(void)
{
rt_thread_t tid;
if (dfs_mount(FS_PARTITION_NAME, "/flash", "lfs", 0, 0) == RT_EOK)
if (dfs_mount(FS_PARTITION_NAME, "/spiflash", "lfs", 0, 0) == RT_EOK)
{
LOG_I("spi flash mount to '/flash'");
LOG_I("spi flash mount to '/spiflash'");
}
else
{
tid = rt_thread_create("spiflash_mount", spiflash_mount, RT_NULL,
1024, RT_THREAD_PRIORITY_MAX - 3, 20);
if (tid != RT_NULL)
dfs_mkfs("lfs", FS_PARTITION_NAME);
if (dfs_mount(FS_PARTITION_NAME, "/spiflash", "lfs", 0, 0) == RT_EOK)
{
rt_thread_startup(tid);
LOG_I("spi flash mount to '/spiflash'");
}
else
{
LOG_E("create spiflash_mount thread err!");
LOG_E("spi flash failed to mount to '/spiflash'");
}
}
@ -133,7 +111,6 @@ static int onboard_spiflash_mount(void)
}
#endif
static const struct romfs_dirent _romfs_root[] =
{
#ifdef BSP_USING_SDCARD
@ -141,7 +118,7 @@ static const struct romfs_dirent _romfs_root[] =
#endif
#ifdef BSP_USING_SPI_FLASH_LITTLEFS
{ROMFS_DIRENT_DIR, "flash", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "spiflash", RT_NULL, 0},
#endif
};

2
bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
View File

@ -52,7 +52,7 @@ extern const struct fal_flash_dev stm32_onchip_flash_128k;
#ifdef BSP_USING_SPI_FLASH_LITTLEFS
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "filesystem",FAL_USING_NOR_FLASH_DEV_NAME, 0 , 16 * 1024 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "spiflash0", FAL_USING_NOR_FLASH_DEV_NAME, 0 , 16 * 1024 * 1024, 0}, \
}
#else
#define FAL_PART_TABLE \

7
components/net/lwip-1.4.1/src/lwipopts.h
View File

@ -222,6 +222,13 @@
#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT)
/* ---------- Memory options ---------- */
#ifdef RT_USING_ASM_MEMCPY
#define MEMCPY(dst,src,len) rt_memcpy(dst,src,len)
#else
#define MEMCPY(dst,src,len) memcpy(dst,src,len)
#endif /* RT_USING_ASM_MEMCPY */
#define SMEMCPY(dst,src,len) MEMCPY(dst,src,len)
#define MEM_ALIGNMENT 4
#define MEM_LIBC_MALLOC 1

8
components/net/lwip-1.4.1/src/netif/ethernetif.c
View File

@ -201,14 +201,14 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len,
{
return -RT_ERROR;
}
rt_memcpy(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
rt_memcpy(&ina, &h->sin_addr, sizeof(ina));
SMEMCPY(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
SMEMCPY(&ina, &h->sin_addr, sizeof(ina));
lwip_freeaddrinfo(res);
if (inet_aton(inet_ntoa(ina), &target_addr) == 0)
{
return -RT_ERROR;
}
rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
SMEMCPY(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
/* new a socket */
if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
@ -331,7 +331,7 @@ static int netdev_add(struct netif *lwip_netif)
netdev->mtu = lwip_netif->mtu;
netdev->ops = &lwip_netdev_ops;
netdev->hwaddr_len = lwip_netif->hwaddr_len;
rt_memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
SMEMCPY(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
netdev->ip_addr = lwip_netif->ip_addr;
netdev->gw = lwip_netif->gw;
netdev->netmask = lwip_netif->netmask;

11
components/net/lwip-2.0.2/src/lwipopts.h
View File

@ -230,14 +230,21 @@
#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT)
/* ---------- Memory options ---------- */
#ifdef RT_USING_ASM_MEMCPY
#define MEMCPY(dst,src,len) rt_memcpy(dst,src,len)
#else
#define MEMCPY(dst,src,len) memcpy(dst,src,len)
#endif /* RT_USING_ASM_MEMCPY */
#define SMEMCPY(dst,src,len) MEMCPY(dst,src,len)
#ifdef RT_LWIP_MEM_ALIGNMENT
#define MEM_ALIGNMENT RT_LWIP_MEM_ALIGNMENT
#else
#define MEM_ALIGNMENT 4
#endif
#define MEMP_OVERFLOW_CHECK 1 ////
#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1 ////
#define MEMP_OVERFLOW_CHECK 1
#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1
//#define MEM_LIBC_MALLOC 1
//#define MEM_USE_POOLS 1
//#define MEMP_USE_CUSTOM_POOLS 1

8
components/net/lwip-2.0.2/src/netif/ethernetif.c
View File

@ -210,14 +210,14 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len,
{
return -RT_ERROR;
}
rt_memcpy(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
rt_memcpy(&ina, &h->sin_addr, sizeof(ina));
SMEMCPY(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
SMEMCPY(&ina, &h->sin_addr, sizeof(ina));
lwip_freeaddrinfo(res);
if (inet_aton(inet_ntoa(ina), &target_addr) == 0)
{
return -RT_ERROR;
}
rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
SMEMCPY(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
/* new a socket */
if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
@ -340,7 +340,7 @@ static int netdev_add(struct netif *lwip_netif)
netdev->mtu = lwip_netif->mtu;
netdev->ops = &lwip_netdev_ops;
netdev->hwaddr_len = lwip_netif->hwaddr_len;
rt_memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
SMEMCPY(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
netdev->ip_addr = lwip_netif->ip_addr;
netdev->gw = lwip_netif->gw;
netdev->netmask = lwip_netif->netmask;

11
components/net/lwip-2.0.3/src/lwipopts.h
View File

@ -230,14 +230,21 @@
#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT)
/* ---------- Memory options ---------- */
#ifdef RT_USING_ASM_MEMCPY
#define MEMCPY(dst,src,len) rt_memcpy(dst,src,len)
#else
#define MEMCPY(dst,src,len) memcpy(dst,src,len)
#endif /* RT_USING_ASM_MEMCPY */
#define SMEMCPY(dst,src,len) MEMCPY(dst,src,len)
#ifdef RT_LWIP_MEM_ALIGNMENT
#define MEM_ALIGNMENT RT_LWIP_MEM_ALIGNMENT
#else
#define MEM_ALIGNMENT 4
#endif
#define MEMP_OVERFLOW_CHECK 1 ////
#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1 ////
#define MEMP_OVERFLOW_CHECK 1
#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1
//#define MEM_LIBC_MALLOC 1
//#define MEM_USE_POOLS 1
//#define MEMP_USE_CUSTOM_POOLS 1

8
components/net/lwip-2.0.3/src/netif/ethernetif.c
View File

@ -210,14 +210,14 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len,
{
return -RT_ERROR;
}
rt_memcpy(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
rt_memcpy(&ina, &h->sin_addr, sizeof(ina));
SMEMCPY(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
SMEMCPY(&ina, &h->sin_addr, sizeof(ina));
lwip_freeaddrinfo(res);
if (inet_aton(inet_ntoa(ina), &target_addr) == 0)
{
return -RT_ERROR;
}
rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
SMEMCPY(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
/* new a socket */
if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
@ -340,7 +340,7 @@ static int netdev_add(struct netif *lwip_netif)
netdev->mtu = lwip_netif->mtu;
netdev->ops = &lwip_netdev_ops;
netdev->hwaddr_len = lwip_netif->hwaddr_len;
rt_memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
SMEMCPY(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
netdev->ip_addr = lwip_netif->ip_addr;
netdev->gw = lwip_netif->gw;
netdev->netmask = lwip_netif->netmask;

11
components/net/lwip-2.1.2/src/lwipopts.h
View File

@ -242,9 +242,16 @@
#endif
/* ---------- Memory options ---------- */
#ifdef RT_USING_ASM_MEMCPY
#define MEMCPY(dst,src,len) rt_memcpy(dst,src,len)
#else
#define MEMCPY(dst,src,len) memcpy(dst,src,len)
#endif /* RT_USING_ASM_MEMCPY */
#define SMEMCPY(dst,src,len) MEMCPY(dst,src,len)
#define MEM_ALIGNMENT 4
#define MEMP_OVERFLOW_CHECK 1 ////
#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1 ////
#define MEMP_OVERFLOW_CHECK 1
#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1
//#define MEM_LIBC_MALLOC 1
//#define MEM_USE_POOLS 1
//#define MEMP_USE_CUSTOM_POOLS 1

8
components/net/lwip-2.1.2/src/netif/ethernetif.c
View File

@ -208,14 +208,14 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len,
{
return -RT_ERROR;
}
rt_memcpy(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
rt_memcpy(&ina, &h->sin_addr, sizeof(ina));
SMEMCPY(&h, &res->ai_addr, sizeof(struct sockaddr_in *));
SMEMCPY(&ina, &h->sin_addr, sizeof(ina));
lwip_freeaddrinfo(res);
if (inet_aton(inet_ntoa(ina), &target_addr) == 0)
{
return -RT_ERROR;
}
rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
SMEMCPY(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t));
/* new a socket */
if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
@ -338,7 +338,7 @@ static int netdev_add(struct netif *lwip_netif)
netdev->mtu = lwip_netif->mtu;
netdev->ops = &lwip_netdev_ops;
netdev->hwaddr_len = lwip_netif->hwaddr_len;
rt_memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
SMEMCPY(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
netdev->ip_addr = lwip_netif->ip_addr;
netdev->gw = lwip_netif->gw;
netdev->netmask = lwip_netif->netmask;

4
src/Kconfig
View File

@ -131,6 +131,10 @@ config RT_KSERVICE_USING_TINY_SIZE
bool "Enable kservice to use tiny size"
default n
config RT_USING_ASM_MEMCPY
bool
default n
endmenu
menuconfig RT_DEBUG

4
src/idle.c
View File

@ -139,7 +139,7 @@ rt_err_t rt_thread_idle_delhook(void (*hook)(void))
#ifdef RT_USING_MODULE
/* Return whether there is defunctional thread to be deleted. */
rt_inline int _has_defunct_thread(void)
rt_inline int _idle_has_defunct_thread(void)
{
/* The rt_list_isempty has prototype of "int rt_list_isempty(const rt_list_t *l)".
* So the compiler has a good reason that the _rt_thread_defunct list does
@ -207,7 +207,7 @@ static void rt_defunct_execute(void)
#ifdef RT_USING_MODULE
/* check whether list is empty */
if (!_has_defunct_thread())
if (!_idle_has_defunct_thread())
{
rt_hw_interrupt_enable(lock);
break;

98
src/ipc.c
View File

@ -68,7 +68,7 @@ extern void (*rt_object_put_hook)(struct rt_object *object);
*
* @warning This function can be called from all IPC initialization and creation.
*/
rt_inline rt_err_t rt_ipc_object_init(struct rt_ipc_object *ipc)
rt_inline rt_err_t _ipc_object_init(struct rt_ipc_object *ipc)
{
/* initialize ipc object */
rt_list_init(&(ipc->suspend_thread));
@ -106,7 +106,7 @@ rt_inline rt_err_t rt_ipc_object_init(struct rt_ipc_object *ipc)
* rt_sem_take(), rt_mutex_take(), rt_event_recv(), rt_mb_send_wait(),
* rt_mb_recv(), rt_mq_recv(), rt_mq_send_wait()
*/
rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t *list,
rt_inline rt_err_t _ipc_list_suspend(rt_list_t *list,
struct rt_thread *thread,
rt_uint8_t flag)
{
@ -175,7 +175,7 @@ rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t *list,
* rt_sem_release(), rt_mutex_release(), rt_mb_send_wait(), rt_mq_send_wait(),
* rt_mb_urgent(), rt_mb_recv(), rt_mq_urgent(), rt_mq_recv(),
*/
rt_inline rt_err_t rt_ipc_list_resume(rt_list_t *list)
rt_inline rt_err_t _ipc_list_resume(rt_list_t *list)
{
struct rt_thread *thread;
@ -204,7 +204,7 @@ rt_inline rt_err_t rt_ipc_list_resume(rt_list_t *list)
* When the return value is any other values, it means this operation failed.
*
*/
rt_inline rt_err_t rt_ipc_list_resume_all(rt_list_t *list)
rt_inline rt_err_t _ipc_list_resume_all(rt_list_t *list)
{
struct rt_thread *thread;
register rt_ubase_t temp;
@ -292,7 +292,7 @@ rt_err_t rt_sem_init(rt_sem_t sem,
rt_object_init(&(sem->parent.parent), RT_Object_Class_Semaphore, name);
/* initialize ipc object */
rt_ipc_object_init(&(sem->parent));
_ipc_object_init(&(sem->parent));
/* set initial value */
sem->value = (rt_uint16_t)value;
@ -331,7 +331,7 @@ rt_err_t rt_sem_detach(rt_sem_t sem)
RT_ASSERT(rt_object_is_systemobject(&sem->parent.parent));
/* wakeup all suspended threads */
rt_ipc_list_resume_all(&(sem->parent.suspend_thread));
_ipc_list_resume_all(&(sem->parent.suspend_thread));
/* detach semaphore object */
rt_object_detach(&(sem->parent.parent));
@ -386,7 +386,7 @@ rt_sem_t rt_sem_create(const char *name, rt_uint32_t value, rt_uint8_t flag)
return sem;
/* initialize ipc object */
rt_ipc_object_init(&(sem->parent));
_ipc_object_init(&(sem->parent));
/* set initial value */
sem->value = value;
@ -427,7 +427,7 @@ rt_err_t rt_sem_delete(rt_sem_t sem)
RT_ASSERT(rt_object_is_systemobject(&sem->parent.parent) == RT_FALSE);
/* wakeup all suspended threads */
rt_ipc_list_resume_all(&(sem->parent.suspend_thread));
_ipc_list_resume_all(&(sem->parent.suspend_thread));
/* delete semaphore object */
rt_object_delete(&(sem->parent.parent));
@ -513,7 +513,7 @@ rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time)
thread->name));
/* suspend thread */
rt_ipc_list_suspend(&(sem->parent.suspend_thread),
_ipc_list_suspend(&(sem->parent.suspend_thread),
thread,
sem->parent.parent.flag);
@ -607,7 +607,7 @@ rt_err_t rt_sem_release(rt_sem_t sem)
if (!rt_list_isempty(&sem->parent.suspend_thread))
{
/* resume the suspended thread */
rt_ipc_list_resume(&(sem->parent.suspend_thread));
_ipc_list_resume(&(sem->parent.suspend_thread));
need_schedule = RT_TRUE;
}
else
@ -667,7 +667,7 @@ rt_err_t rt_sem_control(rt_sem_t sem, int cmd, void *arg)
level = rt_hw_interrupt_disable();
/* resume all waiting thread */
rt_ipc_list_resume_all(&sem->parent.suspend_thread);
_ipc_list_resume_all(&sem->parent.suspend_thread);
/* set new value */
sem->value = (rt_uint16_t)value;
@ -730,7 +730,7 @@ rt_err_t rt_mutex_init(rt_mutex_t mutex, const char *name, rt_uint8_t flag)
rt_object_init(&(mutex->parent.parent), RT_Object_Class_Mutex, name);
/* initialize ipc object */
rt_ipc_object_init(&(mutex->parent));
_ipc_object_init(&(mutex->parent));
mutex->value = 1;
mutex->owner = RT_NULL;
@ -771,7 +771,7 @@ rt_err_t rt_mutex_detach(rt_mutex_t mutex)
RT_ASSERT(rt_object_is_systemobject(&mutex->parent.parent));
/* wakeup all suspended threads */
rt_ipc_list_resume_all(&(mutex->parent.suspend_thread));
_ipc_list_resume_all(&(mutex->parent.suspend_thread));
/* detach mutex object */
rt_object_detach(&(mutex->parent.parent));
@ -813,7 +813,7 @@ rt_mutex_t rt_mutex_create(const char *name, rt_uint8_t flag)
return mutex;
/* initialize ipc object */
rt_ipc_object_init(&(mutex->parent));
_ipc_object_init(&(mutex->parent));
mutex->value = 1;
mutex->owner = RT_NULL;
@ -856,7 +856,7 @@ rt_err_t rt_mutex_delete(rt_mutex_t mutex)
RT_ASSERT(rt_object_is_systemobject(&mutex->parent.parent) == RT_FALSE);
/* wakeup all suspended threads */
rt_ipc_list_resume_all(&(mutex->parent.suspend_thread));
_ipc_list_resume_all(&(mutex->parent.suspend_thread));
/* delete mutex object */
rt_object_delete(&(mutex->parent.parent));
@ -985,7 +985,7 @@ __again:
}
/* suspend current thread */
rt_ipc_list_suspend(&(mutex->parent.suspend_thread),
_ipc_list_suspend(&(mutex->parent.suspend_thread),
thread,
mutex->parent.parent.flag);
@ -1150,7 +1150,7 @@ rt_err_t rt_mutex_release(rt_mutex_t mutex)
}
/* resume thread */
rt_ipc_list_resume(&(mutex->parent.suspend_thread));
_ipc_list_resume(&(mutex->parent.suspend_thread));
need_schedule = RT_TRUE;
}
@ -1269,7 +1269,7 @@ rt_err_t rt_event_init(rt_event_t event, const char *name, rt_uint8_t flag)
event->parent.parent.flag = flag;
/* initialize ipc object */
rt_ipc_object_init(&(event->parent));
_ipc_object_init(&(event->parent));
/* initialize event */
event->set = 0;
@ -1305,7 +1305,7 @@ rt_err_t rt_event_detach(rt_event_t event)
RT_ASSERT(rt_object_is_systemobject(&event->parent.parent));
/* resume all suspended thread */
rt_ipc_list_resume_all(&(event->parent.suspend_thread));
_ipc_list_resume_all(&(event->parent.suspend_thread));
/* detach event object */
rt_object_detach(&(event->parent.parent));
@ -1358,7 +1358,7 @@ rt_event_t rt_event_create(const char *name, rt_uint8_t flag)
event->parent.parent.flag = flag;
/* initialize ipc object */
rt_ipc_object_init(&(event->parent));
_ipc_object_init(&(event->parent));
/* initialize event */
event->set = 0;
@ -1396,7 +1396,7 @@ rt_err_t rt_event_delete(rt_event_t event)
RT_DEBUG_NOT_IN_INTERRUPT;
/* resume all suspended thread */
rt_ipc_list_resume_all(&(event->parent.suspend_thread));
_ipc_list_resume_all(&(event->parent.suspend_thread));
/* delete event object */
rt_object_delete(&(event->parent.parent));
@ -1628,7 +1628,7 @@ rt_err_t rt_event_recv(rt_event_t event,
thread->event_info = option;
/* put thread to suspended thread list */
rt_ipc_list_suspend(&(event->parent.suspend_thread),
_ipc_list_suspend(&(event->parent.suspend_thread),
thread,
event->parent.parent.flag);
@ -1700,7 +1700,7 @@ rt_err_t rt_event_control(rt_event_t event, int cmd, void *arg)
level = rt_hw_interrupt_disable();
/* resume all waiting thread */
rt_ipc_list_resume_all(&event->parent.suspend_thread);
_ipc_list_resume_all(&event->parent.suspend_thread);
/* initialize event set */
event->set = 0;
@ -1781,7 +1781,7 @@ rt_err_t rt_mb_init(rt_mailbox_t mb,
mb->parent.parent.flag = flag;
/* initialize ipc object */
rt_ipc_object_init(&(mb->parent));
_ipc_object_init(&(mb->parent));
/* initialize mailbox */
mb->msg_pool = (rt_ubase_t *)msgpool;
@ -1824,9 +1824,9 @@ rt_err_t rt_mb_detach(rt_mailbox_t mb)
RT_ASSERT(rt_object_is_systemobject(&mb->parent.parent));
/* resume all suspended thread */
rt_ipc_list_resume_all(&(mb->parent.suspend_thread));
_ipc_list_resume_all(&(mb->parent.suspend_thread));
/* also resume all mailbox private suspended thread */
rt_ipc_list_resume_all(&(mb->suspend_sender_thread));
_ipc_list_resume_all(&(mb->suspend_sender_thread));
/* detach mailbox object */
rt_object_detach(&(mb->parent.parent));
@ -1882,7 +1882,7 @@ rt_mailbox_t rt_mb_create(const char *name, rt_size_t size, rt_uint8_t flag)
mb->parent.parent.flag = flag;
/* initialize ipc object */
rt_ipc_object_init(&(mb->parent));
_ipc_object_init(&(mb->parent));
/* initialize mailbox */
mb->size = size;
@ -1934,10 +1934,10 @@ rt_err_t rt_mb_delete(rt_mailbox_t mb)
RT_ASSERT(rt_object_is_systemobject(&mb->parent.parent) == RT_FALSE);
/* resume all suspended thread */
rt_ipc_list_resume_all(&(mb->parent.suspend_thread));
_ipc_list_resume_all(&(mb->parent.suspend_thread));
/* also resume all mailbox private suspended thread */
rt_ipc_list_resume_all(&(mb->suspend_sender_thread));
_ipc_list_resume_all(&(mb->suspend_sender_thread));
/* free mailbox pool */
RT_KERNEL_FREE(mb->msg_pool);
@ -2020,7 +2020,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb,
RT_DEBUG_IN_THREAD_CONTEXT;
/* suspend current thread */
rt_ipc_list_suspend(&(mb->suspend_sender_thread),
_ipc_list_suspend(&(mb->suspend_sender_thread),
thread,
mb->parent.parent.flag);
@ -2087,7 +2087,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb,
/* resume suspended thread */
if (!rt_list_isempty(&mb->parent.suspend_thread))
{
rt_ipc_list_resume(&(mb->parent.suspend_thread));
_ipc_list_resume(&(mb->parent.suspend_thread));
/* enable interrupt */
rt_hw_interrupt_enable(temp);
@ -2183,7 +2183,7 @@ rt_err_t rt_mb_urgent(rt_mailbox_t mb, rt_ubase_t value)
/* resume suspended thread */
if (!rt_list_isempty(&mb->parent.suspend_thread))
{
rt_ipc_list_resume(&(mb->parent.suspend_thread));
_ipc_list_resume(&(mb->parent.suspend_thread));
/* enable interrupt */
rt_hw_interrupt_enable(temp);
@ -2266,7 +2266,7 @@ rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout)
RT_DEBUG_IN_THREAD_CONTEXT;
/* suspend current thread */
rt_ipc_list_suspend(&(mb->parent.suspend_thread),
_ipc_list_suspend(&(mb->parent.suspend_thread),
thread,
mb->parent.parent.flag);
@ -2329,7 +2329,7 @@ rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout)
/* resume suspended thread */
if (!rt_list_isempty(&(mb->suspend_sender_thread)))
{
rt_ipc_list_resume(&(mb->suspend_sender_thread));
_ipc_list_resume(&(mb->suspend_sender_thread));
/* enable interrupt */
rt_hw_interrupt_enable(temp);
@ -2379,9 +2379,9 @@ rt_err_t rt_mb_control(rt_mailbox_t mb, int cmd, void *arg)
level = rt_hw_interrupt_disable();
/* resume all waiting thread */
rt_ipc_list_resume_all(&(mb->parent.suspend_thread));
_ipc_list_resume_all(&(mb->parent.suspend_thread));
/* also resume all mailbox private suspended thread */
rt_ipc_list_resume_all(&(mb->suspend_sender_thread));
_ipc_list_resume_all(&(mb->suspend_sender_thread));
/* re-init mailbox */
mb->entry = 0;
@ -2478,7 +2478,7 @@ rt_err_t rt_mq_init(rt_mq_t mq,
mq->parent.parent.flag = flag;
/* initialize ipc object */
rt_ipc_object_init(&(mq->parent));
_ipc_object_init(&(mq->parent));
/* set message pool */
mq->msg_pool = msgpool;
@ -2538,9 +2538,9 @@ rt_err_t rt_mq_detach(rt_mq_t mq)
RT_ASSERT(rt_object_is_systemobject(&mq->parent.parent));
/* resume all suspended thread */
rt_ipc_list_resume_all(&mq->parent.suspend_thread);
_ipc_list_resume_all(&mq->parent.suspend_thread);
/* also resume all message queue private suspended thread */
rt_ipc_list_resume_all(&(mq->suspend_sender_thread));
_ipc_list_resume_all(&(mq->suspend_sender_thread));
/* detach message queue object */
rt_object_detach(&(mq->parent.parent));
@ -2602,7 +2602,7 @@ rt_mq_t rt_mq_create(const char *name,
mq->parent.parent.flag = flag;
/* initialize ipc object */
rt_ipc_object_init(&(mq->parent));
_ipc_object_init(&(mq->parent));
/* initialize message queue */
@ -2673,9 +2673,9 @@ rt_err_t rt_mq_delete(rt_mq_t mq)
RT_ASSERT(rt_object_is_systemobject(&mq->parent.parent) == RT_FALSE);
/* resume all suspended thread */
rt_ipc_list_resume_all(&(mq->parent.suspend_thread));
_ipc_list_resume_all(&(mq->parent.suspend_thread));
/* also resume all message queue private suspended thread */
rt_ipc_list_resume_all(&(mq->suspend_sender_thread));
_ipc_list_resume_all(&(mq->suspend_sender_thread));
/* free message queue pool */
RT_KERNEL_FREE(mq->msg_pool);
@ -2776,7 +2776,7 @@ rt_err_t rt_mq_send_wait(rt_mq_t mq,
RT_DEBUG_IN_THREAD_CONTEXT;
/* suspend current thread */
rt_ipc_list_suspend(&(mq->suspend_sender_thread),
_ipc_list_suspend(&(mq->suspend_sender_thread),
thread,
mq->parent.parent.flag);
@ -2862,7 +2862,7 @@ rt_err_t rt_mq_send_wait(rt_mq_t mq,
/* resume suspended thread */
if (!rt_list_isempty(&mq->parent.suspend_thread))
{
rt_ipc_list_resume(&(mq->parent.suspend_thread));
_ipc_list_resume(&(mq->parent.suspend_thread));
/* enable interrupt */
rt_hw_interrupt_enable(temp);
@ -2991,7 +2991,7 @@ rt_err_t rt_mq_urgent(rt_mq_t mq, const void *buffer, rt_size_t size)
/* resume suspended thread */
if (!rt_list_isempty(&mq->parent.suspend_thread))
{
rt_ipc_list_resume(&(mq->parent.suspend_thread));
_ipc_list_resume(&(mq->parent.suspend_thread));
/* enable interrupt */
rt_hw_interrupt_enable(temp);
@ -3081,7 +3081,7 @@ rt_err_t rt_mq_recv(rt_mq_t mq,
}
/* suspend current thread */
rt_ipc_list_suspend(&(mq->parent.suspend_thread),
_ipc_list_suspend(&(mq->parent.suspend_thread),
thread,
mq->parent.parent.flag);
@ -3157,7 +3157,7 @@ rt_err_t rt_mq_recv(rt_mq_t mq,
/* resume suspended thread */
if (!rt_list_isempty(&(mq->suspend_sender_thread)))
{
rt_ipc_list_resume(&(mq->suspend_sender_thread));
_ipc_list_resume(&(mq->suspend_sender_thread));
/* enable interrupt */
rt_hw_interrupt_enable(temp);
@ -3208,9 +3208,9 @@ rt_err_t rt_mq_control(rt_mq_t mq, int cmd, void *arg)
level = rt_hw_interrupt_disable();
/* resume all waiting thread */
rt_ipc_list_resume_all(&mq->parent.suspend_thread);
_ipc_list_resume_all(&mq->parent.suspend_thread);
/* also resume all message queue private suspended thread */
rt_ipc_list_resume_all(&(mq->suspend_sender_thread));
_ipc_list_resume_all(&(mq->suspend_sender_thread));
/* release all message in the queue */
while (mq->msg_queue_head != RT_NULL)

4
src/kservice.c
View File

@ -198,6 +198,7 @@ RT_WEAK void *rt_memset(void *s, int c, rt_ubase_t count)
}
RTM_EXPORT(rt_memset);
#ifndef RT_USING_ASM_MEMCPY
/**
* This function will copy memory content from source address to destination
* address.
@ -208,7 +209,7 @@ RTM_EXPORT(rt_memset);
*
* @return the address of destination memory
*/
RT_WEAK void *rt_memcpy(void *dst, const void *src, rt_ubase_t count)
void *rt_memcpy(void *dst, const void *src, rt_ubase_t count)
{
#ifdef RT_KSERVICE_USING_TINY_SIZE
char *tmp = (char *)dst, *s = (char *)src;
@ -280,6 +281,7 @@ RT_WEAK void *rt_memcpy(void *dst, const void *src, rt_ubase_t count)
#endif /* RT_KSERVICE_USING_TINY_SIZE */
}
RTM_EXPORT(rt_memcpy);
#endif /* RT_USING_ASM_MEMCPY */
#ifndef RT_KSERVICE_USING_STDLIB

14
src/scheduler.c
View File

@ -23,7 +23,7 @@
* 2013-12-21 Grissiom add rt_critical_level
* 2018-11-22 Jesven remove the current task from ready queue
* add per cpu ready queue
* add _get_highest_priority_thread to find highest priority task
* add _scheduler_get_highest_priority_thread to find highest priority task
* rt_schedule_insert_thread won't insert current task to ready queue
* in smp version, rt_hw_context_switch_interrupt maybe switch to
* new task directly
@ -119,7 +119,7 @@ static void _rt_scheduler_stack_check(struct rt_thread *thread)
* get the highest priority thread in ready queue
*/
#ifdef RT_USING_SMP
static struct rt_thread* _get_highest_priority_thread(rt_ubase_t *highest_prio)
static struct rt_thread* _scheduler_get_highest_priority_thread(rt_ubase_t *highest_prio)
{
register struct rt_thread *highest_priority_thread;
register rt_ubase_t highest_ready_priority, local_highest_ready_priority;
@ -155,7 +155,7 @@ static struct rt_thread* _get_highest_priority_thread(rt_ubase_t *highest_prio)
return highest_priority_thread;
}
#else
static struct rt_thread* _get_highest_priority_thread(rt_ubase_t *highest_prio)
static struct rt_thread* _scheduler_get_highest_priority_thread(rt_ubase_t *highest_prio)
{
register struct rt_thread *highest_priority_thread;
register rt_ubase_t highest_ready_priority;
@ -241,7 +241,7 @@ void rt_system_scheduler_start(void)
register struct rt_thread *to_thread;
rt_ubase_t highest_ready_priority;
to_thread = _get_highest_priority_thread(&highest_ready_priority);
to_thread = _scheduler_get_highest_priority_thread(&highest_ready_priority);
#ifdef RT_USING_SMP
to_thread->oncpu = rt_hw_cpu_id();
@ -329,7 +329,7 @@ void rt_schedule(void)
if (rt_thread_ready_priority_group != 0 || pcpu->priority_group != 0)
{
to_thread = _get_highest_priority_thread(&highest_ready_priority);
to_thread = _scheduler_get_highest_priority_thread(&highest_ready_priority);
current_thread->oncpu = RT_CPU_DETACHED;
if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_RUNNING)
{
@ -429,7 +429,7 @@ void rt_schedule(void)
/* need_insert_from_thread: need to insert from_thread to ready queue */
int need_insert_from_thread = 0;
to_thread = _get_highest_priority_thread(&highest_ready_priority);
to_thread = _scheduler_get_highest_priority_thread(&highest_ready_priority);
if ((rt_current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_RUNNING)
{
@ -582,7 +582,7 @@ void rt_scheduler_do_irq_switch(void *context)
if (rt_thread_ready_priority_group != 0 || pcpu->priority_group != 0)
{
to_thread = _get_highest_priority_thread(&highest_ready_priority);
to_thread = _scheduler_get_highest_priority_thread(&highest_ready_priority);
current_thread->oncpu = RT_CPU_DETACHED;
if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_RUNNING)
{