Merge pull request #79 from weety/at91sam9260
Use SRAM as EMAC transmit buffer, to avoid the underrun error, especiall...
This commit is contained in:
Bernard Xiong
commit
93a01ee949
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@ -37,16 +37,54 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
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#define BD_CACHE_WRITEBACK(addr, size)
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#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
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/* EMAC internal utility function */
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rt_inline unsigned long emac_virt_to_phys(unsigned long addr)
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{
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return addr;
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}
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#define CONFIG_RMII
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#define MACB_RX_BUFFER_SIZE 4096*4
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#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
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#define AT91SAM9260_SRAM0_VIRT_BASE (0x90000000)
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#define MACB_TX_SRAM
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#if defined(MACB_TX_SRAM)
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#define MACB_TX_RING_SIZE 2
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#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
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#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE)
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#else
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#define MACB_TX_RING_SIZE 16
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#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
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#endif
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#define MACB_RX_BUFFER_SIZE (4096*4)
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#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
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#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE)
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#define TX_RING_GAP(macb) \
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(MACB_TX_RING_SIZE - (macb)->tx_pending)
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#define TX_BUFFS_AVAIL(macb) \
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(((macb)->tx_tail <= (macb)->tx_head) ? \
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(macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \
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(macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb))
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#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1))
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#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1))
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/* minimum number of free TX descriptors before waking up TX process */
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#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4)
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#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
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| MACB_BIT(ISR_ROVR))
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#define MACB_TX_TIMEOUT 1000
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#define MACB_AUTONEG_TIMEOUT 5000000
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#define MACB_LINK_TIMEOUT 500000
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#define MACB_LINK_TIMEOUT 500000
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#define CONFIG_RMII
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struct macb_dma_desc {
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rt_uint32_t addr;
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@ -75,9 +113,6 @@ struct macb_dma_desc {
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#define TXBUF_WRAP 0x40000000
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#define TXBUF_USED 0x80000000
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#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
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| MACB_BIT(ISR_ROVR))
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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@ -93,6 +128,8 @@ struct rt_macb_eth
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unsigned int rx_tail;
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unsigned int tx_head;
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unsigned int tx_tail;
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unsigned int rx_pending;
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unsigned int tx_pending;
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void *rx_buffer;
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void *tx_buffer;
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@ -100,21 +137,28 @@ struct rt_macb_eth
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struct macb_dma_desc *tx_ring;
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unsigned long rx_buffer_dma;
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unsigned long tx_buffer_dma;
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unsigned long rx_ring_dma;
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unsigned long tx_ring_dma;
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unsigned int tx_stop;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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unsigned short phy_addr;
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struct rt_semaphore mdio_bus_lock;
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struct rt_semaphore tx_lock;
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struct rt_semaphore rx_lock;
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struct rt_semaphore tx_ack;
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rt_uint32_t speed;
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rt_uint32_t duplex;
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rt_uint32_t link;
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struct rt_timer timer;
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};
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static struct rt_macb_eth macb_device;
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static struct rt_semaphore sem_ack, sem_lock;
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static void macb_tx(struct rt_macb_eth *macb);
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static void udelay(rt_uint32_t us)
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{
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@ -133,7 +177,8 @@ static void rt_macb_isr(int irq, void *param)
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while (status) {
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if (status & MACB_RX_INT_FLAGS) {
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if (status & MACB_RX_INT_FLAGS)
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{
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rsr = macb_readl(macb, RSR);
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macb_writel(macb, RSR, rsr);
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/* a frame has been received */
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@ -144,10 +189,7 @@ static void rt_macb_isr(int irq, void *param)
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if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
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MACB_BIT(ISR_RLE)))
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{
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tsr = macb_readl(macb, TSR);
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macb_writel(macb, TSR, tsr);
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/* One packet sent complete */
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rt_sem_release(&sem_ack);
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macb_tx(macb);
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}
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/*
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@ -155,7 +197,8 @@ static void rt_macb_isr(int irq, void *param)
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* add that if/when we get our hands on a full-blown MII PHY.
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*/
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if (status & MACB_BIT(HRESP)) {
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if (status & MACB_BIT(HRESP))
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{
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/*
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* TODO: Reset the hardware, and maybe move the printk
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* to a lower-priority context as well (work queue?)
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@ -243,7 +286,8 @@ static void macb_phy_reset(rt_device_t dev)
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macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
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| BMCR_ANRESTART));
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for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
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for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++)
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{
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status = macb_mdio_read(macb, MII_BMSR);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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@ -268,17 +312,20 @@ static int macb_phy_init(rt_device_t dev)
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/* Check if the PHY is up to snuff... */
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phy_id = macb_mdio_read(macb, MII_PHYSID1);
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if (phy_id == 0xffff) {
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if (phy_id == 0xffff)
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{
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rt_kprintf("%s: No PHY present\n", dev->parent.name);
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return 0;
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}
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status = macb_mdio_read(macb, MII_BMSR);
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if (!(status & BMSR_LSTATUS)) {
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if (!(status & BMSR_LSTATUS))
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{
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/* Try to re-negotiate if we don't have link already. */
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macb_phy_reset(dev);
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for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) {
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for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++)
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{
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status = macb_mdio_read(macb, MII_BMSR);
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if (status & BMSR_LSTATUS)
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break;
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@ -286,11 +333,14 @@ static int macb_phy_init(rt_device_t dev)
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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if (!(status & BMSR_LSTATUS))
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{
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rt_kprintf("%s: link down (status: 0x%04x)\n",
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dev->parent.name, status);
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return 0;
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} else {
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}
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else
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{
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adv = macb_mdio_read(macb, MII_ADVERTISE);
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lpa = macb_mdio_read(macb, MII_LPA);
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media = mii_nway_result(lpa & adv);
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@ -338,13 +388,16 @@ void macb_update_link(void *param)
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else
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link = 1;
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if (link != macb->link) {
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if (link != macb->link)
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{
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macb->link = link;
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status_change = 1;
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}
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if (status_change) {
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if (macb->link) {
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if (status_change)
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{
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if (macb->link)
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{
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adv = macb_mdio_read(macb, MII_ADVERTISE);
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lpa = macb_mdio_read(macb, MII_LPA);
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media = mii_nway_result(lpa & adv);
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@ -355,7 +408,9 @@ void macb_update_link(void *param)
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dev->parent.name, macb->speed,
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DUPLEX_FULL == macb->duplex ? "Full":"Half");
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eth_device_linkchange(&macb->parent, RT_TRUE);
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} else {
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}
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else
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{
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rt_kprintf("%s: link down\n", dev->parent.name);
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eth_device_linkchange(&macb->parent, RT_FALSE);
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}
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@ -382,19 +437,23 @@ static rt_err_t rt_macb_init(rt_device_t dev)
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/* initialize DMA descriptors */
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paddr = macb->rx_buffer_dma;
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for (i = 0; i < MACB_RX_RING_SIZE; i++) {
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for (i = 0; i < MACB_RX_RING_SIZE; i++)
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{
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if (i == (MACB_RX_RING_SIZE - 1))
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paddr |= RXADDR_WRAP;
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macb->rx_ring[i].addr = paddr;
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macb->rx_ring[i].ctrl = 0;
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paddr += 128;
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}
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for (i = 0; i < MACB_TX_RING_SIZE; i++) {
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macb->tx_ring[i].addr = 0;
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paddr = macb->tx_buffer_dma;
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for (i = 0; i < MACB_TX_RING_SIZE; i++)
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{
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macb->tx_ring[i].addr = paddr;
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if (i == (MACB_TX_RING_SIZE - 1))
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macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
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else
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macb->tx_ring[i].ctrl = TXBUF_USED;
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paddr += 1536;
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}
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macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
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@ -488,31 +547,127 @@ static rt_err_t rt_macb_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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return RT_EOK;
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}
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static void macb_tx(struct rt_macb_eth *macb)
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{
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unsigned int tail;
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unsigned int head;
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rt_uint32_t status;
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status = macb_readl(macb, TSR);
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macb_writel(macb, TSR, status);
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/*rt_kprintf("macb_tx status = %02lx\n",
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(unsigned long)status);*/
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if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE)))
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{
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int i;
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rt_kprintf("%s: TX %s, resetting buffers\n",
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macb->parent.parent.parent.name, status & MACB_BIT(UND) ?
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"underrun" : "retry limit exceeded");
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/* Transfer ongoing, disable transmitter, to avoid confusion */
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if (status & MACB_BIT(TGO))
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macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
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head = macb->tx_head;
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/*Mark all the buffer as used to avoid sending a lost buffer*/
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for (i = 0; i < MACB_TX_RING_SIZE; i++)
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macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
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/* free transmit buffer in upper layer*/
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macb->tx_head = macb->tx_tail = 0;
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/* Enable the transmitter again */
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if (status & MACB_BIT(TGO))
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macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE));
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}
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if (!(status & MACB_BIT(COMP)))
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/*
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* This may happen when a buffer becomes complete
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* between reading the ISR and scanning the
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* descriptors. Nothing to worry about.
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*/
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return;
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head = macb->tx_head;
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for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail))
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{
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rt_uint32_t bufstat;
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bufstat = macb->tx_ring[tail].ctrl;
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if (!(bufstat & MACB_BIT(TX_USED)))
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break;
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}
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macb->tx_tail = tail;
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if ((macb->tx_stop == 1) &&
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TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH)
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rt_sem_release(&macb->tx_ack);
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}
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/* ethernet device interface */
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/* transmit packet. */
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rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
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{
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unsigned long ctrl;
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struct pbuf* q;
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rt_uint8_t* bufptr;
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rt_uint32_t mapping;
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struct rt_macb_eth *macb = dev->user_data;
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unsigned int tx_head = macb->tx_head;
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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EMAC_CACHE_WRITEBACK(p->payload, p->tot_len);
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rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER);
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if (TX_BUFFS_AVAIL(macb) < 1)
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{
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rt_sem_release(&macb->tx_lock);
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rt_kprintf("Tx Ring full!\n");
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rt_kprintf("tx_head = %u, tx_tail = %u\n",
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macb->tx_head, macb->tx_tail);
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return -RT_ERROR;
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}
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macb->tx_stop = 0;
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ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
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ctrl |= TXBUF_FRAME_END;
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if (tx_head == (MACB_TX_RING_SIZE - 1)) {
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if (tx_head == (MACB_TX_RING_SIZE - 1))
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{
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ctrl |= TXBUF_WRAP;
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macb->tx_head = 0;
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} else
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macb->tx_head++;
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macb->tx_ring[tx_head].ctrl = ctrl;
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macb->tx_ring[tx_head].addr = (rt_uint32_t)p->payload;
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BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
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macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
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}
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#if defined(MACB_TX_SRAM)
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bufptr = macb->tx_buffer + tx_head * 1536;
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#else
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mapping = (unsigned long)macb->tx_buffer + tx_head * 1536;
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bufptr = (rt_uint8_t *)mapping;
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#endif
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rt_sem_release(&sem_lock);
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/* wait ack */
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rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
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for (q = p; q != NULL; q = q->next)
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{
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memcpy(bufptr, q->payload, q->len);
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bufptr += q->len;
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}
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#if !defined(MACB_TX_SRAM)
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EMAC_CACHE_WRITEBACK(mapping, p->tot_len);
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#endif
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macb->tx_ring[tx_head].ctrl = ctrl;
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BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
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tx_head = NEXT_TX(tx_head);
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macb->tx_head = tx_head;
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macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
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macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
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if (TX_BUFFS_AVAIL(macb) < 1)
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{
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macb->tx_stop = 1;
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rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER);
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}
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rt_sem_release(&macb->tx_lock);
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return RT_EOK;
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}
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@ -523,14 +678,16 @@ static void reclaim_rx_buffers(struct rt_macb_eth *macb,
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unsigned int i;
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i = macb->rx_tail;
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while (i > new_tail) {
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while (i > new_tail)
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{
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macb->rx_ring[i].addr &= ~RXADDR_USED;
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i++;
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if (i > MACB_RX_RING_SIZE)
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i = 0;
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}
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while (i < new_tail) {
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while (i < new_tail)
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{
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macb->rx_ring[i].addr &= ~RXADDR_USED;
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i++;
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}
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@ -549,19 +706,22 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
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int wrapped = 0;
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rt_uint32_t status;
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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for (;;) {
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rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER);
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for (;;)
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{
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if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
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break;
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status = macb->rx_ring[rx_tail].ctrl;
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if (status & RXBUF_FRAME_START) {
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if (status & RXBUF_FRAME_START)
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{
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if (rx_tail != macb->rx_tail)
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reclaim_rx_buffers(macb, rx_tail);
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wrapped = 0;
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}
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if (status & RXBUF_FRAME_END) {
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if (status & RXBUF_FRAME_END)
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{
|
||||
buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
|
||||
len = status & RXBUF_FRMLEN_MASK;
|
||||
p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
|
||||
|
|
@ -570,7 +730,8 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
|
|||
rt_kprintf("alloc pbuf failed\n");
|
||||
break;
|
||||
}
|
||||
if (wrapped) {
|
||||
if (wrapped)
|
||||
{
|
||||
unsigned int headlen, taillen;
|
||||
|
||||
headlen = 128 * (MACB_RX_RING_SIZE
|
||||
|
|
@ -581,7 +742,9 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
|
|||
memcpy((void *)p->payload, buffer, headlen);
|
||||
memcpy((void *)((unsigned int)p->payload + headlen),
|
||||
macb->rx_buffer, taillen);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
EMAC_CACHE_INVALIDATE(buffer, len);
|
||||
memcpy((void *)p->payload, buffer, p->len);
|
||||
}
|
||||
|
|
@ -590,15 +753,18 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
|
|||
rx_tail = 0;
|
||||
reclaim_rx_buffers(macb, rx_tail);
|
||||
break;
|
||||
} else {
|
||||
if (++rx_tail >= MACB_RX_RING_SIZE) {
|
||||
}
|
||||
else
|
||||
{
|
||||
if (++rx_tail >= MACB_RX_RING_SIZE)
|
||||
{
|
||||
wrapped = 1;
|
||||
rx_tail = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rt_sem_release(&sem_lock);
|
||||
rt_sem_release(&macb->rx_lock);
|
||||
|
||||
return p;
|
||||
}
|
||||
|
|
@ -615,25 +781,42 @@ void macb_gpio_init()
|
|||
#endif
|
||||
}
|
||||
|
||||
void macb_initialize()
|
||||
rt_err_t macb_initialize()
|
||||
{
|
||||
struct rt_macb_eth *macb = &macb_device;
|
||||
unsigned long macb_hz;
|
||||
rt_uint32_t ncfgr;
|
||||
|
||||
macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
|
||||
macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
macb->tx_ring = rt_malloc(MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
|
||||
EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
#if defined(MACB_TX_SRAM)
|
||||
macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE;
|
||||
macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE;
|
||||
macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES;
|
||||
macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES;
|
||||
#else
|
||||
macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
if (macb->tx_ring == RT_NULL)
|
||||
goto err1;
|
||||
EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring);
|
||||
macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring);
|
||||
macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE);
|
||||
if (macb->tx_buffer == RT_NULL)
|
||||
goto err2;
|
||||
macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer);
|
||||
#endif
|
||||
|
||||
macb->rx_buffer_dma = (unsigned long)macb->rx_buffer;
|
||||
macb->rx_ring_dma = (unsigned long)macb->rx_ring;
|
||||
macb->tx_ring_dma = (unsigned long)macb->tx_ring;
|
||||
macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
if (macb->rx_ring == RT_NULL)
|
||||
goto err3;
|
||||
EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
|
||||
macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring);
|
||||
macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring);
|
||||
macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
|
||||
if (macb->rx_buffer == RT_NULL)
|
||||
goto err4;
|
||||
macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer);
|
||||
|
||||
macb->rx_ring = MMU_NOCACHE_ADDR(macb->rx_ring);
|
||||
macb->tx_ring = MMU_NOCACHE_ADDR(macb->tx_ring);
|
||||
macb->tx_pending = DEF_TX_RING_PENDING;
|
||||
|
||||
macb->regs = AT91SAM9260_BASE_EMAC;
|
||||
macb->phy_addr = 0x00;
|
||||
|
|
@ -653,16 +836,41 @@ void macb_initialize()
|
|||
ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
|
||||
|
||||
macb_writel(macb, NCFGR, ncfgr);
|
||||
|
||||
macb->link = 0;
|
||||
|
||||
return RT_EOK;
|
||||
|
||||
err4:
|
||||
rt_free(macb->rx_ring);
|
||||
macb->rx_ring = RT_NULL;
|
||||
err3:
|
||||
#if !defined(MACB_TX_SRAM)
|
||||
rt_free(macb->tx_buffer);
|
||||
macb->tx_buffer = RT_NULL;
|
||||
err2:
|
||||
rt_free(macb->tx_ring);
|
||||
macb->tx_ring = RT_NULL;
|
||||
err1:
|
||||
#endif
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
void rt_hw_macb_init()
|
||||
{
|
||||
rt_err_t ret;
|
||||
at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock
|
||||
macb_gpio_init();
|
||||
rt_memset(&macb_device, 0, sizeof(macb_device));
|
||||
macb_initialize();
|
||||
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
ret = macb_initialize();
|
||||
if (ret != RT_EOK)
|
||||
{
|
||||
rt_kprintf("AT91 EMAC initialized failed\n");
|
||||
return;
|
||||
}
|
||||
rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
|
||||
macb_device.dev_addr[0] = 0x00;
|
||||
macb_device.dev_addr[1] = 0x60;
|
||||
|
|
|
|||
|
|
@ -471,7 +471,7 @@ void rt_hw_mmu_init(void)
|
|||
mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
|
||||
mmu_setmtt(0x20000000, 0x24000000-1, 0x20000000, RW_CB); /* 64M cached SDRAM memory */
|
||||
mmu_setmtt(0x00000000, 0x100000, 0x20000000, RW_CB); /* isr vector table */
|
||||
mmu_setmtt(0x90000000, 0x100000, 0x00000000, RW_CB); /* 4K cached internal memory */
|
||||
mmu_setmtt(0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB); /* 4K SRAM0 + 4k SRAM1 */
|
||||
mmu_setmtt(0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB); /* 64M none-cached SDRAM memory */
|
||||
|
||||
/* set MMU table address */
|
||||
|
|
|
|||
Loading…
Reference in New Issue