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Correct coding-style format.

This commit is contained in:
Wayne Lin 2021-12-28 13:44:17 +08:00 committed by Bernard Xiong
parent e8f4208bb2
commit 8ab54c3018
1 changed files with 4 additions and 4 deletions
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8
bsp/nuvoton/libraries/n9h30/rtt_port/drv_vpost.c
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@ -190,8 +190,8 @@ static rt_err_t vpost_layer_control(rt_device_t dev, int cmd, void *args)
case RTGRAPHIC_CTRL_WAIT_VSYNC: case RTGRAPHIC_CTRL_WAIT_VSYNC:
{ {
if (args != RT_NULL) if (args != RT_NULL)
g_u32VSyncLastCommit = g_u32VSyncBlank+1; g_u32VSyncLastCommit = g_u32VSyncBlank + 1;
if (g_u32VSyncLastCommit >= g_u32VSyncBlank) if (g_u32VSyncLastCommit >= g_u32VSyncBlank)
{ {
@ -261,13 +261,13 @@ int rt_hw_vpost_init(void)
VPOST_T *psVpostLcmInst = vpostLCMGetInstance(VPOST_USING_LCD_IDX); VPOST_T *psVpostLcmInst = vpostLCMGetInstance(VPOST_USING_LCD_IDX);
RT_ASSERT(psVpostLcmInst != RT_NULL); RT_ASSERT(psVpostLcmInst != RT_NULL);
if ( (psVpostLcmInst->u32DevWidth * psVpostLcmInst->u32DevHeight) > (480*272) ) if ((psVpostLcmInst->u32DevWidth * psVpostLcmInst->u32DevHeight) > (480 * 272))
{ {
/* LCD clock is selected from UPLL and divide to 20MHz */ /* LCD clock is selected from UPLL and divide to 20MHz */
outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0xE18); outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0xE18);
/* LCD clock is selected from UPLL and divide to 30MHz */ /* LCD clock is selected from UPLL and divide to 30MHz */
//outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0x918); //outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0x918);
} }
else else
{ {