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update Fujistu FM3 porting

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1990 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz@gmail.com 2012-03-05 01:13:30 +00:00
parent 9ca7f9dc6b
commit 887bcbbad8
68 changed files with 14345 additions and 273 deletions
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19
bsp/mb9bf500r/CMSIS/SConscript Normal file
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@ -0,0 +1,19 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
src = Glob('*.c')
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src = src + ['start_gcc.S']
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['start_rvds.S']
elif rtconfig.CROSS_TOOL == 'iar':
src = src + ['start_iar.S']
CPPPATH = [GetCurrentDir()]
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '')
Return('group')

0
bsp/fm3/CMSIS/core_cm3.c → bsp/mb9bf500r/CMSIS/core_cm3.c
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0
bsp/fm3/CMSIS/core_cm3.h → bsp/mb9bf500r/CMSIS/core_cm3.h
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0
bsp/fm3/CMSIS/core_cmFunc.h → bsp/mb9bf500r/CMSIS/core_cmFunc.h
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0
bsp/fm3/CMSIS/core_cmInstr.h → bsp/mb9bf500r/CMSIS/core_cmInstr.h
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0
bsp/fm3/CMSIS/mb9bf506r.h → bsp/mb9bf500r/CMSIS/mb9bf506r.h
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0
bsp/fm3/CMSIS/start_gcc.S → bsp/mb9bf500r/CMSIS/start_gcc.S
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0
bsp/fm3/CMSIS/start_iar.S → bsp/mb9bf500r/CMSIS/start_iar.S
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0
bsp/fm3/CMSIS/start_rvds.S → bsp/mb9bf500r/CMSIS/start_rvds.S
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0
bsp/fm3/CMSIS/system_mb9bf50x.c → bsp/mb9bf500r/CMSIS/system_mb9bf50x.c
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0
bsp/fm3/CMSIS/system_mb9bf50x.h → bsp/mb9bf500r/CMSIS/system_mb9bf50x.h
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0
bsp/fm3/mb9bf500r/SConscript → bsp/mb9bf500r/SConscript
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4
bsp/fm3/mb9bf500r/SConstruct → bsp/mb9bf500r/SConstruct
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@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'): if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT') RTT_ROOT = os.getenv('RTT_ROOT')
else: else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import * from building import *
@ -30,7 +30,7 @@ Export('rtconfig')
# prepare building environment # prepare building environment
objs = PrepareBuilding(env, RTT_ROOT) objs = PrepareBuilding(env, RTT_ROOT)
objs = objs + SConscript('../CMSIS/SConscript', variant_dir='build/bsp/Libraries', duplicate=0) objs = objs + SConscript('CMSIS/SConscript', variant_dir='build/bsp/CMSIS', duplicate=0)
# build program # build program
env.Program(TARGET, objs) env.Program(TARGET, objs)

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bsp/fm3/mb9bf500r/adc.c → bsp/mb9bf500r/adc.c
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bsp/fm3/mb9bf500r/adc.h → bsp/mb9bf500r/adc.h
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bsp/fm3/mb9bf500r/application.c → bsp/mb9bf500r/application.c
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0
bsp/fm3/mb9bf500r/board.c → bsp/mb9bf500r/board.c
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bsp/fm3/mb9bf500r/board.h → bsp/mb9bf500r/board.h
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bsp/fm3/mb9bf500r/cpuusage.c → bsp/mb9bf500r/cpuusage.c
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0
bsp/fm3/mb9bf500r/cpuusage.h → bsp/mb9bf500r/cpuusage.h
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170
bsp/fm3/mb9bf500r/fm3_easy_kit.ewp → bsp/mb9bf500r/fm3_easy_kit.ewp
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@ -286,9 +286,9 @@
<option> <option>
<name>CCIncludePath2</name> <name>CCIncludePath2</name>
<state>$PROJ_DIR$\</state> <state>$PROJ_DIR$\</state>
<state>$PROJ_DIR$\..\CMSIS</state> <state>$PROJ_DIR$\CMSIS</state>
<state>$PROJ_DIR$\..\..\..\include</state> <state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\..\..\..\components\rtgui\include</state> <state>$PROJ_DIR$\..\..\components\rtgui\include</state>
</option> </option>
<option> <option>
<name>CCStdIncCheck</name> <name>CCStdIncCheck</name>
@ -1740,259 +1740,259 @@
<group> <group>
<name>CMSIS</name> <name>CMSIS</name>
<file> <file>
<name>$PROJ_DIR$\..\CMSIS\core_cm3.c</name> <name>$PROJ_DIR$\CMSIS\core_cm3.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\CMSIS\start_iar.S</name> <name>$PROJ_DIR$\CMSIS\start_iar.S</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\CMSIS\system_mb9bf50x.c</name> <name>$PROJ_DIR$\CMSIS\system_mb9bf50x.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>FM3</name> <name>FM3</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\context_iar.S</name> <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c</name> <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>Kernel</name> <name>Kernel</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\clock.c</name> <name>$PROJ_DIR$\..\..\src\clock.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\device.c</name> <name>$PROJ_DIR$\..\..\src\device.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\idle.c</name> <name>$PROJ_DIR$\..\..\src\idle.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\ipc.c</name> <name>$PROJ_DIR$\..\..\src\ipc.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\irq.c</name> <name>$PROJ_DIR$\..\..\src\irq.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\kservice.c</name> <name>$PROJ_DIR$\..\..\src\kservice.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\mem.c</name> <name>$PROJ_DIR$\..\..\src\mem.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\mempool.c</name> <name>$PROJ_DIR$\..\..\src\mempool.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\module.c</name> <name>$PROJ_DIR$\..\..\src\module.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\object.c</name> <name>$PROJ_DIR$\..\..\src\object.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\rtm.c</name> <name>$PROJ_DIR$\..\..\src\rtm.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\scheduler.c</name> <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\slab.c</name> <name>$PROJ_DIR$\..\..\src\slab.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\thread.c</name> <name>$PROJ_DIR$\..\..\src\thread.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\timer.c</name> <name>$PROJ_DIR$\..\..\src\timer.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>Rtgui</name> <name>Rtgui</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\about_view.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\about_view.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\asc12font.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\asc12font.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\asc16font.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\asc16font.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\blit.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\blit.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\box.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\box.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\button.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\button.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\checkbox.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\checkbox.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\color.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\color.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\combobox.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\combobox.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\container.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\container.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\dc.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\dc.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\dc_buffer.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\dc_buffer.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\dc_client.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\dc_client.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\dc_hw.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\dc_hw.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\server\driver.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\server\driver.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\filelist_view.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\filelist_view.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\filerw.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\filerw.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\font.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\font.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\font_bmp.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\font_bmp.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\font_freetype.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\font_freetype.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\font_hz_bmp.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\font_hz_bmp.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\font_hz_file.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\font_hz_file.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\framebuffer_driver.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\framebuffer_driver.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\hz12font.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\hz12font.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\hz16font.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\hz16font.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\iconbox.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\iconbox.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image_bmp.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image_bmp.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image_container.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image_container.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image_hdc.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image_hdc.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image_jpg.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image_jpg.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image_png.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image_png.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\image_xpm.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\image_xpm.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\label.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\label.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\list_view.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\list_view.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\listbox.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\listbox.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\listctrl.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\listctrl.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\menu.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\menu.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\server\mouse.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\server\mouse.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\notebook.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\notebook.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\server\panel.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\server\panel.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\pixel_driver.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\pixel_driver.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\progressbar.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\progressbar.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\radiobox.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\radiobox.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\region.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\region.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\rtgui_object.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\rtgui_object.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\rtgui_system.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\rtgui_system.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\rtgui_theme.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\rtgui_theme.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\common\rtgui_xml.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\common\rtgui_xml.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\scrollbar.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\scrollbar.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\server\server.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\server\server.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\slider.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\slider.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\staticline.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\staticline.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\textbox.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\textbox.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\textview.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\textview.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\title.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\title.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\toplevel.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\toplevel.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\server\topwin.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\server\topwin.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\view.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\view.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\widget.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\widget.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\window.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\window.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\rtgui\widgets\workbench.c</name> <name>$PROJ_DIR$\..\..\components\rtgui\widgets\workbench.c</name>
</file> </file>
</group> </group>
<group> <group>

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bsp/fm3/mb9bf500r/fm3_easy_kit.eww → bsp/mb9bf500r/fm3_easy_kit.eww
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bsp/fm3/mb9bf500r/font.h → bsp/mb9bf500r/font.h
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bsp/fm3/mb9bf500r/info.c → bsp/mb9bf500r/info.c
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bsp/fm3/mb9bf500r/key.c → bsp/mb9bf500r/key.c
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bsp/fm3/mb9bf500r/key.h → bsp/mb9bf500r/key.h
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bsp/fm3/mb9bf500r/lcd.c → bsp/mb9bf500r/lcd.c
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bsp/fm3/mb9bf500r/lcd.h → bsp/mb9bf500r/lcd.h
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bsp/fm3/mb9bf500r/led.c → bsp/mb9bf500r/led.c
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bsp/fm3/mb9bf500r/led.h → bsp/mb9bf500r/led.h
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bsp/fm3/mb9bf500r/mb9bf500r.icf → bsp/mb9bf500r/mb9bf500r.icf
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bsp/fm3/mb9bf500r/project.uvopt → bsp/mb9bf500r/project.uvopt
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@ -151,7 +151,7 @@
<Group> <Group>
<GroupName>Startup</GroupName> <GroupName>Startup</GroupName>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<File> <File>
@ -272,10 +272,10 @@
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>39</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>14</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>25</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>.\info.c</PathWithFileName> <PathWithFileName>.\info.c</PathWithFileName>
<FilenameWithoutPath>info.c</FilenameWithoutPath> <FilenameWithoutPath>info.c</FilenameWithoutPath>
@ -284,7 +284,7 @@
<Group> <Group>
<GroupName>FM3</GroupName> <GroupName>FM3</GroupName>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<File> <File>
@ -293,12 +293,12 @@
<FileType>2</FileType> <FileType>2</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>7</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>116</TopLine> <TopLine>1</TopLine>
<CurrentLine>116</CurrentLine> <CurrentLine>1</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</PathWithFileName> <PathWithFileName>..\..\libcpu\arm\cortex-m3\context_rvds.S</PathWithFileName>
<FilenameWithoutPath>context_rvds.S</FilenameWithoutPath> <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -307,19 +307,19 @@
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>22</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>1</TopLine> <TopLine>0</TopLine>
<CurrentLine>1</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\cortex-m3\cpuport.c</PathWithFileName> <PathWithFileName>..\..\libcpu\arm\cortex-m3\cpuport.c</PathWithFileName>
<FilenameWithoutPath>cpuport.c</FilenameWithoutPath> <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
</File> </File>
</Group> </Group>
<Group> <Group>
<GroupName>CMSIS</GroupName> <GroupName>CMSIS</GroupName>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<File> <File>
@ -330,16 +330,16 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>1</TopLine> <TopLine>0</TopLine>
<CurrentLine>1</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\CMSIS\core_cm3.c</PathWithFileName> <PathWithFileName>.\CMSIS\core_cm3.c</PathWithFileName>
<FilenameWithoutPath>core_cm3.c</FilenameWithoutPath> <FilenameWithoutPath>core_cm3.c</FilenameWithoutPath>
</File> </File>
<File> <File>
<GroupNumber>3</GroupNumber> <GroupNumber>3</GroupNumber>
<FileNumber>13</FileNumber> <FileNumber>13</FileNumber>
<FileType>1</FileType> <FileType>2</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
@ -347,28 +347,28 @@
<TopLine>1</TopLine> <TopLine>1</TopLine>
<CurrentLine>1</CurrentLine> <CurrentLine>1</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\CMSIS\system_mb9bf50x.c</PathWithFileName> <PathWithFileName>.\CMSIS\start_rvds.S</PathWithFileName>
<FilenameWithoutPath>system_mb9bf50x.c</FilenameWithoutPath> <FilenameWithoutPath>start_rvds.S</FilenameWithoutPath>
</File> </File>
<File> <File>
<GroupNumber>3</GroupNumber> <GroupNumber>3</GroupNumber>
<FileNumber>14</FileNumber> <FileNumber>14</FileNumber>
<FileType>2</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>39</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>47</TopLine> <TopLine>0</TopLine>
<CurrentLine>61</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\CMSIS\start_rvds.S</PathWithFileName> <PathWithFileName>.\CMSIS\system_mb9bf50x.c</PathWithFileName>
<FilenameWithoutPath>start_rvds.S</FilenameWithoutPath> <FilenameWithoutPath>system_mb9bf50x.c</FilenameWithoutPath>
</File> </File>
</Group> </Group>
<Group> <Group>
<GroupName>Kernel</GroupName> <GroupName>Kernel</GroupName>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<File> <File>
@ -382,7 +382,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\clock.c</PathWithFileName> <PathWithFileName>..\..\src\clock.c</PathWithFileName>
<FilenameWithoutPath>clock.c</FilenameWithoutPath> <FilenameWithoutPath>clock.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -396,7 +396,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\device.c</PathWithFileName> <PathWithFileName>..\..\src\device.c</PathWithFileName>
<FilenameWithoutPath>device.c</FilenameWithoutPath> <FilenameWithoutPath>device.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -410,7 +410,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\idle.c</PathWithFileName> <PathWithFileName>..\..\src\idle.c</PathWithFileName>
<FilenameWithoutPath>idle.c</FilenameWithoutPath> <FilenameWithoutPath>idle.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -424,7 +424,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\ipc.c</PathWithFileName> <PathWithFileName>..\..\src\ipc.c</PathWithFileName>
<FilenameWithoutPath>ipc.c</FilenameWithoutPath> <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -438,7 +438,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\irq.c</PathWithFileName> <PathWithFileName>..\..\src\irq.c</PathWithFileName>
<FilenameWithoutPath>irq.c</FilenameWithoutPath> <FilenameWithoutPath>irq.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -452,7 +452,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\kservice.c</PathWithFileName> <PathWithFileName>..\..\src\kservice.c</PathWithFileName>
<FilenameWithoutPath>kservice.c</FilenameWithoutPath> <FilenameWithoutPath>kservice.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -466,7 +466,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\mem.c</PathWithFileName> <PathWithFileName>..\..\src\mem.c</PathWithFileName>
<FilenameWithoutPath>mem.c</FilenameWithoutPath> <FilenameWithoutPath>mem.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -480,7 +480,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\mempool.c</PathWithFileName> <PathWithFileName>..\..\src\mempool.c</PathWithFileName>
<FilenameWithoutPath>mempool.c</FilenameWithoutPath> <FilenameWithoutPath>mempool.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -494,7 +494,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\module.c</PathWithFileName> <PathWithFileName>..\..\src\module.c</PathWithFileName>
<FilenameWithoutPath>module.c</FilenameWithoutPath> <FilenameWithoutPath>module.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -508,7 +508,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\object.c</PathWithFileName> <PathWithFileName>..\..\src\object.c</PathWithFileName>
<FilenameWithoutPath>object.c</FilenameWithoutPath> <FilenameWithoutPath>object.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -522,7 +522,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\rtm.c</PathWithFileName> <PathWithFileName>..\..\src\rtm.c</PathWithFileName>
<FilenameWithoutPath>rtm.c</FilenameWithoutPath> <FilenameWithoutPath>rtm.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -536,7 +536,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\scheduler.c</PathWithFileName> <PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
<FilenameWithoutPath>scheduler.c</FilenameWithoutPath> <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -550,7 +550,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\slab.c</PathWithFileName> <PathWithFileName>..\..\src\slab.c</PathWithFileName>
<FilenameWithoutPath>slab.c</FilenameWithoutPath> <FilenameWithoutPath>slab.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -564,7 +564,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\thread.c</PathWithFileName> <PathWithFileName>..\..\src\thread.c</PathWithFileName>
<FilenameWithoutPath>thread.c</FilenameWithoutPath> <FilenameWithoutPath>thread.c</FilenameWithoutPath>
</File> </File>
<File> <File>
@ -578,7 +578,7 @@
<TopLine>0</TopLine> <TopLine>0</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\timer.c</PathWithFileName> <PathWithFileName>..\..\src\timer.c</PathWithFileName>
<FilenameWithoutPath>timer.c</FilenameWithoutPath> <FilenameWithoutPath>timer.c</FilenameWithoutPath>
</File> </File>
</Group> </Group>

50
bsp/fm3/mb9bf500r/project.uvproj → bsp/mb9bf500r/project.uvproj
View File

@ -346,7 +346,7 @@
<MiscControls></MiscControls> <MiscControls></MiscControls>
<Define></Define> <Define></Define>
<Undefine></Undefine> <Undefine></Undefine>
<IncludePath>..\CMSIS;.;..\..\..\libcpu\arm\fm3;..\..\..\include;..\..\..\components\rtgui\include</IncludePath> <IncludePath>CMSIS;.;..\..\include;..\..\components\rtgui\include</IncludePath>
</VariousControls> </VariousControls>
</Cads> </Cads>
<Aads> <Aads>
@ -439,12 +439,12 @@
<File> <File>
<FileName>context_rvds.S</FileName> <FileName>context_rvds.S</FileName>
<FileType>2</FileType> <FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath> <FilePath>..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
</File> </File>
<File> <File>
<FileName>cpuport.c</FileName> <FileName>cpuport.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath> <FilePath>..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath>
</File> </File>
</Files> </Files>
</Group> </Group>
@ -454,17 +454,17 @@
<File> <File>
<FileName>core_cm3.c</FileName> <FileName>core_cm3.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\CMSIS\core_cm3.c</FilePath> <FilePath>.\CMSIS\core_cm3.c</FilePath>
</File>
<File>
<FileName>system_mb9bf50x.c</FileName>
<FileType>1</FileType>
<FilePath>..\CMSIS\system_mb9bf50x.c</FilePath>
</File> </File>
<File> <File>
<FileName>start_rvds.S</FileName> <FileName>start_rvds.S</FileName>
<FileType>2</FileType> <FileType>2</FileType>
<FilePath>..\CMSIS\start_rvds.S</FilePath> <FilePath>.\CMSIS\start_rvds.S</FilePath>
</File>
<File>
<FileName>system_mb9bf50x.c</FileName>
<FileType>1</FileType>
<FilePath>.\CMSIS\system_mb9bf50x.c</FilePath>
</File> </File>
</Files> </Files>
</Group> </Group>
@ -474,77 +474,77 @@
<File> <File>
<FileName>clock.c</FileName> <FileName>clock.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath> <FilePath>..\..\src\clock.c</FilePath>
</File> </File>
<File> <File>
<FileName>device.c</FileName> <FileName>device.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\device.c</FilePath> <FilePath>..\..\src\device.c</FilePath>
</File> </File>
<File> <File>
<FileName>idle.c</FileName> <FileName>idle.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath> <FilePath>..\..\src\idle.c</FilePath>
</File> </File>
<File> <File>
<FileName>ipc.c</FileName> <FileName>ipc.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath> <FilePath>..\..\src\ipc.c</FilePath>
</File> </File>
<File> <File>
<FileName>irq.c</FileName> <FileName>irq.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath> <FilePath>..\..\src\irq.c</FilePath>
</File> </File>
<File> <File>
<FileName>kservice.c</FileName> <FileName>kservice.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath> <FilePath>..\..\src\kservice.c</FilePath>
</File> </File>
<File> <File>
<FileName>mem.c</FileName> <FileName>mem.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath> <FilePath>..\..\src\mem.c</FilePath>
</File> </File>
<File> <File>
<FileName>mempool.c</FileName> <FileName>mempool.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath> <FilePath>..\..\src\mempool.c</FilePath>
</File> </File>
<File> <File>
<FileName>module.c</FileName> <FileName>module.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\module.c</FilePath> <FilePath>..\..\src\module.c</FilePath>
</File> </File>
<File> <File>
<FileName>object.c</FileName> <FileName>object.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath> <FilePath>..\..\src\object.c</FilePath>
</File> </File>
<File> <File>
<FileName>rtm.c</FileName> <FileName>rtm.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\rtm.c</FilePath> <FilePath>..\..\src\rtm.c</FilePath>
</File> </File>
<File> <File>
<FileName>scheduler.c</FileName> <FileName>scheduler.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath> <FilePath>..\..\src\scheduler.c</FilePath>
</File> </File>
<File> <File>
<FileName>slab.c</FileName> <FileName>slab.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\slab.c</FilePath> <FilePath>..\..\src\slab.c</FilePath>
</File> </File>
<File> <File>
<FileName>thread.c</FileName> <FileName>thread.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath> <FilePath>..\..\src\thread.c</FilePath>
</File> </File>
<File> <File>
<FileName>timer.c</FileName> <FileName>timer.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath> <FilePath>..\..\src\timer.c</FilePath>
</File> </File>
</Files> </Files>
</Group> </Group>

2
bsp/fm3/mb9bf500r/rtconfig.h → bsp/mb9bf500r/rtconfig.h
View File

@ -3,7 +3,7 @@
#define __RTTHREAD_CFG_H__ #define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/ /* RT_NAME_MAX*/
#define RT_NAME_MAX 4 #define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/ /* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4 #define RT_ALIGN_SIZE 4

4
bsp/fm3/mb9bf500r/rtconfig.py → bsp/mb9bf500r/rtconfig.py
View File

@ -1,7 +1,7 @@
# toolchains options # toolchains options
ARCH='arm' ARCH='arm'
CPU='cortex-m3' CPU='cortex-m3'
CROSS_TOOL='iar' CROSS_TOOL='gcc'
# cross_tool provides the cross compiler # cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
@ -14,7 +14,7 @@ elif CROSS_TOOL == 'keil':
EXEC_PATH = 'C:/Keil' EXEC_PATH = 'C:/Keil'
elif CROSS_TOOL == 'iar': elif CROSS_TOOL == 'iar':
PLATFORM = 'iar' PLATFORM = 'iar'
IAR_PATH = 'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
BUILD = 'debug' BUILD = 'debug'

0
bsp/fm3/mb9bf500r/startup.c → bsp/mb9bf500r/startup.c
View File

0
bsp/fm3/CMSIS/SConscript → bsp/mb9bf506r/CMSIS/SConscript
View File

359
bsp/mb9bf506r/CMSIS/core_cm3.c Normal file
View File

@ -0,0 +1,359 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.40
* @date 18. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V1.40
* @date 16. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H__
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/**
* @brief Enable IRQ Interrupts
*
* Enables IRQ interrupts by clearing the I-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
* @brief Disable IRQ Interrupts
*
* Disables IRQ interrupts by setting the I-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_CONTROL(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_IPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_APSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_xPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PSP(uint32_t topOfProcStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_MSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_MSP(uint32_t topOfMainStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_MSP(uint32_t mainStackPointer)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = mainStackPointer;
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PRIMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PRIMASK(uint32_t priMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/**
* @brief Enable FIQ Interrupts
*
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
* @brief Disable FIQ Interrupts
*
* Disables FIQ interrupts by setting the F-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_BASEPRI(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_BASEPRI(uint32_t basePri);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_FAULTMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_FAULTMASK(uint32_t faultMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/**
* @brief Enable IRQ Interrupts
*
* Enables IRQ interrupts by clearing the I-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
/**
* @brief Disable IRQ Interrupts
*
* Disables IRQ interrupts by setting the I-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/**
* @brief Enable FIQ Interrupts
*
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
/**
* @brief Disable FIQ Interrupts
*
* Disables FIQ interrupts by setting the F-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
/* not yet implemented */
return(0);
#else
return(0);
#endif
}
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
/* not yet implemented */
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Enable IRQ Interrupts
*
* Enables IRQ interrupts by clearing the I-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
/**
* @brief Disable IRQ Interrupts
*
* Disables IRQ interrupts by setting the I-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
static __INLINE uint32_t __get_APSR(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) );
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result __ASM ("r0") = 0;
__ASM volatile ("MRS %0, psp\n"
"BX lr \n" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n"
"BX lr \n" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) );
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result __ASM ("r0") = 0;
__ASM volatile ("MRS %0, msp\n"
"BX lr \n" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n"
"BX lr \n" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/**
* @brief Enable FIQ Interrupts
*
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
/**
* @brief Disable FIQ Interrupts
*
* Disables FIQ interrupts by setting the F-bit in the CPSR.
* Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#if (__CORTEX_M == 0x04)
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result=0;
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("MSR control, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
#endif // __CORE_CMFUNC_H__

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V1.40
* @date 16. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/**
* @brief No Operation
*
* No Operation does nothing. This instruction can be used for code alignment
* purposes.
*/
#define __NOP __nop
/**
* @brief Wait For Interrupt
*
* Wait For Interrupt is a hint instruction that suspends execution until
* one of a number of events occurs.
*/
#define __WFI __wfi
/**
* @brief Wait For Event
*
* Wait For Event is a hint instruction that permits the processor to enter
* a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
* @brief Send Event
*
* Send Event is a hint instruction. It causes an event to be signaled
* to the CPU.
*/
#define __SEV __sev
/**
* @brief Instruction Synchronization Barrier
*
* Instruction Synchronization Barrier flushes the pipeline in the processor,
* so that all instructions following the ISB are fetched from cache or
* memory, after the instruction has been completed
*/
#define __ISB() __isb(0xF)
/**
* @brief Data Synchronization Barrier
*
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
* The DSB operation completes when all explicit memory accesses before this
* instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
* @brief Data Memory Barrier
*
* DMB ensures the apparent order of the explicit memory operations before
* and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
* @brief Reverse byte order (32 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
#define __REV __rev
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint16_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int16_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
#define __RBIT __rbit
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/**
* @brief No Operation
*
* No Operation does nothing. This instruction can be used for code alignment
* purposes.
*/
#define __NOP __no_operation
/**
* @brief Wait For Interrupt
*
* Wait For Interrupt is a hint instruction that suspends execution until
* one of a number of events occurs.
*/
static __INLINE void __WFI() { __ASM ("wfi"); }
/**
* @brief Wait For Event
*
* Wait For Event is a hint instruction that permits the processor to enter
* a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE() { __ASM ("wfe"); }
/**
* @brief Send Event
*
* Send Event is a hint instruction. It causes an event to be signaled
* to the CPU.
*/
static __INLINE void __SEV() { __ASM ("sev"); }
/**
* @brief Instruction Synchronization Barrier
*
* Instruction Synchronization Barrier flushes the pipeline in the processor,
* so that all instructions following the ISB are fetched from cache or
* memory, after the instruction has been completed
*/
/* intrinsic void __ISB(void) (see intrinsics.h */
/**
* @brief Data Synchronization Barrier
*
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
* The DSB operation completes when all explicit memory accesses before this
* instruction complete.
*/
/* intrinsic void __DSB(void) (see intrinsics.h */
/**
* @brief Data Memory Barrier
*
* DMB ensures the apparent order of the explicit memory operations before
* and after the instruction, without ensuring their completion.
*/
/* intrinsic void __DMB(void) (see intrinsics.h */
/**
* @brief Reverse byte order (32 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
static uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
static uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
static uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */
static uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
static uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
static uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */
static uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
static __INLINE void __CLREX() { __ASM ("clrex"); }
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief No Operation
*
* No Operation does nothing. This instruction can be used for code alignment
* purposes.
*/
static __INLINE void __NOP() { __ASM volatile ("nop"); }
/**
* @brief Wait For Interrupt
*
* Wait For Interrupt is a hint instruction that suspends execution until
* one of a number of events occurs.
*/
static __INLINE void __WFI() { __ASM volatile ("wfi"); }
/**
* @brief Wait For Event
*
* Wait For Event is a hint instruction that permits the processor to enter
* a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE() { __ASM volatile ("wfe"); }
/**
* @brief Send Event
*
* Send Event is a hint instruction. It causes an event to be signaled
* to the CPU.
*/
static __INLINE void __SEV() { __ASM volatile ("sev"); }
/**
* @brief Instruction Synchronization Barrier
*
* Instruction Synchronization Barrier flushes the pipeline in the processor,
* so that all instructions following the ISB are fetched from cache or
* memory, after the instruction has been completed
*/
static __INLINE void __ISB() { __ASM volatile ("isb"); }
/**
* @brief Data Synchronization Barrier
*
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
* The DSB operation completes when all explicit memory accesses before this
* instruction complete.
*/
static __INLINE void __DSB() { __ASM volatile ("dsb"); }
/**
* @brief Data Memory Barrier
*
* DMB ensures the apparent order of the explicit memory operations before
* and after the instruction, without ensuring their completion.
*/
static __INLINE void __DMB() { __ASM volatile ("dmb"); }
/**
* @brief Reverse byte order (32 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
static __INLINE uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
static __INLINE int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
static __INLINE uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
static __INLINE uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
static __INLINE uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
#endif // __CORE_CMINSTR_H__

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/*
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-07-01 lgnq first version
*/
.section .bss.init
.equ Stack_Size, 0x00000200
.space Stack_Size
Initial_spTop:
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
// .equ Initial_spTop, 0x20000200
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* restore original stack pointer */
LDR r0, =Initial_spTop
MSR msp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word Initial_spTop
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word CSV_IRQHandler
.word SWDT_IRQHandler
.word LVD_IRQHandler
.word WFG_IRQHandler
.word EXINT0_7_IRQHandler
.word EXINT8_15_IRQHandler
.word DTIM_QDU_IRQHandler
.word MFS0RX_IRQHandler
.word MFS0TX_IRQHandler
.word MFS1RX_IRQHandler
.word MFS1TX_IRQHandler
.word MFS2RX_IRQHandler
.word MFS2TX_IRQHandler
.word MFS3RX_IRQHandler
.word MFS3TX_IRQHandler
.word MFS4RX_IRQHandler
.word MFS4TX_IRQHandler
.word MFS5RX_IRQHandler
.word MFS5TX_IRQHandler
.word MFS6RX_IRQHandler
.word MFS6TX_IRQHandler
.word MFS7RX_IRQHandler
.word MFS7TX_IRQHandler
.word PPG_IRQHandler
.word OSC_PLL_WC_IRQHandler
.word ADC0_IRQHandler
.word ADC1_IRQHandler
.word ADC2_IRQHandler
.word FRTIM_IRQHandler
.word INCAP_IRQHandler
.word OUTCOMP_IRQHandler
.word BTIM_IRQHandler
.word CAN0_IRQHandler
.word CAN1_IRQHandler
.word USBF_IRQHandler
.word USBF_USBH_IRQHandler
.word RESERVED_1_IRQHandler
.word RESERVED_2_IRQHandler
.word DMAC0_IRQHandler
.word DMAC1_IRQHandler
.word DMAC2_IRQHandler
.word DMAC3_IRQHandler
.word DMAC4_IRQHandler
.word DMAC5_IRQHandler
.word DMAC6_IRQHandler
.word DMAC7_IRQHandler
.word RESERVED_3_IRQHandler
.word RESERVED_4_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak CSV_IRQHandler
.thumb_set CSV_IRQHandler,Default_Handler
.weak SWDT_IRQHandler
.thumb_set SWDT_IRQHandler,Default_Handler
.weak LVD_IRQHandler
.thumb_set LVD_IRQHandler,Default_Handler
.weak WFG_IRQHandler
.thumb_set WFG_IRQHandler,Default_Handler
.weak EXINT0_7_IRQHandler
.thumb_set EXINT0_7_IRQHandler,Default_Handler
.weak EXINT8_15_IRQHandler
.thumb_set EXINT8_15_IRQHandler,Default_Handler
.weak DTIM_QDU_IRQHandler
.thumb_set DTIM_QDU_IRQHandler,Default_Handler
.weak MFS0RX_IRQHandler
.thumb_set MFS0RX_IRQHandler,Default_Handler
.weak MFS0TX_IRQHandler
.thumb_set MFS0TX_IRQHandler,Default_Handler
.weak MFS1RX_IRQHandler
.thumb_set MFS1RX_IRQHandler,Default_Handler
.weak MFS1TX_IRQHandler
.thumb_set MFS1TX_IRQHandler,Default_Handler
.weak MFS2RX_IRQHandler
.thumb_set MFS2RX_IRQHandler,Default_Handler
.weak MFS2TX_IRQHandler
.thumb_set MFS2TX_IRQHandler,Default_Handler
.weak MFS3RX_IRQHandler
.thumb_set MFS3RX_IRQHandler,Default_Handler
.weak MFS3TX_IRQHandler
.thumb_set MFS3TX_IRQHandler,Default_Handler
.weak MFS4RX_IRQHandler
.thumb_set MFS4RX_IRQHandler,Default_Handler
.weak MFS4TX_IRQHandler
.thumb_set MFS4TX_IRQHandler,Default_Handler
.weak MFS5RX_IRQHandler
.thumb_set MFS5RX_IRQHandler,Default_Handler
.weak MFS5TX_IRQHandler
.thumb_set MFS5TX_IRQHandler,Default_Handler
.weak MFS6RX_IRQHandler
.thumb_set MFS6RX_IRQHandler,Default_Handler
.weak MFS6TX_IRQHandler
.thumb_set MFS6TX_IRQHandler,Default_Handler
.weak MFS7RX_IRQHandler
.thumb_set MFS7RX_IRQHandler,Default_Handler
.weak MFS7TX_IRQHandler
.thumb_set MFS7TX_IRQHandler,Default_Handler
.weak PPG_IRQHandler
.thumb_set PPG_IRQHandler,Default_Handler
.weak OSC_PLL_WC_IRQHandler
.thumb_set OSC_PLL_WC_IRQHandler,Default_Handler
.weak ADC0_IRQHandler
.thumb_set ADC0_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak ADC2_IRQHandler
.thumb_set ADC2_IRQHandler,Default_Handler
.weak FRTIM_IRQHandler
.thumb_set FRTIM_IRQHandler,Default_Handler
.weak INCAP_IRQHandler
.thumb_set INCAP_IRQHandler,Default_Handler
.weak OUTCOMP_IRQHandler
.thumb_set OUTCOMP_IRQHandler,Default_Handler
.weak BTIM_IRQHandler
.thumb_set BTIM_IRQHandler,Default_Handler
.weak CAN0_IRQHandler
.thumb_set CAN0_IRQHandler,Default_Handler
.weak CAN1_IRQHandler
.thumb_set CAN1_IRQHandler,Default_Handler
.weak USBF_IRQHandler
.thumb_set USBF_IRQHandler,Default_Handler
.weak USBF_USBH_IRQHandler
.thumb_set USBF_USBH_IRQHandler,Default_Handler
.weak RESERVED_1_IRQHandler
.thumb_set RESERVED_1_IRQHandler,Default_Handler
.weak RESERVED_2_IRQHandler
.thumb_set RESERVED_2_IRQHandler,Default_Handler
.weak DMAC0_IRQHandler
.thumb_set DMAC0_IRQHandler,Default_Handler
.weak DMAC1_IRQHandler
.thumb_set DMAC1_IRQHandler,Default_Handler
.weak DMAC2_IRQHandler
.thumb_set DMAC2_IRQHandler,Default_Handler
.weak DMAC3_IRQHandler
.thumb_set DMAC3_IRQHandler,Default_Handler
.weak DMAC4_IRQHandler
.thumb_set DMAC4_IRQHandler,Default_Handler
.weak DMAC5_IRQHandler
.thumb_set DMAC5_IRQHandler,Default_Handler
.weak DMAC6_IRQHandler
.thumb_set DMAC6_IRQHandler,Default_Handler
.weak DMAC7_IRQHandler
.thumb_set DMAC7_IRQHandler,Default_Handler
.weak RESERVED_3_IRQHandler
.thumb_set RESERVED_3_IRQHandler,Default_Handler
.weak RESERVED_4_IRQHandler
.thumb_set RESERVED_4_IRQHandler,Default_Handler

363
bsp/mb9bf506r/CMSIS/start_iar.S Normal file
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@ -0,0 +1,363 @@
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs
; */
#include "rtconfig.h"
MODULE ?cstartup
;; ICODE is the same segment as cstartup. By placing __low_level_init
;; in the same segment, we make sure it can be reached with BL. */
SECTION CSTACK:DATA:NOROOT(3)
SECTION .icode:CODE:NOROOT(2)
#ifdef RT_USING_UART2
IMPORT MFS2RX_IRQHandler
#endif
PUBLIC __low_level_init
PUBWEAK SystemInit_ExtMemCtl
SECTION .text:CODE:REORDER(2)
THUMB
SystemInit_ExtMemCtl
BX LR
__low_level_init:
;; Initialize hardware.
LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
MOV R11, LR
BLX R0
LDR R1, =sfe(CSTACK) ; restore original stack pointer
MSR MSP, R1
MOV R0,#1
;; Return with BX to be independent of mode of caller
BX R11
;; Forward declaration of sections.
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD __iar_program_start
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD CSV_IRQHandler ; Clock Super Visor
DCD SWDT_IRQHandler ; Software Watchdog Timer
DCD LVD_IRQHandler ; Low Voltage Detector
DCD WFG_IRQHandler ; Wave Form Generator
DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7
DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15
DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1
#ifdef RT_USING_UART2
DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2
#else
DCD NULL_IRQHandler ; MultiFunction Serial ch.2
#endif
DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7
DCD PPG_IRQHandler ; PPG
DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; ADC0
DCD ADC1_IRQHandler ; ADC1
DCD ADC2_IRQHandler ; ADC2
DCD FRTIM_IRQHandler ; Free-run Timer
DCD INCAP_IRQHandler ; Input Capture
DCD OUTCOMP_IRQHandler ; Output Compare
DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; CAN ch.0
DCD CAN1_IRQHandler ; CAN ch.1
DCD USBF_IRQHandler ; USB Function
DCD USBF_USBH_IRQHandler ; USB Function / USB HOST
DCD RESERVED_1_IRQHandler ; Reserved_1
DCD RESERVED_2_IRQHandler ; Reserved_2
DCD DMAC0_IRQHandler ; DMAC ch.0
DCD DMAC1_IRQHandler ; DMAC ch.1
DCD DMAC2_IRQHandler ; DMAC ch.2
DCD DMAC3_IRQHandler ; DMAC ch.3
DCD DMAC4_IRQHandler ; DMAC ch.4
DCD DMAC5_IRQHandler ; DMAC ch.5
DCD DMAC6_IRQHandler ; DMAC ch.6
DCD DMAC7_IRQHandler ; DMAC ch.7
DCD RESERVED_3_IRQHandler ; Reserved_3
DCD RESERVED_4_IRQHandler ; Reserved_4
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK CSV_IRQHandler
SECTION .text:CODE:REORDER(1)
CSV_IRQHandler
B CSV_IRQHandler
PUBWEAK SWDT_IRQHandler
SECTION .text:CODE:REORDER(1)
SWDT_IRQHandler
B SWDT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK WFG_IRQHandler
SECTION .text:CODE:REORDER(1)
WFG_IRQHandler
B WFG_IRQHandler
PUBWEAK EXINT0_7_IRQHandler
SECTION .text:CODE:REORDER(1)
EXINT0_7_IRQHandler
B EXINT0_7_IRQHandler
PUBWEAK EXINT8_15_IRQHandler
SECTION .text:CODE:REORDER(1)
EXINT8_15_IRQHandler
B EXINT8_15_IRQHandler
PUBWEAK DTIM_QDU_IRQHandler
SECTION .text:CODE:REORDER(1)
DTIM_QDU_IRQHandler
B DTIM_QDU_IRQHandler
PUBWEAK MFS0RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0RX_IRQHandler
B MFS0RX_IRQHandler
PUBWEAK MFS0TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0TX_IRQHandler
B MFS0TX_IRQHandler
PUBWEAK MFS1RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1RX_IRQHandler
B MFS1RX_IRQHandler
PUBWEAK MFS1TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1TX_IRQHandler
B MFS1TX_IRQHandler
PUBWEAK NULL_IRQHandler
SECTION .text:CODE:REORDER(1)
NULL_IRQHandler
B NULL_IRQHandler
PUBWEAK MFS2TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2TX_IRQHandler
B MFS2TX_IRQHandler
PUBWEAK MFS3RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3RX_IRQHandler
B MFS3RX_IRQHandler
PUBWEAK MFS3TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3TX_IRQHandler
B MFS3TX_IRQHandler
PUBWEAK MFS4RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4RX_IRQHandler
B MFS4RX_IRQHandler
PUBWEAK MFS4TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4TX_IRQHandler
B MFS4TX_IRQHandler
PUBWEAK MFS5RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5RX_IRQHandler
B MFS5RX_IRQHandler
PUBWEAK MFS5TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5TX_IRQHandler
B MFS5TX_IRQHandler
PUBWEAK MFS6RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6RX_IRQHandler
B MFS6RX_IRQHandler
PUBWEAK MFS6TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6TX_IRQHandler
B MFS6TX_IRQHandler
PUBWEAK MFS7RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7RX_IRQHandler
B MFS7RX_IRQHandler
PUBWEAK MFS7TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7TX_IRQHandler
B MFS7TX_IRQHandler
PUBWEAK PPG_IRQHandler
SECTION .text:CODE:REORDER(1)
PPG_IRQHandler
B PPG_IRQHandler
PUBWEAK OSC_PLL_WC_IRQHandler
SECTION .text:CODE:REORDER(1)
OSC_PLL_WC_IRQHandler
B OSC_PLL_WC_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK FRTIM_IRQHandler
SECTION .text:CODE:REORDER(1)
FRTIM_IRQHandler
B FRTIM_IRQHandler
PUBWEAK INCAP_IRQHandler
SECTION .text:CODE:REORDER(1)
INCAP_IRQHandler
B INCAP_IRQHandler
PUBWEAK OUTCOMP_IRQHandler
SECTION .text:CODE:REORDER(1)
OUTCOMP_IRQHandler
B OUTCOMP_IRQHandler
PUBWEAK BTIM_IRQHandler
SECTION .text:CODE:REORDER(1)
BTIM_IRQHandler
B BTIM_IRQHandler
PUBWEAK CAN0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN0_IRQHandler
B CAN0_IRQHandler
PUBWEAK CAN1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_IRQHandler
B CAN1_IRQHandler
PUBWEAK USBF_IRQHandler
SECTION .text:CODE:REORDER(1)
USBF_IRQHandler
B USBF_IRQHandler
PUBWEAK USBF_USBH_IRQHandler
SECTION .text:CODE:REORDER(1)
USBF_USBH_IRQHandler
B USBF_USBH_IRQHandler
PUBWEAK RESERVED_1_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_1_IRQHandler
B RESERVED_1_IRQHandler
PUBWEAK RESERVED_2_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_2_IRQHandler
B RESERVED_2_IRQHandler
PUBWEAK DMAC0_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC0_IRQHandler
B DMAC0_IRQHandler
PUBWEAK DMAC1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC1_IRQHandler
B DMAC1_IRQHandler
PUBWEAK DMAC2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC2_IRQHandler
B DMAC2_IRQHandler
PUBWEAK DMAC3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC3_IRQHandler
B DMAC3_IRQHandler
PUBWEAK DMAC4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC4_IRQHandler
B DMAC4_IRQHandler
PUBWEAK DMAC5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC5_IRQHandler
B DMAC5_IRQHandler
PUBWEAK DMAC6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC6_IRQHandler
B DMAC6_IRQHandler
PUBWEAK DMAC7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC7_IRQHandler
B DMAC7_IRQHandler
PUBWEAK RESERVED_3_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_3_IRQHandler
B RESERVED_3_IRQHandler
PUBWEAK RESERVED_4_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_4_IRQHandler
B RESERVED_4_IRQHandler
END

291
bsp/mb9bf506r/CMSIS/start_rvds.S Normal file
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@ -0,0 +1,291 @@
; /*
; * File : start_rvds.s
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2011-02-23 Bernard first implementation
; */
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0.
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; 32: CAN ch.0
DCD CAN1_IRQHandler ; 33: CAN ch.1
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R1, = __initial_sp ; restore original stack pointer
MSR MSP, R1
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT CSV_Handler [WEAK]
EXPORT SWDT_Handler [WEAK]
EXPORT LVD_Handler [WEAK]
EXPORT MFT_WG_IRQHandler [WEAK]
EXPORT INT0_7_Handler [WEAK]
EXPORT INT8_15_Handler [WEAK]
EXPORT DT_Handler [WEAK]
EXPORT MFS0RX_IRQHandler [WEAK]
EXPORT MFS0TX_IRQHandler [WEAK]
EXPORT MFS1RX_IRQHandler [WEAK]
EXPORT MFS1TX_IRQHandler [WEAK]
EXPORT MFS2RX_IRQHandler [WEAK]
EXPORT MFS2TX_IRQHandler [WEAK]
EXPORT MFS3RX_IRQHandler [WEAK]
EXPORT MFS3TX_IRQHandler [WEAK]
EXPORT MFS4RX_IRQHandler [WEAK]
EXPORT MFS4TX_IRQHandler [WEAK]
EXPORT MFS5RX_IRQHandler [WEAK]
EXPORT MFS5TX_IRQHandler [WEAK]
EXPORT MFS6RX_IRQHandler [WEAK]
EXPORT MFS6TX_IRQHandler [WEAK]
EXPORT MFS7RX_IRQHandler [WEAK]
EXPORT MFS7TX_IRQHandler [WEAK]
EXPORT PPG_Handler [WEAK]
EXPORT TIM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT MFT_FRT_IRQHandler [WEAK]
EXPORT MFT_IPC_IRQHandler [WEAK]
EXPORT MFT_OPC_IRQHandler [WEAK]
EXPORT BT_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT USBF_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT DMAC0_Handler [WEAK]
EXPORT DMAC1_Handler [WEAK]
EXPORT DMAC2_Handler [WEAK]
EXPORT DMAC3_Handler [WEAK]
EXPORT DMAC4_Handler [WEAK]
EXPORT DMAC5_Handler [WEAK]
EXPORT DMAC6_Handler [WEAK]
EXPORT DMAC7_Handler [WEAK]
EXPORT DummyHandler [WEAK]
CSV_Handler
SWDT_Handler
LVD_Handler
MFT_WG_IRQHandler
INT0_7_Handler
INT8_15_Handler
DT_Handler
MFS0RX_IRQHandler
MFS0TX_IRQHandler
MFS1RX_IRQHandler
MFS1TX_IRQHandler
MFS2RX_IRQHandler
MFS2TX_IRQHandler
MFS3RX_IRQHandler
MFS3TX_IRQHandler
MFS4RX_IRQHandler
MFS4TX_IRQHandler
MFS5RX_IRQHandler
MFS5TX_IRQHandler
MFS6RX_IRQHandler
MFS6TX_IRQHandler
MFS7RX_IRQHandler
MFS7TX_IRQHandler
PPG_Handler
TIM_IRQHandler
ADC0_IRQHandler
ADC1_IRQHandler
ADC2_IRQHandler
MFT_FRT_IRQHandler
MFT_IPC_IRQHandler
MFT_OPC_IRQHandler
BT_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
USBF_Handler
USB_Handler
DMAC0_Handler
DMAC1_Handler
DMAC2_Handler
DMAC3_Handler
DMAC4_Handler
DMAC5_Handler
DMAC6_Handler
DMAC7_Handler
DummyHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

111
bsp/mb9bf506r/CMSIS/system_mb9bf50x.c Normal file
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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user’s obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intention and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.4) */
/************************************************************************/
#include "mb9bf506r.h"
/*
* 80MHz : Master Clock
*/
const uint32_t SystemFrequency = 80000000UL;
uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */
uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */
uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */
uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */
uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */
/*
* Prototype of internal function
*/
static void ClockInit(void);
static void HwwdtDisable(void);
/*
* Setup the microcontroller system
*/
void SystemInit (void)
{
HwwdtDisable(); /* Disable Hardware Watchdog */
ClockInit(); /* Initialize Clock */
}
/*
* Initialize Clock
*/
static void ClockInit(void)
{
/*set Main clock stabilization
wait time to 2ms*/
FM3_CRG->CSW_TMR = 0x79;
/*Enable Main Oscilator*/
FM3_CRG->SCM_CTL |= 1<<1;
/*Wait stabilization end*/
while(!(FM3_CRG->SCM_STR & 0x02));
/* sub CLK enable */
//FM3_CRG->SCM_CTL |= 0x08;
//while(!(FM3_CRG->SCM_STR & 0x08));
/*Set PLL stabilization
wait time to 512uS*/
FM3_CRG->PSW_TMR |= 2;
/*Set PLL to 80MHz*/
FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/
FM3_CRG->PLL_CTL2 = 19; /*N = 20*/
/*Enable PLL*/
FM3_CRG->SCM_CTL |= 0x10;
/*Set bus prescalers*/
FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/
FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/
FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/
FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/
/*Wait PLL stabilizatoin end*/
while(!(FM3_CRG->SCM_STR & 0x10));
/*Select PLL for main clock*/
FM3_CRG->SCM_CTL |= 2<<5;
/*Wait PLL to be connected*/
while((FM3_CRG->SCM_STR & 0xe0) != 0x40);
}
/*
* Stop HW Watchdog Timer
*/
static void HwwdtDisable(void)
{
/* UnLock (except WDG_CTL) */
FM3_HWWDT->WDG_LCK = 0x1ACCE551;
/* UnLock (WDG_CTL) */
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
/* Disable WDG */
FM3_HWWDT->WDG_CTL = 0x00;
}

71
bsp/mb9bf506r/CMSIS/system_mb9bf50x.h Normal file
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@ -0,0 +1,71 @@
/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
#ifndef _SYSTEM_MB9BF50X_H_
#define _SYSTEM_MB9BF50X_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_MB9BF50X_H */

0
bsp/fm3/mb9bf506r/SConscript → bsp/mb9bf506r/SConscript
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4
bsp/fm3/mb9bf506r/SConstruct → bsp/mb9bf506r/SConstruct
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@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'): if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT') RTT_ROOT = os.getenv('RTT_ROOT')
else: else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import * from building import *
@ -30,7 +30,7 @@ Export('rtconfig')
# prepare building environment # prepare building environment
objs = PrepareBuilding(env, RTT_ROOT) objs = PrepareBuilding(env, RTT_ROOT)
objs = objs + SConscript('../CMSIS/SConscript', variant_dir='build/bsp/Libraries', duplicate=0) objs = objs + SConscript('CMSIS/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
# build program # build program
env.Program(TARGET, objs) env.Program(TARGET, objs)

0
bsp/fm3/mb9bf506r/application.c → bsp/mb9bf506r/application.c
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128
bsp/fm3/mb9bf506r/board.c → bsp/mb9bf506r/board.c
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@ -1,64 +1,64 @@
/* /*
* File : board.c * File : board.c
* This file is part of RT-Thread RTOS * This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE * http://www.rt-thread.org/license/LICENSE
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2011-02-24 Bernard first implementation * 2011-02-24 Bernard first implementation
*/ */
#include <rthw.h> #include <rthw.h>
#include <rtthread.h> #include <rtthread.h>
#include "board.h" #include "board.h"
#include "mb9bf506r.h" #include "mb9bf506r.h"
#include "serial.h" #include "serial.h"
#include "nand.h" #include "nand.h"
extern const uint32_t SystemFrequency; extern const uint32_t SystemFrequency;
/** /**
* @addtogroup FM3 * @addtogroup FM3
*/ */
/*@{*/ /*@{*/
/** /**
* This is the timer interrupt service routine. * This is the timer interrupt service routine.
* *
*/ */
void SysTick_Handler(void) void SysTick_Handler(void)
{ {
/* enter interrupt */ /* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
rt_tick_increase(); rt_tick_increase();
/* leave interrupt */ /* leave interrupt */
rt_interrupt_leave(); rt_interrupt_leave();
} }
/** /**
* This function will initial FM3 Easy Kit board. * This function will initial FM3 Easy Kit board.
*/ */
void rt_hw_board_init() void rt_hw_board_init(void)
{ {
/* init systick */ /* init systick */
SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND); SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND);
/* initialize UART device */ /* initialize UART device */
rt_hw_serial_init(); rt_hw_serial_init();
/* set console as UART device */ /* set console as UART device */
rt_console_set_device("uart2"); rt_console_set_device("uart2");
/* initialize nand flash device */ /* initialize nand flash device */
rt_hw_nand_init(); rt_hw_nand_init();
} }
/*@}*/ /*@}*/

0
bsp/fm3/mb9bf506r/board.h → bsp/mb9bf506r/board.h
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0
bsp/fm3/mb9bf506r/console.c → bsp/mb9bf506r/console.c
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89
bsp/fm3/mb9bf506r/fm3_easy_kit.ewp → bsp/mb9bf506r/fm3_easy_kit.ewp
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@ -286,11 +286,11 @@
<option> <option>
<name>CCIncludePath2</name> <name>CCIncludePath2</name>
<state>$PROJ_DIR$\</state> <state>$PROJ_DIR$\</state>
<state>$PROJ_DIR$\..\CMSIS</state> <state>$PROJ_DIR$\CMSIS</state>
<state>$PROJ_DIR$\..\..\..\include</state> <state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\..\..\..\components\finsh</state> <state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\..\components\dfs\include</state> <state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat</state> <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
</option> </option>
<option> <option>
<name>CCStdIncCheck</name> <name>CCStdIncCheck</name>
@ -1742,133 +1742,130 @@
<group> <group>
<name>CMSIS</name> <name>CMSIS</name>
<file> <file>
<name>$PROJ_DIR$\..\CMSIS\core_cm3.c</name> <name>$PROJ_DIR$\CMSIS\start_iar.S</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\CMSIS\start_iar.S</name> <name>$PROJ_DIR$\CMSIS\system_mb9bf50x.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\CMSIS\system_mb9bf50x.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>Filesystem</name> <name>Filesystem</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs.c</name> <name>$PROJ_DIR$\..\..\components\dfs\src\dfs.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name> <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c</name> <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_file.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c</name> <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c</name> <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c</name> <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>Finsh</name> <name>Finsh</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name> <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_error.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_init.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_node.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_token.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_var.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c</name> <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name> <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\components\finsh\symbol.c</name> <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>FM3</name> <name>FM3</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\context_iar.S</name> <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c</name> <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
</file> </file>
</group> </group>
<group> <group>
<name>Kernel</name> <name>Kernel</name>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\clock.c</name> <name>$PROJ_DIR$\..\..\src\clock.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\device.c</name> <name>$PROJ_DIR$\..\..\src\device.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\idle.c</name> <name>$PROJ_DIR$\..\..\src\idle.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\ipc.c</name> <name>$PROJ_DIR$\..\..\src\ipc.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\irq.c</name> <name>$PROJ_DIR$\..\..\src\irq.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\kservice.c</name> <name>$PROJ_DIR$\..\..\src\kservice.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\mem.c</name> <name>$PROJ_DIR$\..\..\src\mem.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\mempool.c</name> <name>$PROJ_DIR$\..\..\src\mempool.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\module.c</name> <name>$PROJ_DIR$\..\..\src\module.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\object.c</name> <name>$PROJ_DIR$\..\..\src\object.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\rtm.c</name> <name>$PROJ_DIR$\..\..\src\rtm.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\scheduler.c</name> <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\slab.c</name> <name>$PROJ_DIR$\..\..\src\slab.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\thread.c</name> <name>$PROJ_DIR$\..\..\src\thread.c</name>
</file> </file>
<file> <file>
<name>$PROJ_DIR$\..\..\..\src\timer.c</name> <name>$PROJ_DIR$\..\..\src\timer.c</name>
</file> </file>
</group> </group>
<group> <group>

0
bsp/fm3/mb9bf506r/fm3_easy_kit.eww → bsp/mb9bf506r/fm3_easy_kit.eww
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0
bsp/fm3/mb9bf506r/fm3_rom.ld → bsp/mb9bf506r/fm3_rom.ld
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0
bsp/fm3/mb9bf506r/led.c → bsp/mb9bf506r/led.c
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0
bsp/fm3/mb9bf506r/led.h → bsp/mb9bf506r/led.h
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0
bsp/fm3/mb9bf506r/mb9bf506.icf → bsp/mb9bf506r/mb9bf506.icf
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0
bsp/fm3/mb9bf506r/nand.c → bsp/mb9bf506r/nand.c
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0
bsp/fm3/mb9bf506r/nand.h → bsp/mb9bf506r/nand.h
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4
bsp/fm3/mb9bf506r/rtconfig.h → bsp/mb9bf506r/rtconfig.h
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@ -3,10 +3,10 @@
#define __RTTHREAD_CFG_H__ #define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/ /* RT_NAME_MAX*/
#define RT_NAME_MAX 8 #define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/ /* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 8 #define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */ /* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32 #define RT_THREAD_PRIORITY_MAX 32

4
bsp/fm3/mb9bf506r/rtconfig.py → bsp/mb9bf506r/rtconfig.py
View File

@ -8,13 +8,13 @@ CROSS_TOOL='gcc'
if CROSS_TOOL == 'gcc': if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc' PLATFORM = 'gcc'
EXEC_PATH = '/media/workspace/arm-2011.03/bin' EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
elif CROSS_TOOL == 'keil': elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc' PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil' EXEC_PATH = 'C:/Keil'
elif CROSS_TOOL == 'iar': elif CROSS_TOOL == 'iar':
PLATFORM = 'iar' PLATFORM = 'iar'
IAR_PATH = 'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
BUILD = 'debug' BUILD = 'debug'

0
bsp/fm3/mb9bf506r/serial.c → bsp/mb9bf506r/serial.c
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0
bsp/fm3/mb9bf506r/serial.h → bsp/mb9bf506r/serial.h
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0
bsp/fm3/mb9bf506r/startup.c → bsp/mb9bf506r/startup.c
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