From d023fb47bac22377c73805b74ad85ed3a6ff7aea Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 11:58:09 +0800 Subject: [PATCH 01/15] [bsp][stm32] add all series dma_config files --- .../HAL_Drivers/config/f0/dma_config.h | 42 +++ .../HAL_Drivers/config/f1/dma_config.h | 94 ++++++ .../HAL_Drivers/config/f4/dma_config.h | 267 ++++++++++++++++ .../HAL_Drivers/config/f7/dma_config.h | 285 ++++++++++++++++++ .../HAL_Drivers/config/l4/dma_config.h | 173 +++++++++++ 5 files changed, 861 insertions(+) create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h new file mode 100644 index 0000000000..a883c86fdc --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-01-05 zylx first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +/* dma1 channel1 */ + +/* dma1 channel1 */ + +/* dma1 channel2-3 DMA2 channel1-2 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) +#define USART1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define USART1_RX_DMA_INSTANCE DMA1_Channel3 +#define USART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn + +#endif +/* dma1 channel2-3 DMA2 channel1-2 */ + +/* dma1 channel4-7 DMA2 channel3-5 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) +#define USART2_DMA_RX_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler +#define USART2_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define USART2_RX_DMA_INSTANCE DMA1_Channel5 +#define USART2_RX_DMA_IRQ DMA1_Ch4_7_DMA2_Ch3_5_IRQn + +#endif +/* dma1 channel4-7 DMA2 channel3-5 */ + + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h new file mode 100644 index 0000000000..d073838d44 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-01-02 SummerGift first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +/* DMA1 channel1 */ +/* DMA1 channel2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) +#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define SPI1_RX_DMA_INSTANCE DMA1_Channel2 +#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn +#endif + +/* DMA1 channel3 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) +#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN +#define SPI1_TX_DMA_INSTANCE DMA1_Channel3 +#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn + +#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) +#define USART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler +#define USART3_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define USART3_RX_DMA_INSTANCE DMA1_Channel3 +#define USART3_RX_DMA_IRQ DMA1_Channel3_IRQn +#endif + +/* DMA1 channel4 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) +#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Channel4 +#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn +#endif + +/* DMA1 channel5 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) +#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Channel5 +#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn + +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) +#define USART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define USART1_RX_DMA_INSTANCE DMA1_Channel5 +#define USART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#endif + +/* DMA1 channel6 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) +#define USART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler +#define USART2_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define USART2_RX_DMA_INSTANCE DMA1_Channel6 +#define USART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#endif + + +/* DMA1 channel7 */ + +/* DMA2 channel1 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) +#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN +#define SPI3_RX_DMA_INSTANCE DMA2_Channel1 +#define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn +#endif + +/* DMA2 channel2 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) +#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN +#define SPI3_TX_DMA_INSTANCE DMA2_Channel2 +#define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn +/* DMA1 channel4 */ +#endif + +/* DMA2 channel3 */ +/* DMA2 channel4 */ +/* DMA2 channel5 */ + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h new file mode 100644 index 0000000000..e8cec06fa7 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-01-02 zylx first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +/* dma1 stream0 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) + +#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn + +#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL) +#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART5_RX_DMA_INSTANCE DMA1_Stream0 +#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn + +#endif +/* dma1 stream0 */ + +/* dma1 stream1 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) +#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler +#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART3_RX_DMA_INSTANCE DMA1_Stream1 +#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn + +#endif +/* dma1 stream1 */ + +/* dma1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) + +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn + +#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) +#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART4_RX_DMA_INSTANCE DMA1_Stream2 +#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn + +#endif +/* dma1 stream2 */ + +/* dma1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) + +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn + +#endif +/* dma1 stream3 */ + +/* dma1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) + +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn + +#endif +/* dma1 stream4 */ + +/* dma1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) + +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn + +#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) +#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream5 +#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn + +#endif +/* dma1 stream5 */ + +/* dma1 stream6 */ +/* dma1 stream6 */ + +/* dma1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) + +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn + +#endif +/* dma1 stream7 */ + +/* dma2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) + +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn + +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) + +#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn + +#endif +/* dma2 stream0 */ + +/* dma2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) + +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn + +#endif +/* dma2 stream1 */ + +/* dma2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) + +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn + +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) + +#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream2 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn + +#endif +/* dma2 stream2 */ + +/* dma2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) + +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn + +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) + +#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn + +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) + +#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn + +#endif +/* dma2 stream3 */ + +/* dma2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) + +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn + +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) + +#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn + +#endif +/* dma2 stream4 */ + +/* dma2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) + +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn + +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) + +#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream5 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn + +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) + +#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn + +#endif + +/* dma2 stream5 */ + +/* dma2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) + +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn + +#endif +/* dma2 stream6 */ + +/* dma2 stream7 */ +/* dma2 stream7 */ + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h new file mode 100644 index 0000000000..5ff276900b --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-01-02 zylx first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +/* dma1 stream0 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) + +#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn + +#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL) +#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART5_RX_DMA_INSTANCE DMA1_Stream0 +#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn + +#endif +/* dma1 stream0 */ + +/* dma1 stream1 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) +#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler +#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART3_RX_DMA_INSTANCE DMA1_Stream1 +#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn + +#endif +/* dma1 stream1 */ + +/* dma1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) + +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn + +#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) +#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART4_RX_DMA_INSTANCE DMA1_Stream2 +#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn + +#endif +/* dma1 stream2 */ + +/* dma1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) + +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn + +#endif +/* dma1 stream3 */ + +/* dma1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) + +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn + +#endif +/* dma1 stream4 */ + +/* dma1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) + +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn + +#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) +#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream5 +#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn + +#endif +/* dma1 stream5 */ + +/* dma1 stream6 */ +/* dma1 stream6 */ + +/* dma1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) + +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn + +#endif +/* dma1 stream7 */ + +/* dma2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) + +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn + +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL) + +#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn + +#endif +/* dma2 stream0 */ + +/* dma2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) + +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn + +#endif +/* dma2 stream1 */ + +/* dma2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) + +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn + +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) + +#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream2 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn + +#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) + +#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream2 +#define QSPI_DMA_CHANNEL DMA_CHANNEL_11 +#define QSPI_DMA_IRQ DMA2_Stream2_IRQn + +#endif +/* dma2 stream2 */ + +/* dma2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) + +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn + +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) + +#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn + +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL) + +#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn + +#endif +/* dma2 stream3 */ + +/* dma2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) + +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn + +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) + +#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn + +#endif +/* dma2 stream4 */ + +/* dma2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) + +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn + +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) + +#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream5 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn + +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) + +#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn + +#endif + +/* dma2 stream5 */ + +/* dma2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) + +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn + +#endif +/* dma2 stream6 */ + +/* dma2 stream7 */ +#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) + +#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream7 +#define QSPI_DMA_CHANNEL DMA_CHANNEL_3 +#define QSPI_DMA_IRQ DMA2_Stream7_IRQn + +#endif + +/* dma2 stream7 */ + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h new file mode 100644 index 0000000000..84495c2c5a --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-01-05 zylx first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +/* dma1 channel1 */ + + + +/* dma1 channel1 */ + +/* dma1 channel2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_REQUEST) + +#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI1_RX_DMA_INSTANCE DMA1_Channel2 +#define SPI1_RX_DMA_REQUEST DMA_REQUEST_1 +#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn + +#endif +/* dma1 channel2 */ + +/* dma1 channel3 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_REQUEST) + +#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI1_TX_DMA_INSTANCE DMA1_Channel3 +#define SPI1_TX_DMA_REQUEST DMA_REQUEST_1 +#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn + +#endif +/* dma1 channel3 */ + +/* dma1 channel4 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(USART1_TX_DMA_REQUEST) + +#define USART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler +#define USART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define USART1_TX_DMA_INSTANCE DMA1_Channel4 +#define USART1_TX_DMA_REQUEST DMA_REQUEST_2 +#define USART1_TX_DMA_IRQ DMA1_Channel4_IRQn + +#endif +/* dma1 channel4 */ + +/* dma1 channel5 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_REQUEST) + +#define USART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define USART1_RX_DMA_INSTANCE DMA1_Channel5 +#define USART1_RX_DMA_REQUEST DMA_REQUEST_2 +#define USART1_RX_DMA_IRQ DMA1_Channel5_IRQn + +#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) + +#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN +#define QSPI_DMA_INSTANCE DMA1_Channel5 +#define QSPI_DMA_CHANNEL DMA_REQUEST_5 +#define QSPI_DMA_IRQ DMA1_Channel5_IRQn + +#endif +/* dma1 channel5 */ + +/* dma1 channel6 */ +/* dma1 channel6 */ + +/* dma1 channel7 */ + + + +/* dma1 channel7 */ + +/* dma2 channel1 */ +#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_REQUEST) + +#define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler +#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART5_TX_DMA_INSTANCE DMA2_Channel1 +#define UART5_TX_DMA_REQUEST DMA_REQUEST_2 +#define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn + +#endif +/* dma2 channel1 */ + +/* dma2 channel2 */ +#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_REQUEST) + +#define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler +#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART5_RX_DMA_INSTANCE DMA2_Channel2 +#define UART5_RX_DMA_REQUEST DMA_REQUEST_2 +#define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn + +#endif +/* dma2 channel2 */ + +/* dma2 channel3 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_REQUEST) + +#define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Channel3 +#define SPI1_RX_DMA_REQUEST DMA_REQUEST_4 +#define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn + +#endif +/* dma2 channel3 */ + +/* dma2 channel4 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_REQUEST) + +#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Channel4 +#define SPI1_TX_DMA_REQUEST DMA_REQUEST_4 +#define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn + +#endif +/* dma2 channel4 */ + +/* dma2 channel5 */ + + + +/* dma2 channel5 */ + +/* dma2 channel6 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(USART1_TX_DMA_REQUEST) + +#define USART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler +#define USART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_TX_DMA_INSTANCE DMA2_Channel6 +#define USART1_TX_DMA_REQUEST DMA_REQUEST_2 +#define USART1_TX_DMA_IRQ DMA2_Channel6_IRQn + +#endif +/* dma2 channel6 */ + +/* dma2 channel7 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_REQUEST) + +#define USART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Channel7 +#define USART1_RX_DMA_REQUEST DMA_REQUEST_2 +#define USART1_RX_DMA_IRQ DMA2_Channel7_IRQn + +#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) + +#define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Channel7 +#define QSPI_DMA_CHANNEL DMA_REQUEST_3 +#define QSPI_DMA_IRQ DMA2_Channel7_IRQn + +#endif +/* dma2 channel7 */ + +#endif /* __DMA_CONFIG_H__ */ From 574492a2820f3d38d8e1738065a3c0b6709bb0d9 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 11:58:57 +0800 Subject: [PATCH 02/15] [bsp][stm32] Modify the DMA implementation --- .../HAL_Drivers/config/f0/uart_config.h | 52 +- .../HAL_Drivers/config/f1/spi_config.h | 127 +++-- .../HAL_Drivers/config/f1/uart_config.h | 147 +++-- .../HAL_Drivers/config/f4/spi_config.h | 231 +++++--- .../HAL_Drivers/config/f4/uart_config.h | 153 ++++-- .../HAL_Drivers/config/f7/qspi_config.h | 9 +- .../HAL_Drivers/config/f7/spi_config.h | 245 +++++---- .../HAL_Drivers/config/f7/uart_config.h | 153 ++++-- .../HAL_Drivers/config/l4/qspi_config.h | 7 +- .../HAL_Drivers/config/l4/spi_config.h | 52 +- .../HAL_Drivers/config/l4/uart_config.h | 64 ++- bsp/stm32/libraries/HAL_Drivers/drv_config.h | 5 + bsp/stm32/libraries/HAL_Drivers/drv_dma.h | 5 +- bsp/stm32/libraries/HAL_Drivers/drv_qspi.c | 14 +- bsp/stm32/libraries/HAL_Drivers/drv_spi.c | 501 ++++++++++-------- bsp/stm32/libraries/HAL_Drivers/drv_spi.h | 14 +- bsp/stm32/libraries/HAL_Drivers/drv_usart.c | 100 ++-- bsp/stm32/libraries/HAL_Drivers/drv_usart.h | 38 +- 18 files changed, 1169 insertions(+), 748 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h index 44cbe30039..64ad12adf4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h @@ -15,34 +15,46 @@ #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.Instance = DMA1_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } - -#define USART1_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler #endif /* UART1_CONFIG */ #endif /* BSP_USING_UART1 */ +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.Instance = DMA1_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } - -#define USART2_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #endif /* __UART_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h index a910847e39..b77ce5ef3b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-11-06 SummerGift change to new framework + * 2018-11-06 SummerGift first version + * 2019-01-05 SummerGift modify DMA support */ #ifndef __SPI_CONFIG_H__ @@ -14,55 +15,101 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel2, \ - .dma_rx.dma_irq = DMA1_Channel2_IRQn, \ - .dma_tx.Instance = DMA1_Channel3, \ - .dma_tx.dma_irq = DMA1_Channel3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ -#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler -#endif +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 -#define SPI2_BUS_CONFIG \ - { \ - .Instance = SPI2, \ - .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel4, \ - .dma_rx.dma_irq = DMA1_Channel4_IRQn, \ - .dma_tx.Instance = DMA1_Channel5, \ - .dma_tx.dma_irq = DMA1_Channel5_IRQn, \ +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ -#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler -#endif +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 -#define SPI3_BUS_CONFIG \ - { \ - .Instance = SPI3, \ - .bus_name = "spi3", \ - .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Channel1, \ - .dma_rx.dma_irq = DMA2_Channel1_IRQn, \ - .dma_tx.Instance = DMA2_Channel2, \ - .dma_tx.dma_irq = DMA2_Channel2_IRQn, \ +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ -#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler -#endif +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + #endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h index fd7482f4e6..f7c5f41f9b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h @@ -5,81 +5,122 @@ * * Change Logs: * Date Author Notes - * 2018-10-30 BalanceTWK change to new framework + * 2018-10-30 BalanceTWK first version + * 2019-01-05 SummerGift modify DMA support */ #ifndef __UART_CONFIG_H__ #define __UART_CONFIG_H__ #include +#include "dma_config.h" #if defined(BSP_USING_UART1) -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.channel.Instance = DMA1_Channel5, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Channel5_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA1_Channel5_IRQHandler -#endif +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_USING_UART2) - -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.channel.Instance = DMA1_Channel6, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Channel6_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ -#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler -#endif - #if defined(BSP_USING_UART3) - -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .dma.channel.Instance = DMA1_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA1EN, \ - .dma_irq = DMA1_Channel3_IRQn, \ +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ -#define USART3_RX_DMA_ISR DMA1_Channel3_IRQHandler -#endif +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_CONFIG +#define UART3_DMA_CONFIG \ + { \ + .Instance = USART3_RX_DMA_INSTANCE, \ + .dma_rcc = USART3_RX_DMA_RCC, \ + .dma_irq = USART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_USING_UART4) - -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = UART4, \ - .irq_type = UART4_IRQn, \ - .dma.channel.Instance = DMA2_Channel3, \ - .dma_rcc = RCC_AHBENR_DMA2EN, \ - .dma_irq = DMA2_Channel3_IRQn, \ +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ -#define USART4_RX_DMA_ISR DMA2_Channel3_IRQHandler -#endif +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_CONFIG +#define UART4_DMA_CONFIG \ + { \ + .Instance = USART4_RX_DMA_INSTANCE, \ + .dma_rcc = USART4_RX_DMA_RCC, \ + .dma_irq = USART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_USING_UART5) - -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .dma.channel.Instance = DMA_NOT_AVAILABLE, \ +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ } -#endif +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_CONFIG +#define UART5_DMA_CONFIG \ + { \ + .Instance = DMA_NOT_AVAILABLE, \ + } +#endif /* UART5_DMA_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ + #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h index abeecd7154..3cd3f69884 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-11-06 SummerGift change to new framework + * 2018-11-06 SummerGift first version + * 2019-01-03 zylx modify DMA support */ #ifndef __SPI_CONFIG_H__ @@ -14,101 +15,173 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream2, \ - .dma_rx.channel = DMA_CHANNEL_3, \ - .dma_rx.dma_irq = DMA2_Stream2_IRQn, \ - .dma_tx.Instance = DMA2_Stream3, \ - .dma_tx.channel = DMA_CHANNEL_3, \ - .dma_tx.dma_irq = DMA2_Stream3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ -#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#endif +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 -#define SPI2_BUS_CONFIG \ - { \ - .Instance = SPI2, \ - .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream3_IRQn, \ - .dma_tx.Instance = DMA1_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream4_IRQn, \ +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ -#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler -#endif +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 -#define SPI3_BUS_CONFIG \ - { \ - .Instance = SPI3, \ - .bus_name = "spi3", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream0_IRQn, \ - .dma_tx.Instance = DMA1_Stream5, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream5_IRQn, \ +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler -#endif +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 -#define SPI4_BUS_CONFIG \ - { \ - .Instance = SPI4, \ - .bus_name = "spi4", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream0_IRQn, \ - .dma_tx.Instance = DMA2_Stream1, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream1_IRQn, \ +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_TX_DMA_RCC, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#endif +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_RX_DMA_RCC, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 -#define SPI5_BUS_CONFIG \ - { \ - .Instance = SPI5, \ - .bus_name = "spi5", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_2, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_2, \ - .dma_tx.dma_irq = DMA2_Stream4_IRQn, \ +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_TX_DMA_RCC, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#endif +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_RX_DMA_RCC, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ #endif /*__SPI_CONFIG_H__ */ - - - diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h index d8fab2c361..20dca9cee2 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-10-30 SummerGift change to new framework + * 2018-10-30 SummerGift first version + * 2019-01-03 zylx modify dma support */ #ifndef __UART_CONFIG_H__ @@ -14,78 +15,118 @@ #include #if defined(BSP_USING_UART1) -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.stream_channel.Instance = DMA2_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_irq = DMA2_Stream5_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler -#endif +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .channel = USART1_RX_DMA_CHANNEL, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_USING_UART2) -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream5_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ -#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler -#endif +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .channel = USART2_RX_DMA_CHANNEL, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_USING_UART3) -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream1, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream1_IRQn, \ +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ -#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler -#endif +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_CONFIG +#define UART3_DMA_CONFIG \ + { \ + .Instance = USART3_RX_DMA_INSTANCE, \ + .channel = USART3_RX_DMA_CHANNEL, \ + .dma_rcc = USART3_RX_DMA_RCC, \ + .dma_irq = USART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_USING_UART4) -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = UART4, \ - .irq_type = UART4_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream2, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream2_IRQn, \ +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ -#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler -#endif +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_CONFIG +#define UART4_DMA_CONFIG \ + { \ + .Instance = USART4_RX_DMA_INSTANCE, \ + .channel = USART4_RX_DMA_CHANNEL, \ + .dma_rcc = USART4_RX_DMA_RCC, \ + .dma_irq = USART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_USING_UART5) -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream0, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream0_IRQn, \ +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ -#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler -#endif +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_CONFIG +#define UART5_DMA_CONFIG \ + { \ + .Instance = USART5_RX_DMA_INSTANCE, \ + .channel = USART5_RX_DMA_CHANNEL, \ + .dma_rcc = USART5_RX_DMA_RCC, \ + .dma_irq = USART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h index 5e148aa250..d69ab7aff9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h @@ -24,13 +24,13 @@ } #endif /* QSPI_BUS_CONFIG */ #endif /* BSP_USING_QSPI */ - + #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ { \ - .Instance = DMA2_Stream7, \ - .Init.Channel = DMA_CHANNEL_3, \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ .Init.Direction = DMA_PERIPH_TO_MEMORY, \ .Init.PeriphInc = DMA_PINC_DISABLE, \ .Init.MemInc = DMA_MINC_ENABLE, \ @@ -42,10 +42,7 @@ #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ -#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE() #define QSPI_IRQn QUADSPI_IRQn -#define QSPI_DMA_IRQn DMA2_Stream7_IRQn #define QSPI_IRQHandler QUADSPI_IRQHandler -#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler #endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h index 41c10756a0..ac18fcd015 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h @@ -14,120 +14,173 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream2, \ - .dma_rx.channel = DMA_CHANNEL_3, \ - .dma_rx.dma_irq = DMA2_Stream2_IRQn, \ - .dma_tx.Instance = DMA2_Stream3, \ - .dma_tx.channel = DMA_CHANNEL_3, \ - .dma_tx.dma_irq = DMA2_Stream3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ -#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#endif +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 -#define SPI2_BUS_CONFIG \ - { \ - .Instance = SPI2, \ - .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream3_IRQn, \ - .dma_tx.Instance = DMA1_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream4_IRQn, \ +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ -#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler -#endif +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 -#define SPI3_BUS_CONFIG \ - { \ - .Instance = SPI3, \ - .bus_name = "spi3", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_0, \ - .dma_rx.dma_irq = DMA1_Stream0_IRQn, \ - .dma_tx.Instance = DMA1_Stream7, \ - .dma_tx.channel = DMA_CHANNEL_0, \ - .dma_tx.dma_irq = DMA1_Stream7_IRQn, \ +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler -#endif +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 -#define SPI4_BUS_CONFIG \ - { \ - .Instance = SPI4, \ - .bus_name = "spi4", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream0, \ - .dma_rx.channel = DMA_CHANNEL_4, \ - .dma_rx.dma_irq = DMA2_Stream0_IRQn, \ - .dma_tx.Instance = DMA2_Stream1, \ - .dma_tx.channel = DMA_CHANNEL_4, \ - .dma_tx.dma_irq = DMA2_Stream1_IRQn, \ +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_TX_DMA_RCC, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#endif +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_RX_DMA_RCC, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 -#define SPI5_BUS_CONFIG \ - { \ - .Instance = SPI5, \ - .bus_name = "spi5", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream3, \ - .dma_rx.channel = DMA_CHANNEL_2, \ - .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ - .dma_tx.Instance = DMA2_Stream4, \ - .dma_tx.channel = DMA_CHANNEL_2, \ - .dma_tx.dma_irq = DMA2_Stream4_IRQn, \ +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ } - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#endif - -#ifdef BSP_USING_SPI6 -#define SPI5_BUS_CONFIG \ - { \ - .Instance = SPI6, \ - .bus_name = "spi6", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_rx.Instance = DMA2_Stream6, \ - .dma_rx.channel = DMA_CHANNEL_1, \ - .dma_rx.dma_irq = DMA2_Stream6_IRQn, \ - .dma_tx.Instance = DMA2_Stream5, \ - .dma_tx.channel = DMA_CHANNEL_1, \ - .dma_tx.dma_irq = DMA2_Stream5_IRQn, \ +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_TX_DMA_RCC, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ -#define SPI6_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler -#define SPI6_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler -#endif +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_RX_DMA_RCC, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ #endif /*__SPI_CONFIG_H__ */ - - - diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h index d8fab2c361..ae343a1621 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-10-30 SummerGift change to new framework + * 2018-10-30 SummerGift first version + * 2019-01-05 zylx modify dma support */ #ifndef __UART_CONFIG_H__ @@ -14,78 +15,118 @@ #include #if defined(BSP_USING_UART1) -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.stream_channel.Instance = DMA2_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_irq = DMA2_Stream5_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler -#endif +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .channel = USART1_RX_DMA_CHANNEL, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ #if defined(BSP_USING_UART2) -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream5, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream5_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ -#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler -#endif +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .channel = USART2_RX_DMA_CHANNEL, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #if defined(BSP_USING_UART3) -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream1, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream1_IRQn, \ +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ -#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler -#endif +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_CONFIG +#define UART3_DMA_CONFIG \ + { \ + .Instance = USART3_RX_DMA_INSTANCE, \ + .channel = USART3_RX_DMA_CHANNEL, \ + .dma_rcc = USART3_RX_DMA_RCC, \ + .dma_irq = USART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ #if defined(BSP_USING_UART4) -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = UART4, \ - .irq_type = UART4_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream2, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream2_IRQn, \ +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ -#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler -#endif +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_CONFIG +#define UART4_DMA_CONFIG \ + { \ + .Instance = USART4_RX_DMA_INSTANCE, \ + .channel = USART4_RX_DMA_CHANNEL, \ + .dma_rcc = USART4_RX_DMA_RCC, \ + .dma_irq = USART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ #if defined(BSP_USING_UART5) -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .dma.stream_channel.Instance = DMA1_Stream0, \ - .dma.stream_channel.channel = DMA_CHANNEL_4, \ - .dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_irq = DMA1_Stream0_IRQn, \ +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ -#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler -#endif +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_CONFIG +#define UART5_DMA_CONFIG \ + { \ + .Instance = USART5_RX_DMA_INSTANCE, \ + .channel = USART5_RX_DMA_CHANNEL, \ + .dma_rcc = USART5_RX_DMA_RCC, \ + .dma_irq = USART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h index 93a018ac85..ae968c0cfc 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h @@ -29,8 +29,8 @@ #ifndef QSPI_DMA_CONFIG #define QSPI_DMA_CONFIG \ { \ - .Instance = DMA1_Channel5, \ - .Init.Request = DMA_REQUEST_5, \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Request = QSPI_DMA_CHANNEL, \ .Init.Direction = DMA_PERIPH_TO_MEMORY, \ .Init.PeriphInc = DMA_PINC_DISABLE, \ .Init.MemInc = DMA_MINC_ENABLE, \ @@ -42,10 +42,7 @@ #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ -#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE() #define QSPI_IRQn QUADSPI_IRQn -#define QSPI_DMA_IRQn DMA1_Channel5_IRQn #define QSPI_IRQHandler QUADSPI_IRQHandler -#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler #endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h index 054f55ff77..4a595cd9ff 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h @@ -14,22 +14,38 @@ #include #ifdef BSP_USING_SPI1 -#define SPI1_BUS_CONFIG \ - { \ - .Instance = SPI1, \ - .bus_name = "spi1", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_rx.Instance = DMA1_Channel2, \ - .dma_rx.request = DMA_REQUEST_1, \ - .dma_rx.dma_irq = DMA1_Channel2_IRQn, \ - .dma_tx.Instance = DMA1_Channel3, \ - .dma_tx.request = DMA_REQUEST_1, \ - .dma_tx.dma_irq = DMA1_Channel3_IRQn, \ +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ } -#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler -#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler -#endif +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .request = SPI1_TX_DMA_REQUEST, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .request = SPI1_RX_DMA_REQUEST, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #define SPI2_BUS_CONFIG \ @@ -45,8 +61,7 @@ .dma_tx.request = DMA_REQUEST_1, \ .dma_tx.dma_irq = DMA1_Channel5_IRQn, \ } -#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler -#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler + #endif #ifdef BSP_USING_SPI3 @@ -63,8 +78,7 @@ .dma_tx.request = DMA_REQUEST_3, \ .dma_tx.dma_irq = DMA2_Channel2_IRQn, \ } -#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler -#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler + #endif #endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h index 46d5414f55..0b27ff77c8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h @@ -14,35 +14,49 @@ #include #if defined(BSP_USING_UART1) - -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .dma.channel_request.Instance = DMA2_Channel7, \ - .dma.channel_request.request = DMA_REQUEST_2, \ - .dma_rcc = RCC_AHB1ENR_DMA2EN, \ - .dma_irq = DMA2_Channel7_IRQn, \ +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ -#define USART1_RX_DMA_ISR DMA2_Channel7_IRQHandler -#endif - +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_CONFIG +#define UART1_DMA_CONFIG \ + { \ + .Instance = USART1_RX_DMA_INSTANCE, \ + .request = USART1_RX_DMA_REQUEST, \ + .dma_rcc = USART1_RX_DMA_RCC, \ + .dma_irq = USART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + #if defined(BSP_USING_UART2) - -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .dma.channel_request.Instance = DMA1_Channel6, \ - .dma.channel_request.request = DMA_REQUEST_2, \ - .dma_rcc = RCC_AHB1SMENR_DMA1SMEN, \ - .dma_irq = DMA1_Channel6_IRQn, \ +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ -#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler -#endif +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_CONFIG +#define UART2_DMA_CONFIG \ + { \ + .Instance = USART2_RX_DMA_INSTANCE, \ + .request = USART2_RX_DMA_REQUEST, \ + .dma_rcc = USART2_RX_DMA_RCC, \ + .dma_irq = USART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 1046b44c09..214552398e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -15,12 +15,14 @@ #include #if defined(SOC_SERIES_STM32F0) +#include "f0/dma_config.h" #include "f0/uart_config.h" #include "f0/spi_config.h" #include "f0/tim_config.h" #include "f0/pwm_config.h" #include "f0/adc_config.h" #elif defined(SOC_SERIES_STM32F1) +#include "f1/dma_config.h" #include "f1/uart_config.h" #include "f1/spi_config.h" #include "f1/adc_config.h" @@ -28,6 +30,7 @@ #include "f1/sdio_config.h" #include "f1/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) +#include "f4/dma_config.h" #include "f4/uart_config.h" #include "f4/spi_config.h" #include "f4/adc_config.h" @@ -35,6 +38,7 @@ #include "f4/sdio_config.h" #include "f4/pwm_config.h" #elif defined(SOC_SERIES_STM32F7) +#include "f7/dma_config.h" #include "f7/uart_config.h" #include "f7/spi_config.h" #include "f7/qspi_config.h" @@ -43,6 +47,7 @@ #include "f7/sdio_config.h" #include "f7/pwm_config.h" #elif defined(SOC_SERIES_STM32L4) +#include "l4/dma_config.h" #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/qspi_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h index 4c266eafce..b56cb1e941 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2018-11-10 SummerGift change to new framework + * 2018-11-10 SummerGift first version */ #ifndef __DRV_DMA_H_ @@ -16,7 +16,7 @@ #include #include -#if defined(SOC_SERIES_STM32F0) || (SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define DMA_INSTANCE_TYPE DMA_Stream_TypeDef @@ -36,5 +36,4 @@ struct dma_config { #endif }; - #endif /*__DRV_DMA_H_ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c index 95b7cf10ad..6b54ad2c7a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c @@ -92,11 +92,19 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */ HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0); HAL_NVIC_EnableIRQ(QSPI_IRQn); - HAL_NVIC_SetPriority(QSPI_DMA_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(QSPI_DMA_IRQn); + HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0); + HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ); /* init QSPI DMA */ - QSPI_DMA_CLK_ENABLE; + if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN) + { + __HAL_RCC_DMA1_CLK_ENABLE(); + } + else + { + __HAL_RCC_DMA2_CLK_ENABLE(); + } + HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma); DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG; qspi_bus->hdma_quadspi = hdma_quadspi_config; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index fd70be7d2b..033cd2859f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -5,15 +5,16 @@ * * Change Logs: * Date Author Notes - * 2018-11-5 SummerGift change to new framework + * 2018-11-5 SummerGift first version * 2018-12-11 greedyhao Porting for stm32f7xx + * 2019-01-03 zylx modify DMA initialization and spixfer function */ #include "board.h" #ifdef RT_USING_SPI -#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ #include "drv_spi.h" @@ -72,7 +73,7 @@ static struct stm32_spi_config spi_config[] = #endif }; -static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])]; +static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg) { @@ -201,6 +202,10 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->Init.TIMode = SPI_TIMODE_DISABLE; spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; spi_handle->State = HAL_SPI_STATE_RESET; +#ifdef SOC_SERIES_STM32L4 + spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; +#endif + if (HAL_SPI_Init(spi_handle) != HAL_OK) { return RT_EIO; @@ -210,204 +215,112 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF); #endif + /* DMA configuration */ + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + HAL_DMA_Init(&spi_drv->dma.handle_rx); + + __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx); + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq); + } + + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + HAL_DMA_Init(&spi_drv->dma.handle_tx); + + __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx); + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1); + HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq); + } + __HAL_SPI_ENABLE(spi_handle); LOG_D("%s init done", spi_drv->config->bus_name); return RT_EOK; } -#ifdef BSP_SPI_USING_DMA -static uint8_t dummy = 0xFF; -static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_message* message) -{ - struct stm32_spi *spi_drv = rt_container_of(spi_bus, struct stm32_spi, spi_bus); - - DMA_HandleTypeDef * hdma_tx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_tx; - DMA_HandleTypeDef * hdma_rx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_rx; - - HAL_DMA_DeInit(hdma_tx); - HAL_DMA_DeInit(hdma_rx); - - /* - * Check if the DMA Stream is disabled before enabling it. - * Note that this step is useful when the same Stream is used multiple times. - */ -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - while (hdma_tx->Instance->CR & DMA_SxCR_EN); - while (hdma_rx->Instance->CR & DMA_SxCR_EN); -#endif - - if(message->recv_buf != RT_NULL) - { - hdma_rx->Init.MemInc = DMA_MINC_ENABLE; - } - else - { - message->recv_buf = &dummy; - hdma_rx->Init.MemInc = DMA_MINC_DISABLE; - } - HAL_DMA_Init(hdma_rx); - - __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx); - - if(message->send_buf != RT_NULL) - { - hdma_tx->Init.MemInc = DMA_MINC_ENABLE; - } - else - { - dummy = 0xFF; - message->send_buf = &dummy; - hdma_tx->Init.MemInc = DMA_MINC_DISABLE; - } - HAL_DMA_Init(hdma_tx); - - /* link DMA with SPI */ - __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx); - - LOG_D("%s RX Instance: %x, TX Instance: %x", spi_drv->config->bus_name, hdma_rx->Instance, hdma_tx->Instance); - LOG_D("%s dma config done, TX dma_irq number: %d, RX dma_irq number: %d", - spi_drv->config->bus_name, - spi_drv->config->dma_tx.dma_irq, - spi_drv->config->dma_rx.dma_irq); - - /* NVIC configuration for DMA transfer complete interrupt*/ - HAL_NVIC_SetPriority(spi_drv->config->dma_tx.dma_irq, 0, 1); - HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx.dma_irq); - - /* NVIC configuration for DMA transfer complete interrupt*/ - HAL_NVIC_SetPriority(spi_drv->config->dma_rx.dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx.dma_irq); -} -#endif - static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { + HAL_StatusTypeDef state; + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); RT_ASSERT(message != RT_NULL); struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus); - SPI_HandleTypeDef * spi_handle = &spi_drv->handle; + SPI_HandleTypeDef *spi_handle = &spi_drv->handle; struct stm32_hw_spi_cs *cs = device->parent.user_data; - rt_int32_t length = message->length; - rt_int32_t data_width = spi_drv->cfg->data_width; if (message->cs_take) { HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET); } -#ifdef BSP_SPI_USING_DMA - if(message->length > 32) + LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + spi_drv->config->bus_name, + (uint32_t)message->send_buf, + (uint32_t)message->recv_buf, message->length); + + if (message->length) { - if(data_width <= 8) + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) { - HAL_StatusTypeDef state; - LOG_D("%s dma transfer prepare and start", spi_drv->config->bus_name); - LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", - spi_drv->config->bus_name, - (uint32_t)message->send_buf, - (uint32_t)message->recv_buf, message->length); - - spi_dma_transfer_prepare(device->bus, message); - /* start once data exchange in DMA mode */ - state = HAL_SPI_TransmitReceive_DMA(spi_handle, - (uint8_t*)message->send_buf, - (uint8_t*)message->recv_buf, - message->length); - if (state != HAL_OK) + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length); + }else + { + state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, 1000); + } + } + else if (message->send_buf) + { + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) { - LOG_D("spi flash configuration error : %d", state); - message->length = 0; - //while(1); + state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)message->send_buf, message->length); } else { - LOG_D("%s dma transfer done", spi_drv->config->bus_name); + state = HAL_SPI_Transmit(spi_handle, (uint8_t *)message->send_buf, message->length, 1000); } - - /* For simplicity reasons, this example is just waiting till the end of the - transfer, but application may perform other tasks while transfer operation - is ongoing. */ - while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY); - LOG_D("%s get state done", spi_drv->config->bus_name); } else { - // TODO - } - } else -#endif - { - if (data_width == 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - - while (length--) + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { - rt_uint8_t data = ~0; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /* send data once */ - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET); - *(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data; - - /* receive data once */ -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7) - SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF); -#endif - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET); - data = *(volatile rt_uint8_t *)(&spi_handle->Instance->DR); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } + state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)message->recv_buf, message->length); } - - } else - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - - while (length--) + else { - rt_uint16_t data = ~0; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /* send data once */ - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET); - *(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data; - - /* receive data once */ -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7) - SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF); -#endif - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET); - data = *(volatile rt_uint16_t *)(&spi_handle->Instance->DR); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } + state = HAL_SPI_Receive(spi_handle, (uint8_t *)message->recv_buf, message->length, 1000); } } + + if (state != HAL_OK) + { + LOG_I("spi transfer error : %d", state); + message->length = 0; + spi_handle->State = HAL_SPI_STATE_READY; + } + else + { + LOG_D("%s transfer done", spi_drv->config->bus_name); + } + + /* For simplicity reasons, this example is just waiting till the end of the + transfer, but application may perform other tasks while transfer operation + is ongoing. */ + while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY); } - - /* Wait until Busy flag is reset before disabling SPI */ - while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_BSY) == SET); - + if (message->cs_release) { HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET); @@ -443,61 +356,81 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; spi_bus_obj[i].handle.Instance = spi_config[i].Instance; -#ifdef BSP_SPI_USING_DMA - /* Configure the DMA handler for Transmission process */ - spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance; + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + /* Configure the DMA handler for Transmission process */ + spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance; #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel; + spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel; #elif defined(SOC_SERIES_STM32L4) - spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request; + spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request; #endif - spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; - spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; - spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; + spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; + spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE; + spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; + spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; - spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; + spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; + spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; #endif - spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance; -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel; -#elif defined(SOC_SERIES_STM32L4) - spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request; -#endif - spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE; - spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; - spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; - spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; -#endif { rt_uint32_t tmpreg = 0x00U; #if defined(SOC_SERIES_STM32F1) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc); + SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) - SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc); + SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); #endif UNUSED(tmpreg); /* To avoid compiler warnings */ } + } - LOG_D("%s DMA clock init done", spi_config[i].bus_name); -#endif /* BSP_SPI_USING_DMA */ + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + /* Configure the DMA handler for Transmission process */ + spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance; +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) + spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel; +#elif defined(SOC_SERIES_STM32L4) + spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request; +#endif + spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; + spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) + spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; + spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; +#endif + + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) + SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); +#endif + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + } result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops); RT_ASSERT(result == RT_EOK); @@ -511,7 +444,7 @@ static int rt_hw_spi_bus_init(void) /** * Attach the spi device to SPI bus, this function must be used after initialization. */ -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin) +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) { RT_ASSERT(bus_name != RT_NULL); RT_ASSERT(device_name != RT_NULL); @@ -550,7 +483,20 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, return result; } -#if defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) +void SPI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -566,7 +512,9 @@ void SPI1_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -584,7 +532,20 @@ void SPI1_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) +void SPI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -600,7 +561,9 @@ void SPI2_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -618,7 +581,20 @@ void SPI2_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA) +void SPI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -634,7 +610,9 @@ void SPI3_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -652,8 +630,20 @@ void SPI3_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */ +#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA) +void SPI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); -#if defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) + HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -669,7 +659,9 @@ void SPI4_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -687,7 +679,20 @@ void SPI4_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA) +void SPI5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -703,7 +708,9 @@ void SPI5_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -721,7 +728,7 @@ void SPI5_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */ -#if defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -737,7 +744,9 @@ void SPI6_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA) /** * @brief This function handles DMA Tx interrupt request. * @param None @@ -755,8 +764,78 @@ void SPI6_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */ +static void stm32_get_dma_info(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; +#endif +#ifdef BSP_SPI1_TX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; +#endif +#ifdef BSP_SPI2_TX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; +#endif + +#ifdef BSP_SPI3_RX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; +#endif +#ifdef BSP_SPI3_TX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; +#endif + +#ifdef BSP_SPI4_RX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; +#endif +#ifdef BSP_SPI4_TX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; +#endif + +#ifdef BSP_SPI5_RX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; +#endif +#ifdef BSP_SPI5_TX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; +#endif + +#ifdef BSP_SPI6_RX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; +#endif +#ifdef BSP_SPI6_TX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; +#endif +} + int rt_hw_spi_init(void) { + stm32_get_dma_info(); return rt_hw_spi_bus_init(); } INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h index 710f3fa59c..763a44dfdf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2018-11-5 SummerGift change to new framework + * 2018-11-5 SummerGift first version */ #ifndef __DRV_SPI_H_ @@ -29,7 +29,7 @@ struct stm32_spi_config { SPI_TypeDef *Instance; char *bus_name; - struct dma_config dma_rx, dma_tx; + struct dma_config *dma_rx, *dma_tx; }; struct stm32_spi_device @@ -39,21 +39,23 @@ struct stm32_spi_device char *device_name; }; +#define SPI_USING_RX_DMA_FLAG (1<<0) +#define SPI_USING_TX_DMA_FLAG (1<<1) + /* stm32 spi dirver class */ struct stm32_spi { SPI_HandleTypeDef handle; - const struct stm32_spi_config *config; + struct stm32_spi_config *config; struct rt_spi_configuration *cfg; - -#ifdef BSP_SPI_USING_DMA + struct { DMA_HandleTypeDef handle_rx; DMA_HandleTypeDef handle_tx; } dma; -#endif + rt_uint8_t spi_dma_flag; struct rt_spi_bus spi_bus; }; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c index 916d0ed2d2..87543442b6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c @@ -46,7 +46,7 @@ enum #endif }; -static const struct stm32_uart_config uart_config[] = +static struct stm32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 UART1_CONFIG, @@ -65,7 +65,7 @@ static const struct stm32_uart_config uart_config[] = #endif }; -static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])]; +static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -239,7 +239,7 @@ static void uart_isr(struct rt_serial_device *serial) UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE); } #ifdef RT_SERIAL_USING_DMA - else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) && + else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET)) { level = rt_hw_interrupt_disable(); @@ -309,8 +309,8 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) -void USART1_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) +void USART1_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -320,7 +320,7 @@ void USART1_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) */ +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) @@ -334,8 +334,8 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART2_RX_DMA_ISR) -void USART2_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) +void USART2_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -345,7 +345,7 @@ void USART2_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART2_RX_DMA_ISR) */ +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) @@ -359,8 +359,8 @@ void USART3_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART3_RX_DMA_ISR) -void USART3_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) +void USART3_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -370,7 +370,7 @@ void USART3_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART3_RX_DMA_ISR) */ +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ #endif /* BSP_USING_UART3*/ #if defined(BSP_USING_UART4) @@ -384,8 +384,8 @@ void UART4_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) -void USART4_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) +void USART4_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -395,7 +395,7 @@ void USART4_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART4_RX_DMA_ISR) */ +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ #endif /* BSP_USING_UART4*/ #if defined(BSP_USING_UART5) @@ -409,8 +409,8 @@ void UART5_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(USART5_RX_DMA_ISR) -void USART5_RX_DMA_ISR(void) +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) +void USART5_DMA_RX_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -420,7 +420,7 @@ void USART5_RX_DMA_ISR(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART5_RX_DMA_ISR) */ +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ #endif /* BSP_USING_UART5*/ #ifdef RT_SERIAL_USING_DMA @@ -437,12 +437,12 @@ static void stm32_dma_config(struct rt_serial_device *serial) rt_uint32_t tmpreg= 0x00U; #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, uart->config->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rcc); + SET_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc); #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHB1ENR, uart->config->dma_rcc); - tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rcc); + SET_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc); #endif UNUSED(tmpreg); /* To avoid compiler warnings */ } @@ -450,13 +450,13 @@ static void stm32_dma_config(struct rt_serial_device *serial) __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma.handle); #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) - uart->dma.handle.Instance = uart->config->dma.Instance; + uart->dma.handle.Instance = uart->config->dma_rx->Instance; #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - uart->dma.handle.Instance = uart->config->dma.Instance; - uart->dma.handle.Init.Channel = uart->config->dma.stream_channel.channel; + uart->dma.handle.Instance = uart->config->dma_rx->Instance; + uart->dma.handle.Init.Channel = uart->config->dma_rx->channel; #elif defined(SOC_SERIES_STM32L4) - uart->dma.handle.Instance = uart->config->dma.Instance; - uart->dma.handle.Init.Request = uart->config->dma.channel_request.request; + uart->dma.handle.Instance = uart->config->dma_rx->Instance; + uart->dma.handle.Init.Request = uart->config->dma_rx->request; #endif uart->dma.handle.Init.Direction = DMA_PERIPH_TO_MEMORY; uart->dma.handle.Init.PeriphInc = DMA_PINC_DISABLE; @@ -491,8 +491,8 @@ static void stm32_dma_config(struct rt_serial_device *serial) __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); /* enable rx irq */ - HAL_NVIC_SetPriority(uart->config->dma_irq, 0, 0); - HAL_NVIC_EnableIRQ(uart->config->dma_irq); + HAL_NVIC_SetPriority(uart->config->dma_rx->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(uart->config->dma_rx->dma_irq); HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); HAL_NVIC_EnableIRQ(uart->config->irq_type); @@ -547,31 +547,59 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) } #endif /* RT_SERIAL_USING_DMA */ +static void stm32_uart_get_dma_config(void) +{ +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag = 1; + static struct dma_config uart1_dma_rx = UART1_DMA_CONFIG; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag = 1; + static struct dma_config uart2_dma_rx = UART2_DMA_CONFIG; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag = 1; + static struct dma_config uart3_dma_rx = UART3_DMA_CONFIG; + uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; +#endif +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag = 1; + static struct dma_config uart4_dma_rx = UART4_DMA_CONFIG; + uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; +#endif +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag = 1; + static struct dma_config uart5_dma_rx = UART5_DMA_CONFIG; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif +} + int rt_hw_usart_init(void) { rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart); struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - rt_err_t result = 0; + stm32_uart_get_dma_config(); + for (int i = 0; i < obj_num; i++) { uart_obj[i].config = &uart_config[i]; uart_obj[i].serial.ops = &stm32_uart_ops; uart_obj[i].serial.config = config; - /* Determines whether a serial instance supports DMA */ - if(uart_obj[i].config->dma.Instance != DMA_NOT_AVAILABLE) +#if defined(RT_SERIAL_USING_DMA) + if(uart_obj[i].uart_dma_flag) { /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX -#if defined(RT_SERIAL_USING_DMA) - | RT_DEVICE_FLAG_DMA_RX -#endif + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX| RT_DEVICE_FLAG_DMA_RX ,&uart_obj[i]); } else +#endif { /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name, diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h index 7f6a359826..80716933fe 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h @@ -15,10 +15,10 @@ #include "rtdevice.h" #include #include +#include "drv_dma.h" int rt_hw_usart_init(void); - #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) @@ -37,45 +37,15 @@ struct stm32_uart_config const char *name; USART_TypeDef *Instance; IRQn_Type irq_type; - - union { - DMA_INSTANCE_TYPE *Instance; - -#if defined(SOC_SERIES_STM32F1) - /* the DMA config has channel only, such as on STM32F1xx */ - struct { - DMA_INSTANCE_TYPE *Instance; - } channel; -#endif - -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) - /* the DMA config has stream and channel, such as on STM32F4xx */ - struct { - DMA_INSTANCE_TYPE *Instance; - rt_uint32_t channel; - } stream_channel; -#endif - -#if defined(SOC_SERIES_STM32L4) - /* the DMA config has channel and request, such as on STM32L4xx */ - struct { - DMA_INSTANCE_TYPE *Instance; - rt_uint32_t request; - } channel_request; -#endif - } dma; - - rt_uint32_t dma_rcc; - IRQn_Type dma_irq; + struct dma_config *dma_rx; }; /* stm32 uart dirver class */ struct stm32_uart { UART_HandleTypeDef handle; - const struct stm32_uart_config *config; + struct stm32_uart_config *config; - #ifdef RT_SERIAL_USING_DMA struct { @@ -83,7 +53,7 @@ struct stm32_uart rt_size_t last_index; } dma; #endif - + rt_uint8_t uart_dma_flag; struct rt_serial_device serial; }; From 74395fd11410cb85da8a8fa0a9425976b31ee17a Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 12:04:44 +0800 Subject: [PATCH 03/15] [bsp][stm32] update kconfig --- bsp/stm32/stm32f091-st-nucleo/board/Kconfig | 55 ++++- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 81 ++++++-- bsp/stm32/stm32f103-atk-nano/project.uvprojx | 195 +++++++++++++----- .../stm32f103-fire-arbitrary/board/Kconfig | 106 +++++++--- .../stm32f407-atk-explorer/board/Kconfig | 76 +++++-- .../stm32f407-st-discovery/board/Kconfig | 44 ++-- bsp/stm32/stm32f429-armfly-v6/board/Kconfig | 46 +++-- bsp/stm32/stm32f429-atk-apollo/board/Kconfig | 103 ++++++--- .../stm32f429-fire-challenger/board/Kconfig | 58 ++++-- bsp/stm32/stm32f767-atk-apollo/board/Kconfig | 71 +++++-- .../stm32f767-fire-challenger/board/Kconfig | 102 ++++++--- bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 74 +++++-- 12 files changed, 772 insertions(+), 239 deletions(-) diff --git a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig index 481026ed92..681580fdce 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig @@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart2)" + select BSP_USING_UART select BSP_USING_UART2 default y @@ -21,20 +22,52 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - select RT_USING_SPI + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif + menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index 1c4ae055bb..84ef7224b6 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y @@ -19,6 +20,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (w25q16 spi2)" + select BSP_USING_SPI select BSP_USING_SPI2 select RT_USING_SFUD select RT_SFUD_USING_SFDP @@ -39,6 +41,39 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif + config BSP_USING_UART1 bool "Enable UART1" select RT_USING_SERIAL @@ -90,20 +125,42 @@ menu "On-chip Peripheral Drivers" default n endif endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - select RT_USING_SPI - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f103-atk-nano/project.uvprojx b/bsp/stm32/stm32f103-atk-nano/project.uvprojx index 4d626125a2..af0b59df29 100644 --- a/bsp/stm32/stm32f103-atk-nano/project.uvprojx +++ b/bsp/stm32/stm32f103-atk-nano/project.uvprojx @@ -1,10 +1,7 @@ - 2.1 -
### uVision Project, (C) Keil Software
- rt-thread @@ -19,28 +16,28 @@ Keil.STM32F1xx_DFP.2.2.0 http://www.keil.com/pack/ IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) 0 $$Device:STM32F103RB$Device\Include\stm32f10x.h - - - - - - - - - + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd 0 0 - - - - - + + + + + 0 0 @@ -62,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -83,14 +80,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -104,8 +101,8 @@ 0 0 3 - - + + 1 @@ -114,7 +111,7 @@ DCM.DLL -pCM3 SARMCM3.DLL - + TCM.DLL -pCM3 @@ -139,10 +136,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -175,7 +172,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -307,7 +304,7 @@ 0x0 - + 1 @@ -334,9 +331,9 @@ 0 0 - + STM32F103xB, USE_HAL_DRIVER - + applications;.;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include @@ -352,10 +349,10 @@ 0 0 - - - - + + + + @@ -367,13 +364,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + @@ -396,26 +393,36 @@ 1 board\board.c + + stm32f1xx_hal_msp.c 1 board\CubeMX_Config\Src\stm32f1xx_hal_msp.c + + startup_stm32f103xb.s 2 ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xb.s + + drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c + + drv_usart.c 1 ..\libraries\HAL_Drivers\drv_usart.c + + drv_common.c 1 @@ -431,76 +438,106 @@ 1 ..\..\..\src\clock.c + + components.c 1 ..\..\..\src\components.c + + cpu.c 1 ..\..\..\src\cpu.c + + device.c 1 ..\..\..\src\device.c + + idle.c 1 ..\..\..\src\idle.c + + ipc.c 1 ..\..\..\src\ipc.c + + irq.c 1 ..\..\..\src\irq.c + + kservice.c 1 ..\..\..\src\kservice.c + + mem.c 1 ..\..\..\src\mem.c + + memheap.c 1 ..\..\..\src\memheap.c + + mempool.c 1 ..\..\..\src\mempool.c + + object.c 1 ..\..\..\src\object.c + + scheduler.c 1 ..\..\..\src\scheduler.c + + signal.c 1 ..\..\..\src\signal.c + + thread.c 1 ..\..\..\src\thread.c + + timer.c 1 @@ -516,21 +553,29 @@ 1 ..\..\..\libcpu\arm\cortex-m3\cpuport.c + + context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + + backtrace.c 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 @@ -546,41 +591,57 @@ 1 ..\..\..\components\drivers\misc\pin.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 @@ -596,26 +657,36 @@ 1 ..\..\..\components\finsh\shell.c + + symbol.c 1 ..\..\..\components\finsh\symbol.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 ..\..\..\components\finsh\msh.c + + msh_cmd.c 1 ..\..\..\components\finsh\msh_cmd.c + + msh_file.c 1 @@ -631,66 +702,92 @@ 1 ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c + + stm32f1xx_hal_dma.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c + + stm32f1xx_hal_cortex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c + + stm32f1xx_hal_crc.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_crc.c + + stm32f1xx_hal_pwr.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c + + stm32f1xx_hal_rcc.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c + + stm32f1xx_hal_rcc_ex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c + + stm32f1xx_hal.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c + + stm32f1xx_hal_cec.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c + + stm32f1xx_hal_sram.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c + + stm32f1xx_hal_gpio.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c + + stm32f1xx_hal_gpio_ex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c + + stm32f1xx_hal_uart.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c + + stm32f1xx_hal_usart.c 1 @@ -701,11 +798,9 @@ - - - - + + + - diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig index 51ecf43ef3..2795400969 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig @@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y @@ -19,6 +20,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI select BSP_USING_SPI1 select RT_USING_SFUD select RT_SFUD_USING_SFDP @@ -89,43 +91,93 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL - default y + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_UART2 - bool "Enable UART2" - select RT_USING_SERIAL - default n + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n - config BSP_USING_UART3 - bool "Enable UART3" - select RT_USING_SERIAL - default n - + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif + config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - select RT_USING_SPI - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n - config BSP_USING_SPI3 - bool "Enable SPI3 BUS" - select RT_USING_SPI - default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index ab47b88e1c..41ce192f9e 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -9,21 +9,25 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y config BSP_USING_COM2 bool "Enable COM2 (uart2 pin conflict with Ethernet and PWM)" + select BSP_USING_UART select BSP_USING_UART2 default n config BSP_USING_COM3 bool "Enable COM3 (uart3)" + select BSP_USING_UART select BSP_USING_UART3 default n config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (w25q128 spi1)" + select BSP_USING_SPI select BSP_USING_SPI1 select RT_USING_SFUD select RT_SFUD_USING_SFDP @@ -65,15 +69,29 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y - - config BSP_USING_UART3 - bool "Enable UART3" select RT_USING_SERIAL - default n + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif menuconfig BSP_USING_TIM bool "Enable timer" @@ -112,19 +130,41 @@ menu "On-chip Peripheral Drivers" bool "Enable on-chip FLASH" default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - select RT_USING_SPI - default y - - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - select RT_USING_SPI + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif menuconfig BSP_USING_ADC bool "Enable ADC" diff --git a/bsp/stm32/stm32f407-st-discovery/board/Kconfig b/bsp/stm32/stm32f407-st-discovery/board/Kconfig index 7c0a91960b..1f5bcd321d 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32f407-st-discovery/board/Kconfig @@ -16,23 +16,41 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig index 5986331df2..498495e8d9 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig +++ b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig @@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_RS232_TO_USART bool "Enable RS232 TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y @@ -22,6 +23,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (w25q64 spi3)" + select BSP_USING_SPI select BSP_USING_SPI3 select RT_USING_SFUD select RT_SFUD_USING_SFDP @@ -60,27 +62,45 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI3 - bool "Enable SPI3 BUS" - select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index 8355099335..c8529ead4f 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -9,11 +9,13 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y config BSP_USING_COM2 bool "Enable COM2 (uart2 pin conflict with Ethernet and PWM)" + select BSP_USING_UART select BSP_USING_UART2 default n @@ -28,6 +30,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (w25q256 spi5)" + select BSP_USING_SPI select BSP_USING_SPI5 select RT_USING_SFUD select RT_SFUD_USING_SFDP @@ -66,43 +69,93 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y - - config BSP_USING_UART2 - bool "Enable UART2" select RT_USING_SERIAL - default n + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_UART3 - bool "Enable UART3" - select RT_USING_SERIAL - default n + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - select RT_USING_SPI - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n - config BSP_USING_SPI5 - bool "Enable SPI5 BUS" - select RT_USING_SPI - default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_SPI5_TX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig index 10d86df091..2c8d3f10cf 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig @@ -9,11 +9,13 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y config BSP_USING_RS232 bool "Enable RS232" + select BSP_USING_UART select BSP_USING_UART2 default n @@ -22,7 +24,8 @@ menu "Onboard Peripheral Drivers" default n config BSP_USING_SPI_FLASH - bool "Enable SPI FLASH (W25Q128 spi5)" + bool "Enable SPI FLASH (w25q256 spi5)" + select BSP_USING_SPI select BSP_USING_SPI5 select RT_USING_SFUD select RT_SFUD_USING_SFDP @@ -76,28 +79,55 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y - - config BSP_USING_UART2 - bool "Enable UART2" select RT_USING_SERIAL - default n + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI5 - bool "Enable SPI5 BUS" + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_SPI5_TX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + endif menuconfig BSP_USING_TIM bool "Enable timer" diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index d8a1575d27..e87dbd896a 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -9,11 +9,13 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y config BSP_USING_RS232 bool "Enable RS232 (uart2 pin conflict with Ethernet)" + select BSP_USING_UART select BSP_USING_UART2 default n @@ -67,28 +69,71 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y - - config BSP_USING_UART2 - bool "Enable UART2" select RT_USING_SERIAL - default n + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" +menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n config BSP_USING_QSPI bool "Enable QSPI BUS" diff --git a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig index 8945170ec8..2423430d38 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig @@ -9,11 +9,13 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y config BSP_USING_RS232 bool "Enable RS232 (uart2 pin conflict with Ethernet)" + select BSP_USING_UART select BSP_USING_UART2 default n @@ -43,43 +45,93 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y - - config BSP_USING_UART2 - bool "Enable UART2" select RT_USING_SERIAL - default n + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_UART3 - bool "Enable UART3" - select RT_USING_SERIAL - default n + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIsAL_USING_DMA + default n + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" +menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - select RT_USING_SPI - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n - config BSP_USING_SPI5 - bool "Enable SPI5 BUS" - select RT_USING_SPI - default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n + + config BSP_SPI5_TX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + endif config BSP_USING_QSPI bool "Enable QSPI BUS" diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index 2efacdb00e..538cf8d472 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_STLINK_TO_USART bool "Enable STLINK TO USART (uart1)" + select BSP_USING_UART select BSP_USING_UART1 default y @@ -21,6 +22,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SDCARD bool "Enable SDCARD (spi1)" + select BSP_USING_SPI select BSP_USING_SPI1 select BSP_SPI_USING_DMA select RT_USING_SPI_MSD @@ -37,33 +39,69 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y - - config BSP_USING_UART2 - bool "Enable UART2" select RT_USING_SERIAL - default n - + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + endif + config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - select RT_USING_SPI - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif config BSP_USING_QSPI bool "Enable QSPI BUS" From 688d8994d92856126a85f5f9a3e38593fdd514f6 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 13:59:34 +0800 Subject: [PATCH 04/15] [bsp][stm32] update drv_spi.c --- bsp/stm32/libraries/HAL_Drivers/drv_spi.c | 55 ++++++++++++----------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 033cd2859f..45f425fbe8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -19,6 +19,7 @@ #include "drv_spi.h" #include "drv_config.h" +#include //#define DRV_DEBUG #define LOG_TAG "drv.spi" @@ -204,8 +205,8 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->State = HAL_SPI_STATE_RESET; #ifdef SOC_SERIES_STM32L4 spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; -#endif - +#endif + if (HAL_SPI_Init(spi_handle) != HAL_OK) { return RT_EIO; @@ -267,19 +268,20 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * spi_drv->config->bus_name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length); - + if (message->length) { /* start once data exchange in DMA mode */ if (message->send_buf && message->recv_buf) { - if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) - { + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length); - }else - { + } + else + { state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, 1000); - } + } } else if (message->send_buf) { @@ -294,6 +296,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * } else { + memset(message->recv_buf, 0xff, message->length); if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)message->recv_buf, message->length); @@ -303,7 +306,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * state = HAL_SPI_Receive(spi_handle, (uint8_t *)message->recv_buf, message->length, 1000); } } - + if (state != HAL_OK) { LOG_I("spi transfer error : %d", state); @@ -320,7 +323,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * is ongoing. */ while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY); } - + if (message->cs_release) { HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET); @@ -379,19 +382,19 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4; #endif - { - rt_uint32_t tmpreg = 0x00U; + { + rt_uint32_t tmpreg = 0x00U; #if defined(SOC_SERIES_STM32F1) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); #endif - UNUSED(tmpreg); /* To avoid compiler warnings */ - } + UNUSED(tmpreg); /* To avoid compiler warnings */ + } } if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG) @@ -417,19 +420,19 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; #endif - { - rt_uint32_t tmpreg = 0x00U; + { + rt_uint32_t tmpreg = 0x00U; #if defined(SOC_SERIES_STM32F1) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); #endif - UNUSED(tmpreg); /* To avoid compiler warnings */ - } + UNUSED(tmpreg); /* To avoid compiler warnings */ + } } result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops); From 40a474fefa27f7bdb56946812b764faa44e25d77 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:01:02 +0800 Subject: [PATCH 05/15] [bsp][stm32] optimize eth driver --- bsp/stm32/libraries/HAL_Drivers/drv_eth.c | 56 +++++++++++++++++++++-- bsp/stm32/libraries/HAL_Drivers/drv_eth.h | 7 +++ 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c index 21c2e90cf2..315c1b9890 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c @@ -260,6 +260,9 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) /* TODO Optimize data send speed*/ LOG_D("transmit frame lenth :%d", framelength); + /* wait for unlocked */ + while (EthHandle.Lock == HAL_LOCKED); + state = HAL_ETH_TransmitFrame(&EthHandle, framelength); if (state != HAL_OK) { @@ -410,6 +413,40 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) LOG_E("eth err"); } +#ifdef PHY_USING_INTERRUPT_MODE +static void eth_phy_isr(void *args) +{ + rt_uint32_t status = 0; + static rt_uint8_t link_status = 1; + + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status); + LOG_D("phy interrupt status reg is 0x%X", status); + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status); + LOG_D("phy basic status reg is 0x%X", status); + + if (status & PHY_LINKED_STATUS_MASK) + { + if (link_status == 0) + { + link_status = 1; + LOG_D("link up"); + /* send link up. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); + } + } + else + { + if (link_status == 1) + { + link_status = 0; + LOG_I("link down"); + /* send link down. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE); + } + } +} +#endif /* PHY_USING_INTERRUPT_MODE */ + static uint8_t phy_speed = 0; #define PHY_LINK_MASK (1<<0) static void phy_monitor_thread_entry(void *parameter) @@ -435,12 +472,12 @@ static void phy_monitor_thread_entry(void *parameter) if (phy_addr == 0xFF) { - LOG_E("phy not probe!\r\n"); + LOG_E("phy not probe!"); return; } else { - LOG_D("found a phy, address:0x%02X\r\n", phy_addr); + LOG_D("found a phy, address:0x%02X", phy_addr); } /* RESET PHY */ @@ -452,7 +489,7 @@ static void phy_monitor_thread_entry(void *parameter) while (1) { HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status); - LOG_D("PHY BASIC STATUS REG:0x%04X\r\n", status); + LOG_D("PHY BASIC STATUS REG:0x%04X", status); phy_speed_new = 0; @@ -512,10 +549,21 @@ static void phy_monitor_thread_entry(void *parameter) /* send link up. */ eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); +#ifdef PHY_USING_INTERRUPT_MODE + /* configuration intterrupt pin */ + rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs"); + rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE); + + /* enable phy interrupt */ + HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MSAK_REG, PHY_INT_MASK); + + break; +#endif } /* link up. */ else { - LOG_I("link down\r\n"); + LOG_I("link down"); /* send link down. */ eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE); } diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h index fbfe08d484..378aca5838 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h @@ -55,6 +55,13 @@ #define PHY_10M_MASK ((1<<12) || (1<<13)) #define PHY_100M_MASK ((1<<14) || (1<<15)) #define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13)) +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x15U +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MSAK_REG 0x15U +#define PHY_LINK_CHANGE_FLAG (1<<2) +#define PHY_LINK_CHANGE_MASK (1<<9) +#define PHY_INT_MASK 0 #endif /* PHY_USING_DM9161CEP */ From 02a1fa307987d3883c9eeaebfd00061b4c2af0e3 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:01:51 +0800 Subject: [PATCH 06/15] [bsp][stm32] add hwtimer driver for f7 series --- bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c index 8c3b42606a..57ff812c52 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c @@ -288,13 +288,13 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) { #if defined(SOC_SERIES_STM32L4) val = HAL_RCC_GetPCLK2Freq() / freq; -#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) +#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) val = HAL_RCC_GetPCLK2Freq() * 2 / freq; #endif } else { -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) val = HAL_RCC_GetPCLK1Freq() * 2 / freq; #elif defined(SOC_SERIES_STM32F0) val = HAL_RCC_GetPCLK1Freq() / freq; From 883a9f1e131c4e38193ff367a7068af8135c10e4 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:07:46 +0800 Subject: [PATCH 07/15] [bsp][stm32] update dma config in Kconfig --- .../libraries/templates/stm32f0xx/.config | 36 ++---- .../templates/stm32f0xx/board/Kconfig | 42 +++++-- .../libraries/templates/stm32f0xx/rtconfig.h | 12 +- .../libraries/templates/stm32f10x/.config | 16 +-- .../templates/stm32f10x/board/Kconfig | 42 +++++-- .../libraries/templates/stm32f10x/rtconfig.h | 6 +- .../libraries/templates/stm32f4xx/.config | 16 +-- .../templates/stm32f4xx/board/Kconfig | 42 +++++-- .../libraries/templates/stm32f4xx/rtconfig.h | 6 +- .../libraries/templates/stm32f7xx/.config | 16 +-- .../templates/stm32f7xx/board/Kconfig | 42 +++++-- .../libraries/templates/stm32f7xx/rtconfig.h | 6 +- .../libraries/templates/stm32l4xx/.config | 16 +-- .../templates/stm32l4xx/board/Kconfig | 40 ++++-- .../libraries/templates/stm32l4xx/rtconfig.h | 6 +- bsp/stm32/stm32f091-st-nucleo/.config | 43 +++---- bsp/stm32/stm32f091-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32f091-st-nucleo/rtconfig.h | 14 +-- bsp/stm32/stm32f103-atk-nano/.config | 8 +- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 118 +++++++++--------- bsp/stm32/stm32f103-atk-nano/rtconfig.h | 1 + bsp/stm32/stm32f103-fire-arbitrary/.config | 9 +- .../stm32f103-fire-arbitrary/board/Kconfig | 55 ++++---- bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h | 1 + bsp/stm32/stm32f407-atk-explorer/.config | 13 +- .../stm32f407-atk-explorer/board/Kconfig | 2 +- bsp/stm32/stm32f407-atk-explorer/rtconfig.h | 1 + bsp/stm32/stm32f407-st-discovery/.config | 8 +- .../stm32f407-st-discovery/board/Kconfig | 2 +- bsp/stm32/stm32f407-st-discovery/rtconfig.h | 1 + bsp/stm32/stm32f429-armfly-v6/.config | 37 ++---- bsp/stm32/stm32f429-armfly-v6/board/Kconfig | 18 ++- bsp/stm32/stm32f429-armfly-v6/rtconfig.h | 12 +- bsp/stm32/stm32f429-atk-apollo/.config | 9 +- bsp/stm32/stm32f429-atk-apollo/board/Kconfig | 2 +- bsp/stm32/stm32f429-atk-apollo/rtconfig.h | 1 + bsp/stm32/stm32f429-fire-challenger/.config | 10 +- .../stm32f429-fire-challenger/board/Kconfig | 5 +- .../stm32f429-fire-challenger/rtconfig.h | 1 + bsp/stm32/stm32f767-atk-apollo/.config | 21 ++-- bsp/stm32/stm32f767-atk-apollo/board/Kconfig | 4 +- bsp/stm32/stm32f767-atk-apollo/rtconfig.h | 1 + bsp/stm32/stm32f767-fire-challenger/.config | 13 +- .../stm32f767-fire-challenger/board/Kconfig | 4 +- .../stm32f767-fire-challenger/rtconfig.h | 1 + bsp/stm32/stm32l475-atk-pandora/.config | 8 +- bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 3 +- bsp/stm32/stm32l475-atk-pandora/rtconfig.h | 1 + 48 files changed, 396 insertions(+), 377 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32f0xx/.config b/bsp/stm32/libraries/templates/stm32f0xx/.config index 28eea196b2..95ba89c2b8 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/.config +++ b/bsp/stm32/libraries/templates/stm32f0xx/.config @@ -281,6 +281,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -295,6 +296,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -309,10 +311,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,30 +320,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F0=y @@ -361,9 +338,10 @@ CONFIG_SOC_STM32F091RC=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f0xx/board/Kconfig index 766529e3a3..2af0bda763 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/Kconfig @@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.h index bb37c4d3a2..0026ccb4a8 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.h @@ -149,19 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F0 @@ -174,6 +163,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/libraries/templates/stm32f10x/.config b/bsp/stm32/libraries/templates/stm32f10x/.config index b74dd34859..4d9fc24b34 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/.config +++ b/bsp/stm32/libraries/templates/stm32f10x/.config @@ -296,6 +296,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -310,10 +311,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -322,11 +320,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y @@ -343,9 +338,10 @@ CONFIG_SOC_STM32F103RB=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig b/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig index 39a000d371..a8a2e516f2 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig @@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h index 908c0d760d..63450a8a21 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h @@ -149,13 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F1 @@ -168,6 +163,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/libraries/templates/stm32f4xx/.config b/bsp/stm32/libraries/templates/stm32f4xx/.config index ed06540dab..973b093b5b 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/.config +++ b/bsp/stm32/libraries/templates/stm32f4xx/.config @@ -297,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -311,10 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -323,11 +321,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -344,9 +339,10 @@ CONFIG_SOC_STM32F407ZG=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig index 5ba6059541..a04f418b5b 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig @@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h index b8700de08d..8e6b709a8a 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h @@ -149,13 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 @@ -168,6 +163,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/libraries/templates/stm32f7xx/.config b/bsp/stm32/libraries/templates/stm32f7xx/.config index 5b2fbd74ae..a594f088db 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/.config +++ b/bsp/stm32/libraries/templates/stm32f7xx/.config @@ -297,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -311,10 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -323,11 +321,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y @@ -344,9 +339,10 @@ CONFIG_SOC_STM32F767IG=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig index 02454235c7..bfd687cbc1 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig @@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n - - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h index f1dff62d4b..50eb442ed8 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h @@ -149,13 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F7 @@ -168,6 +163,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/libraries/templates/stm32l4xx/.config b/bsp/stm32/libraries/templates/stm32l4xx/.config index 2ace5a3beb..e29aecd0c8 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/.config +++ b/bsp/stm32/libraries/templates/stm32l4xx/.config @@ -297,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -311,10 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -323,11 +321,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32L4=y @@ -344,9 +339,10 @@ CONFIG_SOC_STM32L475VE=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig index 5d0299fe3b..a06a967059 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig @@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL + menuconfig BSP_USING_UART + bool "Enable UART" default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n select RT_USING_SPI - default n + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_SPI_USING_DMA - bool "Enable SPI DMA support" - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h index 512a1832ce..6ae4a7ba8a 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h @@ -149,13 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32L4 @@ -168,6 +163,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f091-st-nucleo/.config b/bsp/stm32/stm32f091-st-nucleo/.config index 3a0dbd8dc3..0fced6c38b 100644 --- a/bsp/stm32/stm32f091-st-nucleo/.config +++ b/bsp/stm32/stm32f091-st-nucleo/.config @@ -281,6 +281,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -295,6 +296,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -309,10 +311,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,30 +320,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F0=y @@ -356,16 +333,24 @@ CONFIG_SOC_STM32F091RC=y # # Onboard Peripheral Drivers # +CONFIG_BSP_USING_USB_TO_USART=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y # CONFIG_BSP_USING_UART1 is not set CONFIG_BSP_USING_UART2=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART2_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig index 681580fdce..745a331f31 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig @@ -34,7 +34,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART2 bool "Enable UART2" diff --git a/bsp/stm32/stm32f091-st-nucleo/rtconfig.h b/bsp/stm32/stm32f091-st-nucleo/rtconfig.h index 818e2c9cef..dc6298a719 100644 --- a/bsp/stm32/stm32f091-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32f091-st-nucleo/rtconfig.h @@ -149,19 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F0 @@ -171,9 +160,12 @@ /* Onboard Peripheral Drivers */ +#define BSP_USING_USB_TO_USART + /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART2 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f103-atk-nano/.config b/bsp/stm32/stm32f103-atk-nano/.config index 7a673ceb4d..7a4eec1ff9 100644 --- a/bsp/stm32/stm32f103-atk-nano/.config +++ b/bsp/stm32/stm32f103-atk-nano/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y @@ -341,14 +343,14 @@ CONFIG_BSP_USING_USB_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index 84ef7224b6..3c49481a23 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -42,37 +42,37 @@ menu "On-chip Peripheral Drivers" default y menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART1 - bool "Enable UART1" - default y + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default n + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n - config BSP_USING_UART2 - bool "Enable UART2" - default n + config BSP_USING_UART2 + bool "Enable UART2" + default n - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART3 - bool "Enable UART3" - default n + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA - default n - endif + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif config BSP_USING_UART1 bool "Enable UART1" @@ -127,40 +127,40 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_SPI - bool "Enable SPI BUS" - default n - select RT_USING_SPI - if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - default n + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n - config BSP_SPI1_TX_USING_DMA - bool "Enable SPI1 TX DMA" - depends on BSP_USING_SPI1 - default n - - config BSP_SPI1_RX_USING_DMA - bool "Enable SPI1 RX DMA" - depends on BSP_USING_SPI1 - select BSP_SPI1_TX_USING_DMA - default n + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - default n - - config BSP_SPI2_TX_USING_DMA - bool "Enable SPI2 TX DMA" - depends on BSP_USING_SPI2 - default n - - config BSP_SPI2_RX_USING_DMA - bool "Enable SPI2 RX DMA" - depends on BSP_USING_SPI2 - select BSP_SPI2_TX_USING_DMA - default n - endif + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" diff --git a/bsp/stm32/stm32f103-atk-nano/rtconfig.h b/bsp/stm32/stm32f103-atk-nano/rtconfig.h index 8bae9ebc30..816034b45d 100644 --- a/bsp/stm32/stm32f103-atk-nano/rtconfig.h +++ b/bsp/stm32/stm32f103-atk-nano/rtconfig.h @@ -166,6 +166,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f103-fire-arbitrary/.config b/bsp/stm32/stm32f103-fire-arbitrary/.config index 81ee04aba5..0938feaf7e 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/.config +++ b/bsp/stm32/stm32f103-fire-arbitrary/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y @@ -345,14 +347,13 @@ CONFIG_BSP_USING_USB_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig index 2795400969..983ce4bb86 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig @@ -54,7 +54,6 @@ menu "Onboard Peripheral Drivers" select WIZNET_DEVICE_EXTERN_CONFIG select BSP_USING_SPI2 if BSP_USING_ETH - if WIZNET_DEVICE_EXTERN_CONFIG config WIZ_SPI_DEVICE string @@ -92,37 +91,37 @@ menu "On-chip Peripheral Drivers" default y menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART1 - bool "Enable UART1" - default y + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default n + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n - config BSP_USING_UART2 - bool "Enable UART2" - default n + config BSP_USING_UART2 + bool "Enable UART2" + default n - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART3 - bool "Enable UART3" - default n + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA - default n - endif + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" diff --git a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h index b26cc15cae..5a2ac1c53c 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h @@ -167,6 +167,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f407-atk-explorer/.config b/bsp/stm32/stm32f407-atk-explorer/.config index 8bb6510a75..177d468704 100644 --- a/bsp/stm32/stm32f407-atk-explorer/.config +++ b/bsp/stm32/stm32f407-atk-explorer/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -333,8 +335,9 @@ CONFIG_SOC_STM32F407ZG=y # Onboard Peripheral Drivers # CONFIG_BSP_USING_USB_TO_USART=y -# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_COM2 is not set # CONFIG_BSP_USING_COM3 is not set +# CONFIG_BSP_USING_SPI_FLASH is not set # CONFIG_BSP_USING_EEPROM is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_MPU6050 is not set @@ -344,16 +347,14 @@ CONFIG_BSP_USING_USB_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index 41ce192f9e..66d7cf8d0f 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -81,7 +81,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART3 bool "Enable UART3" diff --git a/bsp/stm32/stm32f407-atk-explorer/rtconfig.h b/bsp/stm32/stm32f407-atk-explorer/rtconfig.h index e628397b54..d35ad8f997 100644 --- a/bsp/stm32/stm32f407-atk-explorer/rtconfig.h +++ b/bsp/stm32/stm32f407-atk-explorer/rtconfig.h @@ -165,6 +165,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f407-st-discovery/.config b/bsp/stm32/stm32f407-st-discovery/.config index 0755a2d357..855a959166 100644 --- a/bsp/stm32/stm32f407-st-discovery/.config +++ b/bsp/stm32/stm32f407-st-discovery/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -337,10 +339,10 @@ CONFIG_SOC_STM32F407VG=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/bsp/stm32/stm32f407-st-discovery/board/Kconfig b/bsp/stm32/stm32f407-st-discovery/board/Kconfig index 1f5bcd321d..cdb1f1ff48 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32f407-st-discovery/board/Kconfig @@ -28,7 +28,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n endif menuconfig BSP_USING_SPI diff --git a/bsp/stm32/stm32f407-st-discovery/rtconfig.h b/bsp/stm32/stm32f407-st-discovery/rtconfig.h index a7d941bd2b..41e6ddedbd 100644 --- a/bsp/stm32/stm32f407-st-discovery/rtconfig.h +++ b/bsp/stm32/stm32f407-st-discovery/rtconfig.h @@ -163,6 +163,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f429-armfly-v6/.config b/bsp/stm32/stm32f429-armfly-v6/.config index 8615848ef0..e3045b305e 100644 --- a/bsp/stm32/stm32f429-armfly-v6/.config +++ b/bsp/stm32/stm32f429-armfly-v6/.config @@ -282,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -296,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -310,10 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -322,30 +321,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -369,11 +346,11 @@ CONFIG_BSP_USING_EXT_FMC_IO=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig index 498495e8d9..ae6e2de2fd 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig +++ b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig @@ -39,11 +39,23 @@ menu "Onboard Peripheral Drivers" config PHY_USING_DM9161CEP bool - config BSP_USING_ETH + + + menuconfig BSP_USING_ETH bool "Enable Ethernet" - default n select RT_USING_LWIP select PHY_USING_DM9161CEP + default n + if BSP_USING_ETH + config PHY_USING_INTERRUPT_MODE + bool "enable phy interrupt mode" + select PHY_INT_PIN + default n + + config PHY_INT_PIN + int + default 118 + endif config BSP_USING_MPU6050 bool "Enable MPU6050(i2c1)" @@ -74,7 +86,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n endif config BSP_USING_ON_CHIP_FLASH diff --git a/bsp/stm32/stm32f429-armfly-v6/rtconfig.h b/bsp/stm32/stm32f429-armfly-v6/rtconfig.h index 11ecaf3496..eb2f4e408c 100644 --- a/bsp/stm32/stm32f429-armfly-v6/rtconfig.h +++ b/bsp/stm32/stm32f429-armfly-v6/rtconfig.h @@ -150,19 +150,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 @@ -178,6 +167,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f429-atk-apollo/.config b/bsp/stm32/stm32f429-atk-apollo/.config index e382919ed4..90c7572d90 100644 --- a/bsp/stm32/stm32f429-atk-apollo/.config +++ b/bsp/stm32/stm32f429-atk-apollo/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -345,14 +347,13 @@ CONFIG_BSP_USING_USB_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPI5 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index c8529ead4f..916e0844a4 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -81,7 +81,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART2 bool "Enable UART2" diff --git a/bsp/stm32/stm32f429-atk-apollo/rtconfig.h b/bsp/stm32/stm32f429-atk-apollo/rtconfig.h index f3f451258a..bcf153da33 100644 --- a/bsp/stm32/stm32f429-atk-apollo/rtconfig.h +++ b/bsp/stm32/stm32f429-atk-apollo/rtconfig.h @@ -165,6 +165,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f429-fire-challenger/.config b/bsp/stm32/stm32f429-fire-challenger/.config index 81eb948fb4..c12660c8fe 100644 --- a/bsp/stm32/stm32f429-fire-challenger/.config +++ b/bsp/stm32/stm32f429-fire-challenger/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -346,14 +348,12 @@ CONFIG_BSP_USING_USB_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPI5 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ADC is not set diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig index 2c8d3f10cf..252f188c27 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig @@ -15,7 +15,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_RS232 bool "Enable RS232" - select BSP_USING_UART + select BSP_USING_UART select BSP_USING_UART2 default n @@ -91,7 +91,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART2 bool "Enable UART2" @@ -101,7 +101,6 @@ menu "On-chip Peripheral Drivers" bool "Enable UART2 RX DMA" depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA default n - endif config BSP_USING_ON_CHIP_FLASH diff --git a/bsp/stm32/stm32f429-fire-challenger/rtconfig.h b/bsp/stm32/stm32f429-fire-challenger/rtconfig.h index 83dbf4c0d3..7e366cf856 100644 --- a/bsp/stm32/stm32f429-fire-challenger/rtconfig.h +++ b/bsp/stm32/stm32f429-fire-challenger/rtconfig.h @@ -166,6 +166,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f767-atk-apollo/.config b/bsp/stm32/stm32f767-atk-apollo/.config index 0e7b661c84..46bbff3a82 100644 --- a/bsp/stm32/stm32f767-atk-apollo/.config +++ b/bsp/stm32/stm32f767-atk-apollo/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y @@ -336,28 +338,31 @@ CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_RS232 is not set # CONFIG_BSP_USING_SDRAM is not set # CONFIG_BSP_USING_QSPI_FLASH is not set -# CONFIG_BSP_USING_MPU6050 is not set +# CONFIG_BSP_USING_MPU9250 is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_POT is not set +# CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPI5 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_QSPI_USING_DMA is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_I2C2 is not set -# CONFIG_BSP_USING_I2C3 is not set -# CONFIG_BSP_USING_I2C4 is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index e87dbd896a..7d1273b33f 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -81,7 +81,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART2 bool "Enable UART2" @@ -98,7 +98,7 @@ menu "On-chip Peripheral Drivers" bool "Enable on-chip FLASH" default n -menuconfig BSP_USING_SPI + menuconfig BSP_USING_SPI bool "Enable SPI BUS" default n select RT_USING_SPI diff --git a/bsp/stm32/stm32f767-atk-apollo/rtconfig.h b/bsp/stm32/stm32f767-atk-apollo/rtconfig.h index 7623c3fda4..23599ade59 100644 --- a/bsp/stm32/stm32f767-atk-apollo/rtconfig.h +++ b/bsp/stm32/stm32f767-atk-apollo/rtconfig.h @@ -165,6 +165,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f767-fire-challenger/.config b/bsp/stm32/stm32f767-fire-challenger/.config index 90f3a7719a..7d506e7350 100644 --- a/bsp/stm32/stm32f767-fire-challenger/.config +++ b/bsp/stm32/stm32f767-fire-challenger/.config @@ -181,6 +181,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS @@ -311,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -320,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F7=y @@ -341,21 +344,15 @@ CONFIG_BSP_USING_USB_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPI5 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_QSPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_I2C1 is not set -# CONFIG_BSP_USING_I2C2 is not set -# CONFIG_BSP_USING_I2C3 is not set -# CONFIG_BSP_USING_I2C4 is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set diff --git a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig index 2423430d38..707a0a4746 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig @@ -57,7 +57,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART2 bool "Enable UART2" @@ -74,7 +74,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART3_RX_USING_DMA bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 && RT_SERIsAL_USING_DMA + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n endif diff --git a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h index d001b714a7..16f05af945 100644 --- a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h +++ b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h @@ -165,6 +165,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32l475-atk-pandora/.config b/bsp/stm32/stm32l475-atk-pandora/.config index 5212663f43..630083f09c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/.config +++ b/bsp/stm32/stm32l475-atk-pandora/.config @@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32L4=y @@ -340,12 +342,12 @@ CONFIG_BSP_USING_STLINK_TO_USART=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_QSPI is not set # CONFIG_BSP_QSPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index 538cf8d472..0ec5631f1a 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -24,7 +24,6 @@ menu "Onboard Peripheral Drivers" bool "Enable SDCARD (spi1)" select BSP_USING_SPI select BSP_USING_SPI1 - select BSP_SPI_USING_DMA select RT_USING_SPI_MSD select RT_USING_DFS select RT_USING_DFS_ELMFAT @@ -51,7 +50,7 @@ menu "On-chip Peripheral Drivers" config BSP_UART1_RX_USING_DMA bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default y + default n config BSP_USING_UART2 bool "Enable UART2" diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.h b/bsp/stm32/stm32l475-atk-pandora/rtconfig.h index 82891ef0a0..f138878738 100644 --- a/bsp/stm32/stm32l475-atk-pandora/rtconfig.h +++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.h @@ -165,6 +165,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART #define BSP_USING_UART1 /* Board extended module Drivers */ From bad889140b9ec4a6bb6a57529a4af7f4d257ea4c Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:10:04 +0800 Subject: [PATCH 08/15] [bsp][stm32] fix bug in f7 bsp template --- .../libraries/templates/stm32f7xx/SConstruct | 2 +- .../templates/stm32f7xx/project.uvoptx | 1367 ++++++++++++++++- .../templates/stm32f7xx/project.uvprojx | 342 +---- .../templates/stm32f7xx/template.uvoptx | 10 +- .../templates/stm32f7xx/template.uvprojx | 44 +- 5 files changed, 1462 insertions(+), 303 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32f7xx/SConstruct b/bsp/stm32/libraries/templates/stm32f7xx/SConstruct index f9b3d33a62..51333e0a9c 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/SConstruct +++ b/bsp/stm32/libraries/templates/stm32f7xx/SConstruct @@ -38,7 +38,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) SDK_ROOT = os.path.abspath('./') # include drivers -objs.extend(SConscript(os.path.dirname(SDK_ROOT) + '/libraries/STM32F4xx_HAL/SConscript')) +objs.extend(SConscript(os.path.dirname(SDK_ROOT) + '/libraries/STM32F7xx_HAL/SConscript')) # include libraries objs.extend(SConscript(os.path.dirname(SDK_ROOT) + '/libraries/HAL_Drivers/SConscript')) diff --git a/bsp/stm32/libraries/templates/stm32f7xx/project.uvoptx b/bsp/stm32/libraries/templates/stm32f7xx/project.uvoptx index f8c4606a9e..3287c02122 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/project.uvoptx +++ b/bsp/stm32/libraries/templates/stm32f7xx/project.uvoptx @@ -119,13 +119,13 @@ 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20020000 -FF0STM32F7x_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM) 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM) @@ -173,6 +173,7 @@ 1 + 0 0 2 10000000 @@ -181,11 +182,1367 @@ - Source Group 1 + Applications 0 0 0 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + stm32f4xx_hal_msp.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + startup_stm32f407xx.s + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + CORTEX-M4 + 0 + 0 + 0 + 0 + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + 4 + 23 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\symbol.c + symbol.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 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..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + stm32f4xx_hal_smartcard.c + 0 + 0 + + + 7 + 98 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + stm32f4xx_hal_spdifrx.c + 0 + 0 + + + 7 + 99 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + stm32f4xx_hal_spi.c + 0 + 0 + + + 7 + 100 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + stm32f4xx_hal_sram.c + 0 + 0 + + + 7 + 101 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + stm32f4xx_hal_tim.c + 0 + 0 + + + 7 + 102 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + stm32f4xx_hal_tim_ex.c + 0 + 0 + + + 7 + 103 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + stm32f4xx_hal_uart.c + 0 + 0 + + + 7 + 104 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + stm32f4xx_hal_usart.c + 0 + 0 + + + 7 + 105 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + stm32f4xx_hal_wwdg.c + 0 + 0 + + + 7 + 106 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + stm32f4xx_ll_fmc.c + 0 + 0 + + + 7 + 107 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + stm32f4xx_ll_fsmc.c + 0 + 0 + + + 7 + 108 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + stm32f4xx_ll_sdmmc.c + 0 + 0 + + + 7 + 109 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + stm32f4xx_ll_usb.c + 0 + 0 + diff --git a/bsp/stm32/libraries/templates/stm32f7xx/project.uvprojx b/bsp/stm32/libraries/templates/stm32f7xx/project.uvprojx index 88c46860e7..ffd8f012ec 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/project.uvprojx +++ b/bsp/stm32/libraries/templates/stm32f7xx/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread @@ -11,33 +14,33 @@ 0 - STM32F407ZGTx + STM32F767BGTx STMicroelectronics - Keil.STM32F4xx_DFP.2.11.0 + Keil.STM32F7xx_DFP.2.9.0 http://www.keil.com/pack - IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM)) 0 - $$Device:STM32F407ZGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - - - - $$Device:STM32F407ZGTx$CMSIS\SVD\STM32F40x.svd + $$Device:STM32F767BGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F767BGTx$CMSIS\SVD\STM32F7x7_v1r2.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,19 +104,19 @@ 0 0 3 - - + + 1 SARMCM3.DLL -REMAP -MPU DCM.DLL - -pCM4 + -pCM7 SARMCM3.DLL -MPU TCM.DLL - -pCM4 + -pCM7 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - "" () - - - - + + + + + 0 @@ -171,8 +174,8 @@ 1 0 0 - "Cortex-M4" - + "Cortex-M7" + 0 0 0 @@ -180,15 +183,16 @@ 1 0 0 - 2 + 3 + 0 1 - 0 + 1 8 0 0 0 0 - 3 + 4 4 0 0 @@ -205,7 +209,7 @@ 0 0 0 - 0 + 1 1 @@ -240,8 +244,8 @@ 0 - 0x20000000 - 0x20000 + 0x20020000 + 0x60000 1 @@ -275,8 +279,8 @@ 1 - 0x0 - 0x0 + 0x200000 + 0x100000 0 @@ -295,16 +299,16 @@ 0 - 0x20000000 - 0x20000 + 0x20020000 + 0x60000 0 - 0x10000000 - 0x10000 + 0x20000000 + 0x20000 - + 1 @@ -331,9 +335,9 @@ 0 0 - + USE_HAL_DRIVER, STM32F407xx - + applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include @@ -349,10 +353,10 @@ 0 0 - - - - + + + + @@ -364,13 +368,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + @@ -393,36 +397,26 @@ 1 board\board.c - - stm32f4xx_hal_msp.c 1 board\CubeMX_Config\Src\stm32f4xx_hal_msp.c - - startup_stm32f407xx.s 2 ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c - - drv_usart.c 1 ..\libraries\HAL_Drivers\drv_usart.c - - drv_common.c 1 @@ -438,92 +432,66 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - signal.c 1 ..\..\..\src\signal.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -539,29 +507,21 @@ 1 ..\..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 @@ -577,57 +537,41 @@ 1 ..\..\..\components\drivers\misc\pin.c - - serial.c 1 ..\..\..\components\drivers\serial\serial.c - - completion.c 1 ..\..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\src\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 @@ -643,36 +587,26 @@ 1 ..\..\..\components\finsh\shell.c - - symbol.c 1 ..\..\..\components\finsh\symbol.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_cmd.c 1 ..\..\..\components\finsh\msh_cmd.c - - msh_file.c 1 @@ -688,470 +622,336 @@ 1 ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - - stm32f4xx_hal.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - - stm32f4xx_hal_adc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c - - stm32f4xx_hal_adc_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c - - stm32f4xx_hal_can.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c - - stm32f4xx_hal_cec.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c - - stm32f4xx_hal_cortex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - - stm32f4xx_hal_crc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - - stm32f4xx_hal_cryp.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c - - stm32f4xx_hal_cryp_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c - - stm32f4xx_hal_dac.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c - - stm32f4xx_hal_dac_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c - - stm32f4xx_hal_dcmi.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c - - stm32f4xx_hal_dcmi_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c - - stm32f4xx_hal_dfsdm.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c - - stm32f4xx_hal_dma.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - - stm32f4xx_hal_dma2d.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c - - stm32f4xx_hal_dma_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - - stm32f4xx_hal_dsi.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c - - stm32f4xx_hal_eth.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c - - stm32f4xx_hal_flash.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c - - stm32f4xx_hal_flash_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c - - stm32f4xx_hal_flash_ramfunc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c - - stm32f4xx_hal_fmpi2c.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c - - stm32f4xx_hal_fmpi2c_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c - - stm32f4xx_hal_gpio.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - - stm32f4xx_hal_hash.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c - - stm32f4xx_hal_hash_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c - - stm32f4xx_hal_hcd.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c - - stm32f4xx_hal_i2c.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c - - stm32f4xx_hal_i2c_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c - - stm32f4xx_hal_i2s.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c - - stm32f4xx_hal_i2s_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c - - stm32f4xx_hal_irda.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c - - stm32f4xx_hal_iwdg.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c - - stm32f4xx_hal_lptim.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c - - stm32f4xx_hal_ltdc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c - - stm32f4xx_hal_ltdc_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c - - stm32f4xx_hal_nand.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c - - stm32f4xx_hal_nor.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c - - stm32f4xx_hal_pccard.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c - - stm32f4xx_hal_pcd.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c - - stm32f4xx_hal_pcd_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c - - stm32f4xx_hal_pwr.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - - stm32f4xx_hal_pwr_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - - stm32f4xx_hal_qspi.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c - - stm32f4xx_hal_rcc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - - stm32f4xx_hal_rcc_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - - stm32f4xx_hal_rng.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c - - stm32f4xx_hal_rtc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c - - stm32f4xx_hal_rtc_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c - - stm32f4xx_hal_sai.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c - - stm32f4xx_hal_sai_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c - - stm32f4xx_hal_sd.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c - - stm32f4xx_hal_sdram.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c - - stm32f4xx_hal_smartcard.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c - - stm32f4xx_hal_spdifrx.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c - - stm32f4xx_hal_spi.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c - - stm32f4xx_hal_sram.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c - - stm32f4xx_hal_tim.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c - - stm32f4xx_hal_tim_ex.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c - - stm32f4xx_hal_uart.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - - stm32f4xx_hal_usart.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c - - stm32f4xx_hal_wwdg.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c - - stm32f4xx_ll_fmc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c - - stm32f4xx_ll_fsmc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c - - stm32f4xx_ll_sdmmc.c 1 ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c - - stm32f4xx_ll_usb.c 1 @@ -1162,9 +962,11 @@ + - - - + + + + diff --git a/bsp/stm32/libraries/templates/stm32f7xx/template.uvoptx b/bsp/stm32/libraries/templates/stm32f7xx/template.uvoptx index 84efc74877..79e4edc632 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/template.uvoptx +++ b/bsp/stm32/libraries/templates/stm32f7xx/template.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 3 + 4 @@ -119,13 +119,13 @@ 0 - JL2CM3 - -U59400616 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20020000 -FF0STM32F7x_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM) 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + JL2CM3 + -U59400616 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM) diff --git a/bsp/stm32/libraries/templates/stm32f7xx/template.uvprojx b/bsp/stm32/libraries/templates/stm32f7xx/template.uvprojx index af223abacc..a196f74381 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/template.uvprojx +++ b/bsp/stm32/libraries/templates/stm32f7xx/template.uvprojx @@ -14,16 +14,16 @@ 0 - STM32F407ZGTx + STM32F767BGTx STMicroelectronics - Keil.STM32F4xx_DFP.2.13.0 + Keil.STM32F7xx_DFP.2.9.0 http://www.keil.com/pack - IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM)) 0 - $$Device:STM32F407ZGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + $$Device:STM32F767BGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h @@ -33,7 +33,7 @@ - $$Device:STM32F407ZGTx$CMSIS\SVD\STM32F40x.svd + $$Device:STM32F767BGTx$CMSIS\SVD\STM32F7x7_v1r2.svd 0 0 @@ -112,11 +112,11 @@ SARMCM3.DLL -REMAP -MPU DCM.DLL - -pCM4 + -pCM7 SARMCM3.DLL -MPU TCM.DLL - -pCM4 + -pCM7 @@ -138,7 +138,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -174,7 +174,7 @@ 1 0 0 - "Cortex-M4" + "Cortex-M7" 0 0 @@ -183,16 +183,16 @@ 1 0 0 - 2 + 3 0 1 - 0 + 1 8 0 0 0 0 - 3 + 4 4 0 0 @@ -209,7 +209,7 @@ 0 0 0 - 0 + 1 1 @@ -244,8 +244,8 @@ 0 - 0x20000000 - 0x20000 + 0x20020000 + 0x60000 1 @@ -279,8 +279,8 @@ 1 - 0x0 - 0x0 + 0x200000 + 0x100000 0 @@ -299,13 +299,13 @@ 0 - 0x20000000 - 0x20000 + 0x20020000 + 0x60000 0 - 0x10000000 - 0x10000 + 0x20000000 + 0x20000 From f1004b013d3b803d0fc4611cd6484c337f1448e1 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:15:49 +0800 Subject: [PATCH 09/15] [bsp][stm32] update stm32/stm32f103-atk-nano --- bsp/stm32/stm32f103-atk-nano/project.uvoptx | 12 +- bsp/stm32/stm32f103-atk-nano/project.uvprojx | 195 +++++-------------- 2 files changed, 56 insertions(+), 151 deletions(-) diff --git a/bsp/stm32/stm32f103-atk-nano/project.uvoptx b/bsp/stm32/stm32f103-atk-nano/project.uvoptx index cfd9c2865b..eba66b79a0 100644 --- a/bsp/stm32/stm32f103-atk-nano/project.uvoptx +++ b/bsp/stm32/stm32f103-atk-nano/project.uvoptx @@ -187,7 +187,7 @@ Applications - 0 + 1 0 0 0 @@ -207,7 +207,7 @@ Drivers - 0 + 1 0 0 0 @@ -287,7 +287,7 @@ Kernel - 0 + 1 0 0 0 @@ -487,7 +487,7 @@ CORTEX-M3 - 0 + 1 0 0 0 @@ -555,7 +555,7 @@ DeviceDrivers - 0 + 1 0 0 0 @@ -671,7 +671,7 @@ finsh - 0 + 1 0 0 0 diff --git a/bsp/stm32/stm32f103-atk-nano/project.uvprojx b/bsp/stm32/stm32f103-atk-nano/project.uvprojx index af0b59df29..4d626125a2 100644 --- a/bsp/stm32/stm32f103-atk-nano/project.uvprojx +++ b/bsp/stm32/stm32f103-atk-nano/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread @@ -16,28 +19,28 @@ Keil.STM32F1xx_DFP.2.2.0 http://www.keil.com/pack/ IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) 0 $$Device:STM32F103RB$Device\Include\stm32f10x.h - - - - - - - - - + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -111,7 +114,7 @@ DCM.DLL -pCM3 SARMCM3.DLL - + TCM.DLL -pCM3 @@ -136,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -304,7 +307,7 @@ 0x0 - + 1 @@ -331,9 +334,9 @@ 0 0 - + STM32F103xB, USE_HAL_DRIVER - + applications;.;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include @@ -349,10 +352,10 @@ 0 0 - - - - + + + + @@ -364,13 +367,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + @@ -393,36 +396,26 @@ 1 board\board.c - - stm32f1xx_hal_msp.c 1 board\CubeMX_Config\Src\stm32f1xx_hal_msp.c - - startup_stm32f103xb.s 2 ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xb.s - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c - - drv_usart.c 1 ..\libraries\HAL_Drivers\drv_usart.c - - drv_common.c 1 @@ -438,106 +431,76 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - cpu.c 1 ..\..\..\src\cpu.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - memheap.c 1 ..\..\..\src\memheap.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - signal.c 1 ..\..\..\src\signal.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -553,29 +516,21 @@ 1 ..\..\..\libcpu\arm\cortex-m3\cpuport.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - - backtrace.c 1 ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 @@ -591,57 +546,41 @@ 1 ..\..\..\components\drivers\misc\pin.c - - serial.c 1 ..\..\..\components\drivers\serial\serial.c - - completion.c 1 ..\..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\src\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 @@ -657,36 +596,26 @@ 1 ..\..\..\components\finsh\shell.c - - symbol.c 1 ..\..\..\components\finsh\symbol.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_cmd.c 1 ..\..\..\components\finsh\msh_cmd.c - - msh_file.c 1 @@ -702,92 +631,66 @@ 1 ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c - - stm32f1xx_hal_dma.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c - - stm32f1xx_hal_cortex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c - - stm32f1xx_hal_crc.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_crc.c - - stm32f1xx_hal_pwr.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c - - stm32f1xx_hal_rcc.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c - - stm32f1xx_hal_rcc_ex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c - - stm32f1xx_hal.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c - - stm32f1xx_hal_cec.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c - - stm32f1xx_hal_sram.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c - - stm32f1xx_hal_gpio.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c - - stm32f1xx_hal_gpio_ex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c - - stm32f1xx_hal_uart.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c - - stm32f1xx_hal_usart.c 1 @@ -798,9 +701,11 @@ + - - - + + + + From fd396975a8f925c292a54801d11287ee0a735a62 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:19:49 +0800 Subject: [PATCH 10/15] [bsp][stm32] add stm32/stm32f411-st-nucleo bsp --- bsp/stm32/stm32f411-st-nucleo/.config | 346 ++ bsp/stm32/stm32f411-st-nucleo/.gitignore | 42 + bsp/stm32/stm32f411-st-nucleo/Kconfig | 21 + bsp/stm32/stm32f411-st-nucleo/README.md | 105 + bsp/stm32/stm32f411-st-nucleo/SConscript | 14 + bsp/stm32/stm32f411-st-nucleo/SConstruct | 58 + .../applications/SConscript | 12 + .../stm32f411-st-nucleo/applications/main.c | 33 + .../board/CubeMX_Config/.mxproject | 17 + .../board/CubeMX_Config/CubeMX_Config.ioc | 155 + .../board/CubeMX_Config/Inc/main.h | 101 + .../CubeMX_Config/Inc/stm32f4xx_hal_conf.h | 451 +++ .../board/CubeMX_Config/Inc/stm32f4xx_it.h | 84 + .../board/CubeMX_Config/Src/main.c | 269 ++ .../CubeMX_Config/Src/stm32f4xx_hal_msp.c | 174 + .../board/CubeMX_Config/Src/stm32f4xx_it.c | 217 ++ .../CubeMX_Config/Src/system_stm32f4xx.c | 761 +++++ bsp/stm32/stm32f411-st-nucleo/board/Kconfig | 44 + .../stm32f411-st-nucleo/board/SConscript | 37 + bsp/stm32/stm32f411-st-nucleo/board/board.c | 50 + bsp/stm32/stm32f411-st-nucleo/board/board.h | 41 + .../board/linker_scripts/link.icf | 28 + .../board/linker_scripts/link.lds | 144 + .../board/linker_scripts/link.sct | 15 + .../stm32f411-st-nucleo/figures/board.png | Bin 0 -> 451390 bytes bsp/stm32/stm32f411-st-nucleo/project.ewd | 2834 +++++++++++++++++ bsp/stm32/stm32f411-st-nucleo/project.ewp | 2261 +++++++++++++ bsp/stm32/stm32f411-st-nucleo/project.eww | 10 + bsp/stm32/stm32f411-st-nucleo/project.uvopt | 162 + bsp/stm32/stm32f411-st-nucleo/project.uvoptx | 947 ++++++ bsp/stm32/stm32f411-st-nucleo/project.uvprojx | 720 +++++ bsp/stm32/stm32f411-st-nucleo/rtconfig.h | 171 + bsp/stm32/stm32f411-st-nucleo/rtconfig.py | 134 + bsp/stm32/stm32f411-st-nucleo/template.ewp | 2032 ++++++++++++ bsp/stm32/stm32f411-st-nucleo/template.eww | 10 + bsp/stm32/stm32f411-st-nucleo/template.uvopt | 162 + bsp/stm32/stm32f411-st-nucleo/template.uvoptx | 191 ++ .../stm32f411-st-nucleo/template.uvprojx | 393 +++ 38 files changed, 13246 insertions(+) create mode 100644 bsp/stm32/stm32f411-st-nucleo/.config create mode 100644 bsp/stm32/stm32f411-st-nucleo/.gitignore create mode 100644 bsp/stm32/stm32f411-st-nucleo/Kconfig create mode 100644 bsp/stm32/stm32f411-st-nucleo/README.md create mode 100644 bsp/stm32/stm32f411-st-nucleo/SConscript create mode 100644 bsp/stm32/stm32f411-st-nucleo/SConstruct create mode 100644 bsp/stm32/stm32f411-st-nucleo/applications/SConscript create mode 100644 bsp/stm32/stm32f411-st-nucleo/applications/main.c create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/.mxproject create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/main.h create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_it.h create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/main.c create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_it.c create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/system_stm32f4xx.c create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/Kconfig create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/SConscript create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/board.c create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/board.h create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds create mode 100644 bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.sct create mode 100644 bsp/stm32/stm32f411-st-nucleo/figures/board.png create mode 100644 bsp/stm32/stm32f411-st-nucleo/project.ewd create mode 100644 bsp/stm32/stm32f411-st-nucleo/project.ewp create mode 100644 bsp/stm32/stm32f411-st-nucleo/project.eww create mode 100644 bsp/stm32/stm32f411-st-nucleo/project.uvopt create mode 100644 bsp/stm32/stm32f411-st-nucleo/project.uvoptx create mode 100644 bsp/stm32/stm32f411-st-nucleo/project.uvprojx create mode 100644 bsp/stm32/stm32f411-st-nucleo/rtconfig.h create mode 100644 bsp/stm32/stm32f411-st-nucleo/rtconfig.py create mode 100644 bsp/stm32/stm32f411-st-nucleo/template.ewp create mode 100644 bsp/stm32/stm32f411-st-nucleo/template.eww create mode 100644 bsp/stm32/stm32f411-st-nucleo/template.uvopt create mode 100644 bsp/stm32/stm32f411-st-nucleo/template.uvoptx create mode 100644 bsp/stm32/stm32f411-st-nucleo/template.uvprojx diff --git a/bsp/stm32/stm32f411-st-nucleo/.config b/bsp/stm32/stm32f411-st-nucleo/.config new file mode 100644 index 0000000000..ca166c9644 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/.config @@ -0,0 +1,346 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x40000 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F411RE=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f411-st-nucleo/.gitignore b/bsp/stm32/stm32f411-st-nucleo/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f411-st-nucleo/Kconfig b/bsp/stm32/stm32f411-st-nucleo/Kconfig new file mode 100644 index 0000000000..d174bcc585 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f411-st-nucleo/README.md b/bsp/stm32/stm32f411-st-nucleo/README.md new file mode 100644 index 0000000000..ec84e51601 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/README.md @@ -0,0 +1,105 @@ +# STM32F411-Nucleo-64 开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 STM32F411-Nucleo-64 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +探索者 STM32F411-Nucleo-64 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F411RE 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 ** 板载资源 ** 如下： + +- MCU：STM32F407ZGT6，主频 100MHz，512KB FLASH ，128KB RAM。 +- 常用外设 + - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 + - 按键，2 个，USER and RESET 。 +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口，板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考意法半导体 [STM32F411-Nucleo-64 开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f411re.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | +| UART | 支持 | UART2 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 BSP 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32 系列 BSP 外设驱动使用教程. md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [misonyo](https://github.com/misonyo) ，邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f411-st-nucleo/SConscript b/bsp/stm32/stm32f411-st-nucleo/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f411-st-nucleo/SConstruct b/bsp/stm32/stm32f411-st-nucleo/SConstruct new file mode 100644 index 0000000000..8ecf112e9c --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/SConstruct @@ -0,0 +1,58 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map rtthread.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/SConscript b/bsp/stm32/stm32f411-st-nucleo/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/main.c b/bsp/stm32/stm32f411-st-nucleo/applications/main.c new file mode 100644 index 0000000000..5e963c636d --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift change to new framework + */ + +#include +#include +#include +#include "drv_gpio.h" +/* defined the LED0 pin: PA5 */ +#define LED0_PIN GET_PIN(A, 5) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..8691bed235 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/.mxproject @@ -0,0 +1,17 @@ +[PreviousGenFiles] +HeaderPath=D:/repository/BspFramework/rt-thread/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=D:/repository/BspFramework/rt-thread/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + +[PreviousLibFiles] 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+ +[PreviousUsedIarFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; + diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..0428900030 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,155 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +KeepUserPlacement=true +Mcu.Family=STM32F4 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IP3=USART2 +Mcu.IPNb=4 +Mcu.Name=STM32F411R(C-E)Tx +Mcu.Package=LQFP64 +Mcu.Pin0=PC13-ANTI_TAMP +Mcu.Pin1=PC14-OSC32_IN +Mcu.Pin10=PB3 +Mcu.Pin11=VP_SYS_VS_Systick +Mcu.Pin2=PC15-OSC32_OUT +Mcu.Pin3=PH0 - OSC_IN +Mcu.Pin4=PH1 - OSC_OUT +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PA5 +Mcu.Pin8=PA13 +Mcu.Pin9=PA14 +Mcu.PinsNb=12 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F411RETx +MxCube.Version=5.0.0 +MxDb.Version=DB.5.0.0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true +PA13.GPIOParameters=GPIO_Label +PA13.GPIO_Label=TMS +PA13.Locked=true +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.GPIOParameters=GPIO_Label +PA14.GPIO_Label=TCK +PA14.Locked=true +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=LD2 [Green Led] +PA5.Locked=true +PA5.Signal=GPIO_Output +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=SWO +PB3.Locked=true +PB3.Signal=SYS_JTDO-SWO +PC13-ANTI_TAMP.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI +PC13-ANTI_TAMP.GPIO_Label=B1 [Blue PushButton] +PC13-ANTI_TAMP.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PC13-ANTI_TAMP.Locked=true +PC13-ANTI_TAMP.Signal=GPXTI13 +PC14-OSC32_IN.Locked=true +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Locked=true +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PCC.Checker=false +PCC.Line=STM32F411 +PCC.MCU=STM32F411R(C-E)Tx +PCC.PartNumber=STM32F411RETx +PCC.Seq0=0 +PCC.Series=STM32F4 +PCC.Temperature=25 +PCC.Vdd=null +PH0\ -\ OSC_IN.Locked=true +PH0\ -\ OSC_IN.Mode=HSE-External-Clock-Source +PH0\ -\ OSC_IN.Signal=RCC_OSC_IN +PH1\ -\ OSC_OUT.Locked=true +PH1\ -\ OSC_OUT.Mode=HSE-External-Clock-Source +PH1\ -\ OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage=..\\..\\..\\..\\..\\..\\..\\..\\board\\stm32cubefx-repo\\STM32Cube_FW_F4_V1.11.0 +ProjectManager.DefaultFWLocation=false +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F411RETx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.23.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true +RCC.48MHZClocksFreq_Value=42000000 +RCC.AHBFreq_Value=84000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV2 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=84000000 +RCC.CortexFreq_Value=84000000 +RCC.EthernetFreq_Value=84000000 +RCC.FCLKCortexFreq_Value=84000000 +RCC.FLatency-AdvancedSettings=FLASH_LATENCY_2 +RCC.FamilyName=M +RCC.HCLKFreq_Value=84000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=48000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FLatency-AdvancedSettings,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOInputMFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=84000000 +RCC.PLLCLKFreq_Value=84000000 +RCC.PLLM=4 +RCC.PLLN=84 +RCC.PLLQCLKFreq_Value=42000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RTCFreq_Value=32000 +RCC.RTCHSEDivFreq_Value=4000000 +RCC.SYSCLKFreq_VALUE=84000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=96000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOInputMFreq_Value=500000 +RCC.VCOOutputFreq_Value=168000000 +RCC.VcooutputI2S=48000000 +SH.GPXTI13.0=GPIO_EXTI13 +SH.GPXTI13.ConfNb=1 +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=NUCLEO-F411RE +boardIOC=true diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..47036898b7 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,101 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define B1_Pin GPIO_PIN_13 +#define B1_GPIO_Port GPIOC +#define LD2_Pin GPIO_PIN_5 +#define LD2_GPIO_Port GPIOA +#define TMS_Pin GPIO_PIN_13 +#define TMS_GPIO_Port GPIOA +#define TCK_Pin GPIO_PIN_14 +#define TCK_GPIO_Port GPIOA +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..15f9b6ae02 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,451 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_it.h new file mode 100644 index 0000000000..7a788c296b --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..f934319b9d --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/main.c @@ -0,0 +1,269 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART2_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 84; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : LD2_Pin */ + GPIO_InitStruct.Pin = LD2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000000..a0b3b19ee5 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,174 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ + +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_it.c new file mode 100644 index 0000000000..5973f7fddb --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -0,0 +1,217 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/system_stm32f4xx.c b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/system_stm32f4xx.c new file mode 100644 index 0000000000..14204ed5e7 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/CubeMX_Config/Src/system_stm32f4xx.c @@ -0,0 +1,761 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.4.3 + * @date 22-January-2016 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/Kconfig b/bsp/stm32/stm32f411-st-nucleo/board/Kconfig new file mode 100644 index 0000000000..1c6ee6b39b --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/Kconfig @@ -0,0 +1,44 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F411RE + bool + select SOC_SERIES_STM32F4 + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART2 + bool "Enable UART2" + default y + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f411-st-nucleo/board/SConscript b/bsp/stm32/stm32f411-st-nucleo/board/SConscript new file mode 100644 index 0000000000..19ed8a3678 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/SConscript @@ -0,0 +1,37 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f4xx_hal_msp.c +''') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f411xe.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s'] + +# STM32F405xx) || STM32F415xx) || STM32F407xx) || STM32F417xx) +# STM32F427xx) || STM32F437xx) || STM32F429xx) || STM32F439xx) +# STM32F401xC) || STM32F401xE) || STM32F410Tx) || STM32F410Cx) +# STM32F410Rx) || STM32F411xE) || STM32F446xx) || STM32F469xx) +# STM32F479xx) || STM32F412Cx) || STM32F412Rx) || STM32F412Vx) +# STM32F412Zx) || STM32F413xx) || STM32F423xx) +# You can select chips from the list above +CPPDEFINES = ['STM32F411xE'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.c b/bsp/stm32/stm32f411-st-nucleo/board/board.c new file mode 100644 index 0000000000..74579865c7 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/board.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift change to new framework + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 84; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.h b/bsp/stm32/stm32f411-st-nucleo/board/board.h new file mode 100644 index 0000000000..d3e860a5f5 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift change to new framework + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (512 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE 128 +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#endif + diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf new file mode 100644 index 0000000000..f6b6ffd23b --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds new file mode 100644 index 0000000000..4d08a6d00e --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.lds @@ -0,0 +1,144 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.sct new file mode 100644 index 0000000000..5d1e3e6c00 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U066CFF535155878281155143 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F411RETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F411RETx$CMSIS\Flash\STM32F4xx_512.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + stm32f4xx_hal_msp.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f411xe.s + startup_stm32f411xe.s + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 3 + 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1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + CORTEX-M4 + 0 + 0 + 0 + 0 + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + 4 + 24 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\symbol.c + symbol.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_cmd.c + msh_cmd.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + + + STM32_HAL + 0 + 0 + 0 + 0 + + 7 + 43 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + system_stm32f4xx.c + 0 + 0 + + + 7 + 44 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + stm32f4xx_hal.c + 0 + 0 + + + 7 + 45 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + stm32f4xx_hal_cec.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + stm32f4xx_hal_cortex.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + stm32f4xx_hal_crc.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + stm32f4xx_hal_cryp.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + stm32f4xx_hal_cryp_ex.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + stm32f4xx_hal_dma.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + stm32f4xx_hal_dma_ex.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + stm32f4xx_hal_pwr.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + stm32f4xx_hal_pwr_ex.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + stm32f4xx_hal_rcc.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + stm32f4xx_hal_rcc_ex.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + stm32f4xx_hal_rng.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + stm32f4xx_hal_gpio.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + stm32f4xx_hal_uart.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + stm32f4xx_hal_usart.c + 0 + 0 + + + + diff --git a/bsp/stm32/stm32f411-st-nucleo/project.uvprojx b/bsp/stm32/stm32f411-st-nucleo/project.uvprojx new file mode 100644 index 0000000000..735e620c46 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/project.uvprojx @@ -0,0 +1,720 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F411RETx + STMicroelectronics + Keil.STM32F4xx_DFP.2.12.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F411RETx$CMSIS\Flash\STM32F4xx_512.FLM)) + 0 + $$Device:STM32F411RETx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F411RETx$CMSIS\SVD\STM32F411xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32F411xE + + applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + startup_stm32f411xe.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f411xe.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + cpu.c + 1 + ..\..\..\src\cpu.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + STM32_HAL + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f411-st-nucleo/rtconfig.h b/bsp/stm32/stm32f411-st-nucleo/rtconfig.h new file mode 100644 index 0000000000..94d5708a91 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/rtconfig.h @@ -0,0 +1,171 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F4 + +/* Hardware Drivers Config */ + +#define SOC_STM32F411RE + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32f411-st-nucleo/rtconfig.py b/bsp/stm32/stm32f411-st-nucleo/rtconfig.py new file mode 100644 index 0000000000..4d9d4450aa --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/rtconfig.py @@ -0,0 +1,134 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99 -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/stm32/stm32f411-st-nucleo/template.ewp b/bsp/stm32/stm32f411-st-nucleo/template.ewp new file mode 100644 index 0000000000..51abb339f9 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/template.ewp @@ -0,0 +1,2032 @@ + + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f411-st-nucleo/template.eww b/bsp/stm32/stm32f411-st-nucleo/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f411-st-nucleo/template.uvopt b/bsp/stm32/stm32f411-st-nucleo/template.uvopt new file mode 100644 index 0000000000..b53d69d5df --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/template.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/stm32/stm32f411-st-nucleo/template.uvoptx b/bsp/stm32/stm32f411-st-nucleo/template.uvoptx new file mode 100644 index 0000000000..f42ac67b9d --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/template.uvoptx @@ -0,0 +1,191 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U066CFF535155878281155143 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F411RETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F411RETx$CMSIS\Flash\STM32F4xx_512.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f411-st-nucleo/template.uvprojx b/bsp/stm32/stm32f411-st-nucleo/template.uvprojx new file mode 100644 index 0000000000..cda776d330 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/template.uvprojx @@ -0,0 +1,393 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F411RETx + STMicroelectronics + Keil.STM32F4xx_DFP.2.12.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F411RETx$CMSIS\Flash\STM32F4xx_512.FLM)) + 0 + $$Device:STM32F411RETx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F411RETx$CMSIS\SVD\STM32F411xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + From f717dd5f44cbe773efcbddc8adc7ba9a07146087 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:20:23 +0800 Subject: [PATCH 11/15] [bsp][stm32] update README.md --- bsp/stm32/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index a79e692510..1021fbdf8a 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -11,6 +11,7 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/) | 野火 F103 霸道开发板 | | **F4 系列** | | | [stm32f407-st-discovery](stm32f407-st-discovery/) | ST 官方 stm32f407-discovery 开发板 | +| [stm32f411-st-nucleo](stm32f411-st-nucleo/) | ST 官方 STM32F411-Nucleo-64 开发板 | | [stm32f407-atk-explorer](stm32f407-atk-explorer/) | 正点原子 F407 探索者开发板 | | [stm32f429-atk-apollo](stm32f429-atk-apollo/) | 正点原子 F429 阿波罗开发板 | | [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 | From f39797090309101ccb5150dcadc95befb0cc2b1e Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 14:53:02 +0800 Subject: [PATCH 12/15] [bsp][stm32] add ci for stm32f411-st-nucleo bsp --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 1c16bf683d..fde8606ac3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -86,6 +86,7 @@ env: - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm' From c1ce319f930eb04b7461a7c9192dd0adbd232d4e Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 18:15:27 +0800 Subject: [PATCH 13/15] [bsp][stm32] optimize Kconfig file --- bsp/stm32/stm32f091-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig index 745a331f31..4fe2365ebc 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig @@ -9,7 +9,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart2)" - select BSP_USING_UART + select BSP_USING_UART select BSP_USING_UART2 default y diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index 0ec5631f1a..afe8fe2f5e 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -51,7 +51,7 @@ menu "On-chip Peripheral Drivers" bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA default n - + config BSP_USING_UART2 bool "Enable UART2" default n From 0032fff1d24aa06063000bdfc2ebecf5a030e0e3 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 18:15:59 +0800 Subject: [PATCH 14/15] [bsp][stm32] remove useless configuration --- .../libraries/templates/stm32l4xx/board/Kconfig | 2 +- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 15 --------------- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig index a06a967059..e16439982f 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig @@ -44,7 +44,7 @@ menu "On-chip Peripheral Drivers" bool "Enable SPI1 TX DMA" depends on BSP_USING_SPI1 default n - + config BSP_SPI1_RX_USING_DMA bool "Enable SPI1 RX DMA" depends on BSP_USING_SPI1 diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index 3c49481a23..e7873048cf 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -73,21 +73,6 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n endif - - config BSP_USING_UART1 - bool "Enable UART1" - select RT_USING_SERIAL - default y - - config BSP_USING_UART2 - bool "Enable UART2" - select RT_USING_SERIAL - default n - - config BSP_USING_UART3 - bool "Enable UART3" - select RT_USING_SERIAL - default n menuconfig BSP_USING_TIM bool "Enable timer" From 0d025a69e62895a720da602ae85397f7e50acb39 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 8 Jan 2019 18:19:11 +0800 Subject: [PATCH 15/15] [bsp][stm32] fix bug in dma config && clean up the dma config code --- .../HAL_Drivers/config/f0/dma_config.h | 37 +- .../HAL_Drivers/config/f0/uart_config.h | 12 +- .../HAL_Drivers/config/f1/dma_config.h | 46 +- .../HAL_Drivers/config/f1/uart_config.h | 24 +- .../HAL_Drivers/config/f4/dma_config.h | 374 +++++++--------- .../HAL_Drivers/config/f7/dma_config.h | 402 ++++++++---------- .../HAL_Drivers/config/l4/dma_config.h | 146 +++---- .../HAL_Drivers/config/l4/qspi_config.h | 2 +- .../HAL_Drivers/config/l4/uart_config.h | 18 +- 9 files changed, 443 insertions(+), 618 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h index a883c86fdc..1c44c20531 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-01-05 zylx first version + * 2019-01-08 SummerGift clean up the code */ #ifndef __DMA_CONFIG_H__ @@ -13,30 +14,24 @@ #include -/* dma1 channel1 */ - -/* dma1 channel1 */ - -/* dma1 channel2-3 DMA2 channel1-2 */ -#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) -#define USART1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHBENR_DMA1EN -#define USART1_RX_DMA_INSTANCE DMA1_Channel3 -#define USART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn +/* DMA1 channel1 */ +/* DMA1 channel2-3 DMA2 channel1-2 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART1_RX_DMA_INSTANCE DMA1_Channel3 +#define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn #endif -/* dma1 channel2-3 DMA2 channel1-2 */ - -/* dma1 channel4-7 DMA2 channel3-5 */ -#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) -#define USART2_DMA_RX_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler -#define USART2_RX_DMA_RCC RCC_AHBENR_DMA1EN -#define USART2_RX_DMA_INSTANCE DMA1_Channel5 -#define USART2_RX_DMA_IRQ DMA1_Ch4_7_DMA2_Ch3_5_IRQn +/* DMA1 channel2-3 DMA2 channel1-2 */ +/* DMA1 channel4-7 DMA2 channel3-5 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Channel5 +#define UART2_RX_DMA_IRQ DMA1_Ch4_7_DMA2_Ch3_5_IRQn #endif -/* dma1 channel4-7 DMA2 channel3-5 */ - - +/* DMA1 channel4-7 DMA2 channel3-5 */ #endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h index 64ad12adf4..9ef9b2ba67 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h @@ -28,9 +28,9 @@ #ifndef UART1_DMA_CONFIG #define UART1_DMA_CONFIG \ { \ - .Instance = USART1_RX_DMA_INSTANCE, \ - .dma_rcc = USART1_RX_DMA_RCC, \ - .dma_irq = USART1_RX_DMA_IRQ, \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ } #endif /* UART1_DMA_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -50,9 +50,9 @@ #ifndef UART2_DMA_CONFIG #define UART2_DMA_CONFIG \ { \ - .Instance = USART2_RX_DMA_INSTANCE, \ - .dma_rcc = USART2_RX_DMA_RCC, \ - .dma_irq = USART2_RX_DMA_IRQ, \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ } #endif /* UART2_DMA_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h index d073838d44..0b6b0550a4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-01-02 SummerGift first version + * 2019-01-08 SummerGift clean up the code */ #ifndef __DMA_CONFIG_H__ @@ -15,7 +16,7 @@ /* DMA1 channel1 */ /* DMA1 channel2 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 @@ -23,21 +24,20 @@ #endif /* DMA1 channel3 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn - -#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) -#define USART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler -#define USART3_RX_DMA_RCC RCC_AHBENR_DMA1EN -#define USART3_RX_DMA_INSTANCE DMA1_Channel3 -#define USART3_RX_DMA_IRQ DMA1_Channel3_IRQn +#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) +#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler +#define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART3_RX_DMA_INSTANCE DMA1_Channel3 +#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn #endif /* DMA1 channel4 */ -#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler #define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 @@ -45,32 +45,31 @@ #endif /* DMA1 channel5 */ -#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) -#define USART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHBENR_DMA1EN -#define USART1_RX_DMA_INSTANCE DMA1_Channel5 -#define USART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART1_RX_DMA_INSTANCE DMA1_Channel5 +#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ -#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) -#define USART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler -#define USART2_RX_DMA_RCC RCC_AHBENR_DMA1EN -#define USART2_RX_DMA_INSTANCE DMA1_Channel6 -#define USART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Channel6 +#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn #endif - /* DMA1 channel7 */ /* DMA2 channel1 */ -#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) #define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler #define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN #define SPI3_RX_DMA_INSTANCE DMA2_Channel1 @@ -78,12 +77,11 @@ #endif /* DMA2 channel2 */ -#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) #define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler #define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN #define SPI3_TX_DMA_INSTANCE DMA2_Channel2 #define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn -/* DMA1 channel4 */ #endif /* DMA2 channel3 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h index f7c5f41f9b..bdfafee744 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h @@ -30,9 +30,9 @@ #ifndef UART1_DMA_CONFIG #define UART1_DMA_CONFIG \ { \ - .Instance = USART1_RX_DMA_INSTANCE, \ - .dma_rcc = USART1_RX_DMA_RCC, \ - .dma_irq = USART1_RX_DMA_IRQ, \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ } #endif /* UART1_DMA_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -52,9 +52,9 @@ #ifndef UART2_DMA_CONFIG #define UART2_DMA_CONFIG \ { \ - .Instance = USART2_RX_DMA_INSTANCE, \ - .dma_rcc = USART2_RX_DMA_RCC, \ - .dma_irq = USART2_RX_DMA_IRQ, \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ } #endif /* UART2_DMA_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ @@ -74,9 +74,9 @@ #ifndef UART3_DMA_CONFIG #define UART3_DMA_CONFIG \ { \ - .Instance = USART3_RX_DMA_INSTANCE, \ - .dma_rcc = USART3_RX_DMA_RCC, \ - .dma_irq = USART3_RX_DMA_IRQ, \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ } #endif /* UART3_DMA_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ @@ -96,9 +96,9 @@ #ifndef UART4_DMA_CONFIG #define UART4_DMA_CONFIG \ { \ - .Instance = USART4_RX_DMA_INSTANCE, \ - .dma_rcc = USART4_RX_DMA_RCC, \ - .dma_irq = USART4_RX_DMA_IRQ, \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ } #endif /* UART4_DMA_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h index e8cec06fa7..9eb55f2b9a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-01-02 zylx first version + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code */ #ifndef __DMA_CONFIG_H__ @@ -13,255 +14,196 @@ #include -/* dma1 stream0 */ -#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) - -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 -#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn - -#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL) +/* DMA1 stream0 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn +#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) #define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART5_RX_DMA_INSTANCE DMA1_Stream0 #define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn - #endif -/* dma1 stream0 */ -/* dma1 stream1 */ -#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) +/* DMA1 stream1 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) #define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART3_RX_DMA_INSTANCE DMA1_Stream1 #define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn - #endif -/* dma1 stream1 */ -/* dma1 stream2 */ -#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) - -#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler -#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 -#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn - -#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) +/* DMA1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn +#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) #define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler #define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART4_RX_DMA_INSTANCE DMA1_Stream2 #define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn - #endif -/* dma1 stream2 */ - -/* dma1 stream3 */ -#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) - -#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler -#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 -#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn +/* DMA1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn #endif -/* dma1 stream3 */ - -/* dma1 stream4 */ -#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) - -#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler -#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 -#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +/* DMA1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn #endif -/* dma1 stream4 */ -/* dma1 stream5 */ -#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) - -#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler -#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 -#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn - -#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) +/* DMA1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn +#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) #define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART2_RX_DMA_INSTANCE DMA1_Stream5 #define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn - -#endif -/* dma1 stream5 */ - -/* dma1 stream6 */ -/* dma1 stream6 */ - -/* dma1 stream7 */ -#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) - -#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler -#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 -#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn - -#endif -/* dma1 stream7 */ - -/* dma2 stream0 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) - -#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 -#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn - -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) - -#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream0 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 -#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn - -#endif -/* dma2 stream0 */ - -/* dma2 stream1 */ -#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) - -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 -#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn - -#endif -/* dma2 stream1 */ - -/* dma2 stream2 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) - -#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 -#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn - -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) - -#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define USART1_RX_DMA_INSTANCE DMA2_Stream2 -#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn - -#endif -/* dma2 stream2 */ - -/* dma2 stream3 */ -#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 -#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 -#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn - -#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) - -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 -#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn - -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) - -#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream3 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn - -#endif -/* dma2 stream3 */ - -/* dma2 stream4 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) - -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 -#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn - -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) - -#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn - -#endif -/* dma2 stream4 */ - -/* dma2 stream5 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) - -#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler -#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 -#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn - -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) - -#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define USART1_RX_DMA_INSTANCE DMA2_Stream5 -#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn - -#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler -#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 -#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 -#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn - #endif -/* dma2 stream5 */ - -/* dma2 stream6 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) - -#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler -#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 -#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 -#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +/* DMA1 stream6 */ +/* DMA1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn #endif -/* dma2 stream6 */ -/* dma2 stream7 */ -/* dma2 stream7 */ +/* DMA2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn +#endif + +/* DMA2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#endif + +/* DMA2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE) +#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream2 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn +#endif + +/* DMA2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) + +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn +#endif + +/* DMA2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE) +#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream5 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn +#endif + +/* DMA2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +#endif + +/* DMA2 stream7 */ + #endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h index 5ff276900b..cf0c416311 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-01-02 zylx first version + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code */ #ifndef __DMA_CONFIG_H__ @@ -13,273 +14,208 @@ #include -/* dma1 stream0 */ -#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) - -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 -#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn - -#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL) +/* DMA1 stream0 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn +#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) #define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART5_RX_DMA_INSTANCE DMA1_Stream0 #define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn - #endif -/* dma1 stream0 */ -/* dma1 stream1 */ -#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) +/* DMA1 stream1 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) #define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART3_RX_DMA_INSTANCE DMA1_Stream1 #define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn - #endif -/* dma1 stream1 */ -/* dma1 stream2 */ -#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) - -#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler -#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 -#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn - -#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) +/* DMA1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn +#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) #define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler #define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART4_RX_DMA_INSTANCE DMA1_Stream2 #define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn - #endif -/* dma1 stream2 */ - -/* dma1 stream3 */ -#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) - -#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler -#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 -#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn +/* DMA1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn #endif -/* dma1 stream3 */ - -/* dma1 stream4 */ -#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) - -#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler -#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 -#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +/* DMA1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn #endif -/* dma1 stream4 */ -/* dma1 stream5 */ -#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) -#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler -#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 -#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn - -#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) +/* DMA1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn +#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) #define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART2_RX_DMA_INSTANCE DMA1_Stream5 #define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 #define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn - -#endif -/* dma1 stream5 */ - -/* dma1 stream6 */ -/* dma1 stream6 */ - -/* dma1 stream7 */ -#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) - -#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler -#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 -#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn - -#endif -/* dma1 stream7 */ - -/* dma2 stream0 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) - -#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 -#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn - -#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL) - -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 -#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn - -#endif -/* dma2 stream0 */ - -/* dma2 stream1 */ -#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) - -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 -#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn - -#endif -/* dma2 stream1 */ - -/* dma2 stream2 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) - -#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 -#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn - -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) - -#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define USART1_RX_DMA_INSTANCE DMA2_Stream2 -#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn - -#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) - -#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler -#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN -#define QSPI_DMA_INSTANCE DMA2_Stream2 -#define QSPI_DMA_CHANNEL DMA_CHANNEL_11 -#define QSPI_DMA_IRQ DMA2_Stream2_IRQn - -#endif -/* dma2 stream2 */ - -/* dma2 stream3 */ -#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 -#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 -#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn - -#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) - -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 -#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn - -#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL) - -#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_RX_DMA_INSTANCE DMA2_Stream3 -#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn - -#endif -/* dma2 stream3 */ - -/* dma2 stream4 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) - -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 -#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn - -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL) - -#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn - -#endif -/* dma2 stream4 */ - -/* dma2 stream5 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) - -#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler -#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 -#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn - -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL) - -#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define USART1_RX_DMA_INSTANCE DMA2_Stream5 -#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn - -#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL) - -#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler -#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 -#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 -#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn - #endif -/* dma2 stream5 */ - -/* dma2 stream6 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL) - -#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler -#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 -#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 -#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn - -#endif -/* dma2 stream6 */ - -/* dma2 stream7 */ -#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) - -#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler -#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN -#define QSPI_DMA_INSTANCE DMA2_Stream7 -#define QSPI_DMA_CHANNEL DMA_CHANNEL_3 -#define QSPI_DMA_IRQ DMA2_Stream7_IRQn +/* DMA1 stream6 */ +/* DMA1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn #endif -/* dma2 stream7 */ +/* DMA2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn +#endif + +/* DMA2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#endif + +/* DMA2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE) +#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream2 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn +#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream2 +#define QSPI_DMA_CHANNEL DMA_CHANNEL_11 +#define QSPI_DMA_IRQ DMA2_Stream2_IRQn +#endif + +/* DMA2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn +#endif + +/* DMA2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE) +#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define USART1_RX_DMA_INSTANCE DMA2_Stream5 +#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn +#endif + +/* DMA2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +#endif + +/* DMA2 stream7 */ +#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream7 +#define QSPI_DMA_CHANNEL DMA_CHANNEL_3 +#define QSPI_DMA_IRQ DMA2_Stream7_IRQn +#endif #endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h index 84495c2c5a..14b0246ca8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h @@ -5,7 +5,8 @@ * * Change Logs: * Date Author Notes - * 2018-01-05 zylx first version + * 2019-01-05 zylx first version + * 2019-01-08 SummerGift clean up the code */ #ifndef __DMA_CONFIG_H__ @@ -13,161 +14,114 @@ #include -/* dma1 channel1 */ - - - -/* dma1 channel1 */ - -/* dma1 channel2 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_REQUEST) +/* DMA1 channel1 */ +/* DMA1 channel2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_1 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn - #endif -/* dma1 channel2 */ - -/* dma1 channel3 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_REQUEST) +/* DMA1 channel3 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_1 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn - #endif -/* dma1 channel3 */ - -/* dma1 channel4 */ -#if defined(BSP_UART1_TX_USING_DMA) && !defined(USART1_TX_DMA_REQUEST) - -#define USART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler -#define USART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define USART1_TX_DMA_INSTANCE DMA1_Channel4 -#define USART1_TX_DMA_REQUEST DMA_REQUEST_2 -#define USART1_TX_DMA_IRQ DMA1_Channel4_IRQn +/* DMA1 channel4 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler +#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART1_TX_DMA_INSTANCE DMA1_Channel4 +#define UART1_TX_DMA_REQUEST DMA_REQUEST_2 +#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn #endif -/* dma1 channel4 */ - -/* dma1 channel5 */ -#if defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_REQUEST) - -#define USART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define USART1_RX_DMA_INSTANCE DMA1_Channel5 -#define USART1_RX_DMA_REQUEST DMA_REQUEST_2 -#define USART1_RX_DMA_IRQ DMA1_Channel5_IRQn - -#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) +/* DMA1 channel5 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART1_RX_DMA_INSTANCE DMA1_Channel5 +#define UART1_RX_DMA_REQUEST DMA_REQUEST_2 +#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) #define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler #define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN #define QSPI_DMA_INSTANCE DMA1_Channel5 -#define QSPI_DMA_CHANNEL DMA_REQUEST_5 +#define QSPI_DMA_REQUEST DMA_REQUEST_5 #define QSPI_DMA_IRQ DMA1_Channel5_IRQn - #endif -/* dma1 channel5 */ -/* dma1 channel6 */ -/* dma1 channel6 */ +/* DMA1 channel6 */ -/* dma1 channel7 */ - - - -/* dma1 channel7 */ - -/* dma2 channel1 */ -#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_REQUEST) +/* DMA1 channel7 */ +/* DMA2 channel1 */ +#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) #define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler #define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART5_TX_DMA_INSTANCE DMA2_Channel1 #define UART5_TX_DMA_REQUEST DMA_REQUEST_2 #define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn - #endif -/* dma2 channel1 */ - -/* dma2 channel2 */ -#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_REQUEST) +/* DMA2 channel2 */ +#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) #define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART5_RX_DMA_INSTANCE DMA2_Channel2 #define UART5_RX_DMA_REQUEST DMA_REQUEST_2 #define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn - #endif -/* dma2 channel2 */ - -/* dma2 channel3 */ -#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_REQUEST) +/* DMA2 channel3 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_RX_DMA_INSTANCE DMA2_Channel3 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_4 #define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn - #endif -/* dma2 channel3 */ - -/* dma2 channel4 */ -#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_REQUEST) +/* DMA2 channel4 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_TX_DMA_INSTANCE DMA2_Channel4 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_4 #define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn - #endif -/* dma2 channel4 */ -/* dma2 channel5 */ - - - -/* dma2 channel5 */ - -/* dma2 channel6 */ -#if defined(BSP_UART1_TX_USING_DMA) && !defined(USART1_TX_DMA_REQUEST) - -#define USART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler -#define USART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define USART1_TX_DMA_INSTANCE DMA2_Channel6 -#define USART1_TX_DMA_REQUEST DMA_REQUEST_2 -#define USART1_TX_DMA_IRQ DMA2_Channel6_IRQn +/* DMA2 channel5 */ +/* DMA2 channel6 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler +#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART1_TX_DMA_INSTANCE DMA2_Channel6 +#define UART1_TX_DMA_REQUEST DMA_REQUEST_2 +#define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn #endif -/* dma2 channel6 */ - -/* dma2 channel7 */ -#if defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_REQUEST) - -#define USART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler -#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define USART1_RX_DMA_INSTANCE DMA2_Channel7 -#define USART1_RX_DMA_REQUEST DMA_REQUEST_2 -#define USART1_RX_DMA_IRQ DMA2_Channel7_IRQn - -#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL) +/* DMA2 channel7 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define UART1_RX_DMA_INSTANCE DMA2_Channel7 +#define UART1_RX_DMA_REQUEST DMA_REQUEST_2 +#define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn +#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) #define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN #define QSPI_DMA_INSTANCE DMA2_Channel7 -#define QSPI_DMA_CHANNEL DMA_REQUEST_3 +#define QSPI_DMA_REQUEST DMA_REQUEST_3 #define QSPI_DMA_IRQ DMA2_Channel7_IRQn - #endif -/* dma2 channel7 */ #endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h index ae968c0cfc..d76ef6dd1d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h @@ -30,7 +30,7 @@ #define QSPI_DMA_CONFIG \ { \ .Instance = QSPI_DMA_INSTANCE, \ - .Init.Request = QSPI_DMA_CHANNEL, \ + .Init.Request = QSPI_DMA_REQUEST, \ .Init.Direction = DMA_PERIPH_TO_MEMORY, \ .Init.PeriphInc = DMA_PINC_DISABLE, \ .Init.MemInc = DMA_MINC_ENABLE, \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h index 0b27ff77c8..58644894b8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2018-11-06 SummerGift change to new framework + * 2018-11-06 SummerGift first version */ #ifndef __UART_CONFIG_H__ @@ -28,10 +28,10 @@ #ifndef UART1_DMA_CONFIG #define UART1_DMA_CONFIG \ { \ - .Instance = USART1_RX_DMA_INSTANCE, \ - .request = USART1_RX_DMA_REQUEST, \ - .dma_rcc = USART1_RX_DMA_RCC, \ - .dma_irq = USART1_RX_DMA_IRQ, \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .request = UART1_RX_DMA_REQUEST, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ } #endif /* UART1_DMA_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -51,10 +51,10 @@ #ifndef UART2_DMA_CONFIG #define UART2_DMA_CONFIG \ { \ - .Instance = USART2_RX_DMA_INSTANCE, \ - .request = USART2_RX_DMA_REQUEST, \ - .dma_rcc = USART2_RX_DMA_RCC, \ - .dma_irq = USART2_RX_DMA_IRQ, \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .request = UART2_RX_DMA_REQUEST, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ } #endif /* UART2_DMA_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */