更新gicv3中断亲和性设置，重构api: arm_gic_send_affinity_sgi, 增加AMP宏判断, rt_ioremap和宏RT_USING_SMART解耦
修改:中断安装默认绑定至当前核心， 修改rt_hw_interrupt_set_target_cpus函数,
This commit is contained in:
wangqinglin
guo
parent
a790c809a8
commit
8335c5add2
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@ -35,9 +35,8 @@
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#define ARM_SPI_BIND_CPU_ID 0
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#endif
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#ifndef RT_USING_SMP
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#if !defined(RT_USING_SMP) && !defined(RT_USING_AMP)
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#define RT_CPUS_NR 1
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extern int rt_hw_cpu_id(void);
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#else
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extern rt_uint64_t rt_cpu_mpidr_early[];
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#endif /* RT_USING_SMP */
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@ -114,6 +113,7 @@ static unsigned int _gic_max_irq;
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/* Macro to access the Generic Interrupt Controller Distributor (GICD) */
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#define GIC_DIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U)
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#define GIC_DIST_TYPE(hw_base) HWREG32((hw_base) + 0x004U)
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#define GIC_DIST_IIDR(hw_base) HWREG32((hw_base) + 0x008U)
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#define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n) / 32U) * 4U)
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#define GIC_DIST_ENABLE_SET(hw_base, n) HWREG32((hw_base) + 0x100U + ((n) / 32U) * 4U)
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#define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n) / 32U) * 4U)
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@ -335,6 +335,26 @@ void arm_gic_clear_active(rt_uint64_t index, int irq)
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GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
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}
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void arm_gic_set_router_cpu(rt_uint64_t index, int irq, rt_uint64_t aff)
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{
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 32);
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GIC_DIST_IROUTER(_gic_table[index].dist_hw_base, irq) = aff & 0xff00ffffffULL;
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}
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rt_uint64_t arm_gic_get_router_cpu(rt_uint64_t index, int irq)
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{
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 32);
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return GIC_DIST_IROUTER(_gic_table[index].dist_hw_base, irq);
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}
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/* Set up the cpu mask for the specific interrupt */
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void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask)
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{
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@ -478,76 +498,118 @@ rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq)
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return ((active << 1) | pending);
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}
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#ifdef RT_USING_SMP
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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struct gicv3_sgi_aff
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{
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rt_uint64_t aff;
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rt_uint32_t cpu_mask[(RT_CPUS_NR + 31) >> 5];
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rt_uint16_t target_list;
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};
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static struct gicv3_sgi_aff sgi_aff_table[RT_CPUS_NR];
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static rt_uint64_t sgi_aff_table_num;
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static void sgi_aff_add_table(rt_uint64_t aff, rt_uint64_t cpu_index)
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{
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rt_uint64_t i;
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for (i = 0; i < sgi_aff_table_num; i++)
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{
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if (sgi_aff_table[i].aff == aff)
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{
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sgi_aff_table[i].cpu_mask[cpu_index >> 5] |= (1 << (cpu_index & 0x1F));
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return;
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}
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}
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sgi_aff_table[sgi_aff_table_num].aff = aff;
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sgi_aff_table[sgi_aff_table_num].cpu_mask[cpu_index >> 5] |= (1 << (cpu_index & 0x1F));
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sgi_aff_table_num++;
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}
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static rt_uint64_t gicv3_sgi_init(void)
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{
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rt_uint64_t i, icc_sgi1r_value;
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for (i = 0; i < RT_CPUS_NR; i++)
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{
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icc_sgi1r_value = (rt_uint64_t)((rt_cpu_mpidr_early[i] >> 8) & 0xFF) << 16;
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icc_sgi1r_value |= (rt_uint64_t)((rt_cpu_mpidr_early[i] >> 16) & 0xFF) << 32;
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icc_sgi1r_value |= (rt_uint64_t)((rt_cpu_mpidr_early[i] >> 32) & 0xFF) << 48;
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icc_sgi1r_value |= (rt_uint64_t)((rt_cpu_mpidr_early[i] >> 4) & 0xF) << 44;
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sgi_aff_add_table(icc_sgi1r_value, i);
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}
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return (RT_CPUS_NR + 31) >> 5;
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}
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rt_inline void gicv3_sgi_send(rt_uint64_t int_id)
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{
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rt_uint64_t i;
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for (i = 0; i < sgi_aff_table_num; i++)
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{
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if (sgi_aff_table[i].target_list)
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{
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__DSB();
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/* Interrupts routed to the PEs specified by Aff3.Aff2.Aff1.<target list>. */
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SET_GICV3_REG(ICC_SGI1R_EL1, sgi_aff_table[i].aff | int_id | sgi_aff_table[i].target_list);
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__ISB();
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sgi_aff_table[i].target_list = 0;
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}
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}
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}
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rt_inline void gicv3_sgi_target_list_set(rt_uint64_t array, rt_uint32_t cpu_mask)
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{
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rt_uint64_t i, value;
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for (i = 0; i < sgi_aff_table_num; i++)
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{
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if (sgi_aff_table[i].cpu_mask[array] & cpu_mask)
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{
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while (cpu_mask)
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{
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value = __builtin_ctzl(cpu_mask);
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cpu_mask &= ~(1 << value);
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sgi_aff_table[i].target_list |= 1 << (rt_cpu_mpidr_early[(array << 5) | value] & 0xF);
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}
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}
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}
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}
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void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint32_t cpu_masks[], rt_uint64_t routing_mode)
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{
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const int cpu_mask_cpu_max_nr = sizeof(cpu_masks[0]) * 8;
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rt_uint64_t i;
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rt_uint64_t int_id = (irq & 0xf) << 24;
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rt_uint64_t irm = routing_mode << 40; /* Interrupt Routing Mode */
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static rt_uint64_t masks_nrs = 0;
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if (routing_mode == GICV3_ROUTED_TO_SPEC)
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{
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int cpu_id, cpu_mask_bit, i, cpu_masks_nr = RT_CPUS_NR / cpu_mask_cpu_max_nr;
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rt_uint16_t target_list;
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rt_uint64_t rs = 0; /* Range Selector */
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rt_uint64_t affinity_val, next_affinity_val;
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if (cpu_masks_nr * cpu_mask_cpu_max_nr != RT_CPUS_NR)
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if (!masks_nrs)
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{
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++cpu_masks_nr;
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masks_nrs = gicv3_sgi_init();
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}
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for (i = cpu_id = 0; i < cpu_masks_nr;)
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for (i = 0; i < masks_nrs; i++)
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{
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/* No cpu in this mask */
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if (cpu_masks[i] == 0)
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{
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++i;
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cpu_id += cpu_mask_cpu_max_nr;
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continue;
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}
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/* Get last cpu affinity value */
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affinity_val = rt_cpu_mpidr_early[cpu_id] & 0xff00ffff00ULL;
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/* Read 16 cpus information */
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for (cpu_mask_bit = 0; cpu_mask_bit < 16; ++cpu_mask_bit, ++cpu_id)
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{
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/* MPIDR_EL1: aff3[39:32], aff2[23:16], aff1[15:8] */
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next_affinity_val = rt_cpu_mpidr_early[cpu_id] & 0xff00ffff00ULL;
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/* Affinity value is different, read end */
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if (affinity_val != next_affinity_val)
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{
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break;
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}
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}
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/* Get all valid cpu mask */
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target_list = (0xffff >> (16 - cpu_mask_bit)) & cpu_masks[i];
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/* Clear read mask */
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cpu_masks[i] >>= cpu_mask_bit;
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/* ICC_SGI1R_EL1: aff3[55:48], aff2[39:32], aff1[23:16] */
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affinity_val <<= 8;
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__DSB();
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/* Interrupts routed to the PEs specified by Aff3.Aff2.Aff1.<target list>. */
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SET_GICV3_REG(ICC_SGI1R_EL1, affinity_val | (rs << 44) | irm | int_id | target_list);
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__ISB();
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/* Check if reset the range selector */
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rs = affinity_val != next_affinity_val ? 0 : rs + 1;
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gicv3_sgi_target_list_set(i, cpu_masks[i]);
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}
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gicv3_sgi_send(int_id);
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}
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else
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{
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__DSB();
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/* Interrupts routed to all PEs in the system, excluding "self". */
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SET_GICV3_REG(ICC_SGI1R_EL1, irm | int_id);
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SET_GICV3_REG(ICC_SGI1R_EL1, (0x10000000000ULL) | int_id);
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__ISB();
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}
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}
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#endif /* RT_USING_SMP */
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#endif /* defined(RT_USING_SMP) || defined(RT_USING_AMP) */
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rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index)
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{
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@ -636,6 +698,8 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
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unsigned int gic_type;
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rt_uint64_t main_cpu_affinity_val;
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RT_UNUSED(i);
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RT_UNUSED(main_cpu_affinity_val);
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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_gic_table[index].dist_hw_base = dist_base;
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@ -660,6 +724,8 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
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_gic_max_irq = ARM_GIC_NR_IRQS;
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}
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#ifndef RT_AMP_SLAVE
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GIC_DIST_CTRL(dist_base) = 0;
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/* Wait for register write pending */
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arm_gicv3_wait_rwp(0, 32);
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@ -724,6 +790,7 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
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*/
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GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS;
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#endif /* RT_AMP_SLAVE */
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return 0;
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}
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@ -811,13 +878,19 @@ int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base)
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void arm_gic_dump_type(rt_uint64_t index)
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{
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unsigned int gic_type;
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unsigned int gic_version;
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unsigned int gic_rp;
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gic_version = (GIC_DIST_IIDR(_gic_table[index].dist_hw_base) >> 24) & 0xfUL;
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gic_rp = (GIC_DIST_IIDR(_gic_table[index].dist_hw_base) >> 12) & 0xfUL;
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gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
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rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
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(GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
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rt_kprintf("GICv3-%d r%dp%d on %p, max IRQs: %d, %s security extension(%08x)\n",
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(gic_version == 0) ? 500 : (gic_version == 2) ? 600 : 0,
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(gic_rp >> 4) & 0xF,
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gic_rp & 0xF,
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_gic_table[index].dist_hw_base,
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_gic_max_irq,
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gic_type & (1 << 10) ? "has" : "no",
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gic_type & (1U << 10U) ? "has" : "no",
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gic_type);
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}
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@ -850,10 +923,36 @@ void arm_gic_dump(rt_uint64_t index)
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rt_kprintf("\b\b\n");
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}
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static void arm_gic_bind_dump(void)
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{
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#ifdef BSP_USING_GICV3
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int i;
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for (i = 32; i < _gic_max_irq; i++)
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{
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rt_kprintf("irq(%d) -> 0x%X\n", i, arm_gic_get_router_cpu(0, i));
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}
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#endif /* BSP_USING_GICV3 */
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}
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static void arm_gic_sgi_dump(rt_uint64_t index)
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{
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rt_int32_t cpu_id = rt_hw_cpu_id();
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rt_kprintf("redist_hw_base = 0x%X\n", _gic_table[index].redist_hw_base[cpu_id]);
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rt_kprintf("--- sgi mask ---\n");
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rt_kprintf("0x%08x\n", GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]));
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rt_kprintf("--- sgi pending ---\n");
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rt_kprintf("0x%08x\n", GIC_RDISTSGI_ISPENDR0(_gic_table[index].redist_hw_base[cpu_id]));
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rt_kprintf("--- sgi active ---\n");
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rt_kprintf("0x%08x\n", GIC_RDISTSGI_ISACTIVER0(_gic_table[index].redist_hw_base[cpu_id]));
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}
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long gic_dump(void)
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{
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arm_gic_dump_type(0);
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arm_gic_dump(0);
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arm_gic_bind_dump();
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arm_gic_sgi_dump(0);
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return 0;
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}
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@ -41,6 +41,7 @@ rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
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void arm_gic_clear_active(rt_uint64_t index, int irq);
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void arm_gic_set_router_cpu(rt_uint64_t index, int irq, rt_uint64_t aff);
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void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask);
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rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq);
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@ -55,7 +56,7 @@ rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
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rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
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#ifdef RT_USING_SMP
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint32_t cpu_masks[], rt_uint64_t routing_mode);
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#endif
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@ -14,12 +14,8 @@
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#include "interrupt.h"
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#include "gic.h"
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#include "gicv3.h"
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#ifdef RT_USING_SMART
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#include "ioremap.h"
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#else
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#define rt_ioremap(x, ...) (x)
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#endif
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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@ -215,9 +211,15 @@ void rt_hw_interrupt_ack(int vector)
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* @param vector: the interrupt number
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* cpu_mask: target cpus mask, one bit for one core
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*/
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void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask)
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void rt_hw_interrupt_set_target_cpus(int vector, unsigned long cpu_mask)
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{
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arm_gic_set_cpu(0, vector, cpu_mask);
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#ifdef BSP_USING_GIC
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#ifdef BSP_USING_GICV3
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arm_gic_set_router_cpu(0, vector, cpu_mask);
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#else
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arm_gic_set_cpu(0, vector, (unsigned int) cpu_mask);
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#endif
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#endif
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}
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/**
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@ -379,16 +381,31 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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}
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}
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#ifdef BSP_USING_GIC
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if (vector > 32)
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{
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#ifdef BSP_USING_GICV3
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rt_uint64_t cpu_affinity_val;
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__asm__ volatile ("mrs %0, mpidr_el1":"=r"(cpu_affinity_val));
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rt_hw_interrupt_set_target_cpus(vector, cpu_affinity_val);
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#else
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rt_hw_interrupt_set_target_cpus(vector, rt_hw_cpu_id());
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#endif /* BSP_USING_GICV3 */
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}
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#endif
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return old_handler;
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}
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#ifdef RT_USING_SMP
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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#ifdef BSP_USING_GICV2
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arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
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#elif defined(BSP_USING_GICV3)
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arm_gic_send_affinity_sgi(0, ipi_vector, (unsigned int *)&cpu_mask, GICV3_ROUTED_TO_SPEC);
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rt_uint32_t gicv3_cpu_mask[(RT_CPUS_NR + 31) >> 5];
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gicv3_cpu_mask[0] = cpu_mask;
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arm_gic_send_affinity_sgi(0, ipi_vector, gicv3_cpu_mask, GICV3_ROUTED_TO_SPEC);
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#endif
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}
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@ -30,7 +30,7 @@ void rt_hw_interrupt_umask(int vector);
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int rt_hw_interrupt_get_irq(void);
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void rt_hw_interrupt_ack(int vector);
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void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask);
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void rt_hw_interrupt_set_target_cpus(int vector, unsigned long cpu_mask);
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unsigned int rt_hw_interrupt_get_target_cpus(int vector);
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void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode);
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@ -52,8 +52,7 @@ unsigned int rt_hw_interrupt_get_prior_group_bits(void);
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name);
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#ifdef RT_USING_SMP
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask);
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
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#endif
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||||
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Loading…
Reference in New Issue