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完善了STM32H7系列SPI使用DMA的驱动 

1.使能DMA时钟的条件编译中加入了STM32H7
2.添加STM32H7 "spi_config" 中的request字段
3.DMA初始化FiFo相关的初始化的条件编译选项中加入STM32H7
This commit is contained in:
qinge 2021-12-10 15:30:30 +08:00
parent 462f093cbd
commit 81b84ab166
2 changed files with 16 additions and 6 deletions
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10
bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h
View File

@ -35,6 +35,7 @@ extern "C" {
.dma_rcc = SPI1_TX_DMA_RCC, \ .dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \ .Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \ .dma_irq = SPI1_TX_DMA_IRQ, \
.request = DMA_REQUEST_SPI1_TX \
} }
#endif /* SPI1_TX_DMA_CONFIG */ #endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */ #endif /* BSP_SPI1_TX_USING_DMA */
@ -46,6 +47,7 @@ extern "C" {
.dma_rcc = SPI1_RX_DMA_RCC, \ .dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \ .Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \ .dma_irq = SPI1_RX_DMA_IRQ, \
.request = DMA_REQUEST_SPI1_RX \
} }
#endif /* SPI1_RX_DMA_CONFIG */ #endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */ #endif /* BSP_SPI1_RX_USING_DMA */
@ -68,6 +70,7 @@ extern "C" {
.dma_rcc = SPI2_TX_DMA_RCC, \ .dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \ .Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \ .dma_irq = SPI2_TX_DMA_IRQ, \
.request = DMA_REQUEST_SPI2_TX \
} }
#endif /* SPI2_TX_DMA_CONFIG */ #endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */ #endif /* BSP_SPI2_TX_USING_DMA */
@ -79,6 +82,7 @@ extern "C" {
.dma_rcc = SPI2_RX_DMA_RCC, \ .dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \ .Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \ .dma_irq = SPI2_RX_DMA_IRQ, \
.request = DMA_REQUEST_SPI2_RX \
} }
#endif /* SPI2_RX_DMA_CONFIG */ #endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */ #endif /* BSP_SPI2_RX_USING_DMA */
@ -101,6 +105,7 @@ extern "C" {
.dma_rcc = SPI3_TX_DMA_RCC, \ .dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \ .Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \ .dma_irq = SPI3_TX_DMA_IRQ, \
.request = DMA_REQUEST_SPI3_TX \
} }
#endif /* SPI3_TX_DMA_CONFIG */ #endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */ #endif /* BSP_SPI3_TX_USING_DMA */
@ -112,6 +117,7 @@ extern "C" {
.dma_rcc = SPI3_RX_DMA_RCC, \ .dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \ .Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \ .dma_irq = SPI3_RX_DMA_IRQ, \
.request = DMA_REQUEST_SPI3_RX \
} }
#endif /* SPI3_RX_DMA_CONFIG */ #endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */ #endif /* BSP_SPI3_RX_USING_DMA */
@ -134,6 +140,7 @@ extern "C" {
.dma_rcc = SPI4_TX_DMA_RCC, \ .dma_rcc = SPI4_TX_DMA_RCC, \
.Instance = SPI4_TX_DMA_INSTANCE, \ .Instance = SPI4_TX_DMA_INSTANCE, \
.dma_irq = SPI4_TX_DMA_IRQ, \ .dma_irq = SPI4_TX_DMA_IRQ, \
.request = DMA_REQUEST_SPI4_TX \
} }
#endif /* SPI4_TX_DMA_CONFIG */ #endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */ #endif /* BSP_SPI4_TX_USING_DMA */
@ -145,6 +152,7 @@ extern "C" {
.dma_rcc = SPI4_RX_DMA_RCC, \ .dma_rcc = SPI4_RX_DMA_RCC, \
.Instance = SPI4_RX_DMA_INSTANCE, \ .Instance = SPI4_RX_DMA_INSTANCE, \
.dma_irq = SPI4_RX_DMA_IRQ, \ .dma_irq = SPI4_RX_DMA_IRQ, \
.request = DMA_REQUEST_SPI4_RX \
} }
#endif /* SPI4_RX_DMA_CONFIG */ #endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */ #endif /* BSP_SPI4_RX_USING_DMA */
@ -167,6 +175,7 @@ extern "C" {
.dma_rcc = SPI5_TX_DMA_RCC, \ .dma_rcc = SPI5_TX_DMA_RCC, \
.Instance = SPI5_TX_DMA_INSTANCE, \ .Instance = SPI5_TX_DMA_INSTANCE, \
.dma_irq = SPI5_TX_DMA_IRQ, \ .dma_irq = SPI5_TX_DMA_IRQ, \
.request = DMA_REQUEST_SPI5_TX \
} }
#endif /* SPI5_TX_DMA_CONFIG */ #endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */ #endif /* BSP_SPI5_TX_USING_DMA */
@ -178,6 +187,7 @@ extern "C" {
.dma_rcc = SPI5_RX_DMA_RCC, \ .dma_rcc = SPI5_RX_DMA_RCC, \
.Instance = SPI5_RX_DMA_INSTANCE, \ .Instance = SPI5_RX_DMA_INSTANCE, \
.dma_irq = SPI5_RX_DMA_IRQ, \ .dma_irq = SPI5_RX_DMA_IRQ, \
.request = DMA_REQUEST_SPI5_RX \
} }
#endif /* SPI5_RX_DMA_CONFIG */ #endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */ #endif /* BSP_SPI5_RX_USING_DMA */

12
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
View File

@ -432,7 +432,7 @@ static int rt_hw_spi_bus_init(void)
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance; spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel; spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request; spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
#endif #endif
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
@ -442,7 +442,7 @@ static int rt_hw_spi_bus_init(void)
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
@ -455,7 +455,7 @@ static int rt_hw_spi_bus_init(void)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
@ -474,7 +474,7 @@ static int rt_hw_spi_bus_init(void)
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance; spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel; spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request; spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
#endif #endif
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
@ -484,7 +484,7 @@ static int rt_hw_spi_bus_init(void)
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
@ -497,7 +497,7 @@ static int rt_hw_spi_bus_init(void)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);