From 81b84ab16605b5b87c3b965050f86eef06e204ec Mon Sep 17 00:00:00 2001 From: qinge Date: Fri, 10 Dec 2021 15:30:30 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=8C=E5=96=84=E4=BA=86STM32H7=E7=B3=BB?= =?UTF-8?q?=E5=88=97SPI=E4=BD=BF=E7=94=A8DMA=E7=9A=84=E9=A9=B1=E5=8A=A8=20?= =?UTF-8?q?1.=E4=BD=BF=E8=83=BDDMA=E6=97=B6=E9=92=9F=E7=9A=84=E6=9D=A1?= =?UTF-8?q?=E4=BB=B6=E7=BC=96=E8=AF=91=E4=B8=AD=E5=8A=A0=E5=85=A5=E4=BA=86?= =?UTF-8?q?STM32H7=202.=E6=B7=BB=E5=8A=A0STM32H7=20"spi=5Fconfig"=20?= =?UTF-8?q?=E4=B8=AD=E7=9A=84request=E5=AD=97=E6=AE=B5=203.DMA=E5=88=9D?= =?UTF-8?q?=E5=A7=8B=E5=8C=96FiFo=E7=9B=B8=E5=85=B3=E7=9A=84=E5=88=9D?= =?UTF-8?q?=E5=A7=8B=E5=8C=96=E7=9A=84=E6=9D=A1=E4=BB=B6=E7=BC=96=E8=AF=91?= =?UTF-8?q?=E9=80=89=E9=A1=B9=E4=B8=AD=E5=8A=A0=E5=85=A5STM32H7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../libraries/HAL_Drivers/config/h7/spi_config.h | 10 ++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_spi.c | 12 ++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h index 79d2d83c0a..925ffa7197 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h @@ -35,6 +35,7 @@ extern "C" { .dma_rcc = SPI1_TX_DMA_RCC, \ .Instance = SPI1_TX_DMA_INSTANCE, \ .dma_irq = SPI1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI1_TX \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ @@ -46,6 +47,7 @@ extern "C" { .dma_rcc = SPI1_RX_DMA_RCC, \ .Instance = SPI1_RX_DMA_INSTANCE, \ .dma_irq = SPI1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI1_RX \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ @@ -68,6 +70,7 @@ extern "C" { .dma_rcc = SPI2_TX_DMA_RCC, \ .Instance = SPI2_TX_DMA_INSTANCE, \ .dma_irq = SPI2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI2_TX \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ @@ -79,6 +82,7 @@ extern "C" { .dma_rcc = SPI2_RX_DMA_RCC, \ .Instance = SPI2_RX_DMA_INSTANCE, \ .dma_irq = SPI2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI2_RX \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ @@ -101,6 +105,7 @@ extern "C" { .dma_rcc = SPI3_TX_DMA_RCC, \ .Instance = SPI3_TX_DMA_INSTANCE, \ .dma_irq = SPI3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI3_TX \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ @@ -112,6 +117,7 @@ extern "C" { .dma_rcc = SPI3_RX_DMA_RCC, \ .Instance = SPI3_RX_DMA_INSTANCE, \ .dma_irq = SPI3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI3_RX \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ @@ -134,6 +140,7 @@ extern "C" { .dma_rcc = SPI4_TX_DMA_RCC, \ .Instance = SPI4_TX_DMA_INSTANCE, \ .dma_irq = SPI4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI4_TX \ } #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ @@ -145,6 +152,7 @@ extern "C" { .dma_rcc = SPI4_RX_DMA_RCC, \ .Instance = SPI4_RX_DMA_INSTANCE, \ .dma_irq = SPI4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI4_RX \ } #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ @@ -167,6 +175,7 @@ extern "C" { .dma_rcc = SPI5_TX_DMA_RCC, \ .Instance = SPI5_TX_DMA_INSTANCE, \ .dma_irq = SPI5_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI5_TX \ } #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ @@ -178,6 +187,7 @@ extern "C" { .dma_rcc = SPI5_RX_DMA_RCC, \ .Instance = SPI5_RX_DMA_INSTANCE, \ .dma_irq = SPI5_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI5_RX \ } #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 9b5dcc0885..7630d39189 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -432,7 +432,7 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance; #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request; #endif spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; @@ -442,7 +442,7 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4; @@ -455,7 +455,7 @@ static int rt_hw_spi_bus_init(void) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc); @@ -474,7 +474,7 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance; #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request; #endif spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; @@ -484,7 +484,7 @@ static int rt_hw_spi_bus_init(void) spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW; -#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; @@ -497,7 +497,7 @@ static int rt_hw_spi_bus_init(void) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc); -#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);