From b21d59b3dc5ed87c0745e1f848e8d0d3a43cf686 Mon Sep 17 00:00:00 2001
From: Meco Man <920369182@qq.com>
Date: Sun, 21 Mar 2021 02:54:01 +0800
Subject: [PATCH 1/2] update project files
---
bsp/stm32f20x/.config | 259 ++++++--
bsp/stm32f20x/project.ewp | 544 +++++++---------
bsp/stm32f20x/project.uvproj | 1089 +++++++++++++++-----------------
bsp/stm32f20x/project.uvprojx | 1080 ++++++++++++-------------------
bsp/stm32f20x/rtconfig.h | 45 +-
bsp/stm32f20x/template.uvproj | 37 +-
bsp/stm32f20x/template.uvprojx | 79 ++-
7 files changed, 1408 insertions(+), 1725 deletions(-)
diff --git a/bsp/stm32f20x/.config b/bsp/stm32f20x/.config
index a568b7e0ae..5f3bc12590 100644
--- a/bsp/stm32f20x/.config
+++ b/bsp/stm32f20x/.config
@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -20,18 +21,7 @@ CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
-CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
-# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
-# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
-# CONFIG_RT_DEBUG_IPC_CONFIG is not set
-# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
-# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
-# CONFIG_RT_DEBUG_MEM_CONFIG is not set
-# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
-# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
-# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+# CONFIG_RT_DEBUG is not set
#
# Inter-Thread communication
@@ -51,6 +41,7 @@ CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
@@ -63,8 +54,9 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40001
+CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M3=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -73,6 +65,7 @@ CONFIG_ARCH_ARM_CORTEX_M3=y
# RT-Thread Components
#
# CONFIG_RT_USING_COMPONENTS_INIT is not set
+# CONFIG_RT_USING_USER_MAIN is not set
#
# C++ features
@@ -101,51 +94,34 @@ CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=4
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-CONFIG_RT_USING_DFS_ELMFAT=y
-
-#
-# elm-chan's FatFs, Generic FAT Filesystem Module
-#
-CONFIG_RT_DFS_ELM_CODE_PAGE=437
-CONFIG_RT_DFS_ELM_WORD_ACCESS=y
-CONFIG_RT_DFS_ELM_USE_LFN_0=y
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
-CONFIG_RT_DFS_ELM_USE_LFN=0
-CONFIG_RT_DFS_ELM_MAX_LFN=255
-CONFIG_RT_DFS_ELM_DRIVES=1
-CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
-# CONFIG_RT_DFS_ELM_USE_ERASE is not set
-CONFIG_RT_DFS_ELM_REENTRANT=y
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
# CONFIG_RT_USING_SERIAL is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
@@ -155,10 +131,10 @@ CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
-
-#
-# Using WiFi
-#
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
@@ -170,13 +146,9 @@ CONFIG_RT_USING_RTC=y
#
# POSIX layer and C standard library
#
-CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
-# CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_USING_TIME=y
#
# Network
@@ -187,16 +159,16 @@ CONFIG_RT_USING_POSIX=y
#
# CONFIG_RT_USING_SAL is not set
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
#
# AT commands
#
@@ -210,16 +182,9 @@ CONFIG_RT_USING_POSIX=y
#
# Utilities
#
-# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
-
-#
-# ARM CMSIS
-#
-# CONFIG_RT_USING_CMSIS_OS is not set
-# CONFIG_RT_USING_RTT_CMSIS is not set
# CONFIG_RT_USING_LWP is not set
#
@@ -229,14 +194,20 @@ CONFIG_RT_USING_POSIX=y
#
# IoT - internet of things
#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
@@ -258,7 +229,10 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
@@ -268,9 +242,34 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
#
# security packages
@@ -278,6 +277,8 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@@ -292,6 +293,11 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
#
# tools packages
@@ -303,7 +309,31 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
#
# system packages
@@ -314,12 +344,40 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
#
# peripheral libraries and drivers
@@ -327,17 +385,61 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
-# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
#
# miscellaneous packages
@@ -347,12 +449,17 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
@@ -363,7 +470,29 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
CONFIG_SOC_STM32F2=y
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART6 is not set
+CONFIG_SOC_STM32F20X=y
diff --git a/bsp/stm32f20x/project.ewp b/bsp/stm32f20x/project.ewp
index 9bdc55d5c8..930a998d2b 100644
--- a/bsp/stm32f20x/project.ewp
+++ b/bsp/stm32f20x/project.ewp
@@ -145,10 +145,8 @@
CCDefines
__RTTHREAD__
USE_STDPERIPH_DRIVER
- RT_USING_DLIBC
- _DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
CCPreprocFile
@@ -279,22 +277,18 @@
CCIncludePath2
$PROJ_DIR$\Libraries\CMSIS\Include
- $PROJ_DIR$\applications
- $PROJ_DIR$\..\..\components\libc\compilers\dlib
- $PROJ_DIR$\..\..\components\finsh
+ $PROJ_DIR$\..\..\include
+ $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx
$PROJ_DIR$\Drivers
$PROJ_DIR$\..\..\components\libc\compilers\common
- $PROJ_DIR$\..\..\components\drivers\include
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc
$PROJ_DIR$\.
- $PROJ_DIR$\..\..\include
+ $PROJ_DIR$\applications
$PROJ_DIR$\Libraries\CMSIS\CM3\CoreSupport
$PROJ_DIR$\..\..\libcpu\arm\cortex-m3
+ $PROJ_DIR$\..\..\components\drivers\include
$PROJ_DIR$\..\..\libcpu\arm\common
- $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc
- $PROJ_DIR$\..\..\components\dfs\filesystems\devfs
- $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx
- $PROJ_DIR$\..\..\components\dfs\include
+ $PROJ_DIR$\..\..\components\finsh
CCStdIncCheck
@@ -1022,10 +1016,8 @@
CCDefines
NDEBUG
+ __RTTHREAD__
USE_STDPERIPH_DRIVER
- RT_USING_DLIBC
- _DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
CCPreprocFile
@@ -1156,22 +1148,18 @@
CCIncludePath2
$PROJ_DIR$\Libraries\CMSIS\Include
- $PROJ_DIR$\applications
- $PROJ_DIR$\..\..\components\libc\compilers\dlib
- $PROJ_DIR$\..\..\components\finsh
+ $PROJ_DIR$\..\..\include
+ $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx
$PROJ_DIR$\Drivers
$PROJ_DIR$\..\..\components\libc\compilers\common
- $PROJ_DIR$\..\..\components\drivers\include
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc
$PROJ_DIR$\.
- $PROJ_DIR$\..\..\include
+ $PROJ_DIR$\applications
$PROJ_DIR$\Libraries\CMSIS\CM3\CoreSupport
$PROJ_DIR$\..\..\libcpu\arm\cortex-m3
+ $PROJ_DIR$\..\..\components\drivers\include
$PROJ_DIR$\..\..\libcpu\arm\common
- $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc
- $PROJ_DIR$\..\..\components\dfs\filesystems\devfs
- $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx
- $PROJ_DIR$\..\..\components\dfs\include
+ $PROJ_DIR$\..\..\components\finsh
CCStdIncCheck
@@ -1754,16 +1742,136 @@
+ Applications
+
+ $PROJ_DIR$\applications\startup.c
+
+
+ $PROJ_DIR$\applications\application.c
+
+
+
+ CPU
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\div0.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+ $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S
+
+
+
+ DeviceDrivers
+
+ $PROJ_DIR$\..\..\components\drivers\misc\pin.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\rtc\rtc.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\pipe.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\workqueue.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\completion.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c
+
+
+ $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c
+
+
+
+ Drivers
+
+ $PROJ_DIR$\Drivers\stm32f2xx_it.c
+
+
+ $PROJ_DIR$\Drivers\serial.c
+
+
+ $PROJ_DIR$\Drivers\24LCxx.c
+
+
+ $PROJ_DIR$\Drivers\board.c
+
+
+ $PROJ_DIR$\Drivers\i2c.c
+
+
+ $PROJ_DIR$\Drivers\FM25Lx.c
+
+
+ $PROJ_DIR$\Drivers\usart.c
+
+
+ $PROJ_DIR$\Drivers\drv_rtc.c
+
+
+
+ finsh
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_node.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_parser.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\cmd.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_vm.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\shell.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_var.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_heap.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_ops.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\msh.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_error.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_token.c
+
+
+ $PROJ_DIR$\..\..\components\finsh\finsh_init.c
+
+
Kernel
- $PROJ_DIR$\..\..\src\clock.c
-
-
- $PROJ_DIR$\..\..\src\cpu.c
-
-
- $PROJ_DIR$\..\..\src\device.c
+ $PROJ_DIR$\..\..\src\timer.c
$PROJ_DIR$\..\..\src\idle.c
@@ -1777,341 +1885,137 @@
$PROJ_DIR$\..\..\src\kservice.c
-
- $PROJ_DIR$\..\..\src\mem.c
-
$PROJ_DIR$\..\..\src\mempool.c
- $PROJ_DIR$\..\..\src\object.c
-
-
- $PROJ_DIR$\..\..\src\scheduler.c
-
-
- $PROJ_DIR$\..\..\src\signal.c
+ $PROJ_DIR$\..\..\src\device.c
$PROJ_DIR$\..\..\src\thread.c
- $PROJ_DIR$\..\..\src\timer.c
+ $PROJ_DIR$\..\..\src\components.c
-
-
- Applications
- $PROJ_DIR$\applications\application.c
+ $PROJ_DIR$\..\..\src\object.c
- $PROJ_DIR$\applications\startup.c
+ $PROJ_DIR$\..\..\src\mem.c
-
-
- Drivers
- $PROJ_DIR$\Drivers\24LCxx.c
+ $PROJ_DIR$\..\..\src\scheduler.c
- $PROJ_DIR$\Drivers\FM25Lx.c
-
-
- $PROJ_DIR$\Drivers\board.c
-
-
- $PROJ_DIR$\Drivers\drv_rtc.c
-
-
- $PROJ_DIR$\Drivers\i2c.c
-
-
- $PROJ_DIR$\Drivers\sdio_sd.c
-
-
- $PROJ_DIR$\Drivers\serial.c
-
-
- $PROJ_DIR$\Drivers\stm32f2xx_it.c
-
-
- $PROJ_DIR$\Drivers\usart.c
-
-
-
- STM32_StdPeriph
-
- $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
-
-
- $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
-
-
- $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\iar\startup_stm32f2xx.s
-
-
-
- cpu
-
- $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c
-
-
- $PROJ_DIR$\..\..\libcpu\arm\common\div0.c
-
-
- $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c
-
-
- $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c
-
-
- $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S
-
-
-
- Filesystem
-
- $PROJ_DIR$\..\..\components\dfs\src\dfs.c
-
-
- $PROJ_DIR$\..\..\components\dfs\src\dfs_file.c
-
-
- $PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c
-
-
- $PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c
-
-
- $PROJ_DIR$\..\..\components\dfs\src\poll.c
-
-
- $PROJ_DIR$\..\..\components\dfs\src\select.c
-
-
- $PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c
-
-
- $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c
-
-
- $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c
-
-
-
- DeviceDrivers
-
- $PROJ_DIR$\..\..\components\drivers\misc\pin.c
-
-
- $PROJ_DIR$\..\..\components\drivers\rtc\rtc.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\completion.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\pipe.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c
-
-
- $PROJ_DIR$\..\..\components\drivers\src\workqueue.c
-
-
-
- finsh
-
- $PROJ_DIR$\..\..\components\finsh\shell.c
-
-
- $PROJ_DIR$\..\..\components\finsh\symbol.c
-
-
- $PROJ_DIR$\..\..\components\finsh\cmd.c
-
-
- $PROJ_DIR$\..\..\components\finsh\msh.c
-
-
- $PROJ_DIR$\..\..\components\finsh\msh_cmd.c
-
-
- $PROJ_DIR$\..\..\components\finsh\msh_file.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_error.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_heap.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_init.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_node.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_ops.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_parser.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_var.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_vm.c
-
-
- $PROJ_DIR$\..\..\components\finsh\finsh_token.c
+ $PROJ_DIR$\..\..\src\clock.c
libc
- $PROJ_DIR$\..\..\components\libc\compilers\common\gmtime_r.c
+ $PROJ_DIR$\..\..\components\libc\compilers\common\time.c
- dlib
+ Libraries
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\libc.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\rmtx.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\stdio.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
- $PROJ_DIR$\..\..\components\libc\compilers\dlib\time.c
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
+
+
+ $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
+
+
+ $PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\iar\startup_stm32f2xx.s
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
+
+
+ $PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
diff --git a/bsp/stm32f20x/project.uvproj b/bsp/stm32f20x/project.uvproj
index 5424b2e029..debdfbaadd 100644
--- a/bsp/stm32f20x/project.uvproj
+++ b/bsp/stm32f20x/project.uvproj
@@ -7,6 +7,7 @@
RT-Thread STM32
0x4
ARM-ADS
+ 0
STM32F207VG
@@ -27,6 +28,7 @@
SFD\ST\STM32F2xx\STM32F2xx.sfr
+ 0
0
0
0
+ 0
+ 0
0
@@ -66,6 +70,8 @@
0
0
+ 0
+ 0
1
@@ -74,6 +80,8 @@
0
0
+ 0
+ 0
0
3
1
SARMCM3.DLL
@@ -121,6 +130,7 @@
1
1
0
+ 1
1
@@ -131,9 +141,11 @@
1
0
1
+ 0
+ 1
0
- 7
+ 4
1
4099
+ 0
Segger\JL2CM3.dll
"" ()
0
@@ -208,6 +225,7 @@
0
0
0
+ 0
3
3
0
@@ -331,7 +349,7 @@
1
0
0
- 0
+ 1
0
0
0
@@ -339,11 +357,22 @@
0
0
0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER
+ USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
.;..\..\include;applications;.;Drivers;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common
+ applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;Drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include
@@ -354,6 +383,9 @@
0
0
0
+ 0
+ 0
+ 0
0
0x08000000
0x20000000
+
-
- Kernel
-
-
- clock.c
- 1
- ..\..\src\clock.c
-
-
-
-
- components.c
- 1
- ..\..\src\components.c
-
-
-
-
- cpu.c
- 1
- ..\..\src\cpu.c
-
-
-
-
- device.c
- 1
- ..\..\src\device.c
-
-
-
-
- idle.c
- 1
- ..\..\src\idle.c
-
-
-
-
- ipc.c
- 1
- ..\..\src\ipc.c
-
-
-
-
- irq.c
- 1
- ..\..\src\irq.c
-
-
-
-
- kservice.c
- 1
- ..\..\src\kservice.c
-
-
-
-
- mem.c
- 1
- ..\..\src\mem.c
-
-
-
-
- mempool.c
- 1
- ..\..\src\mempool.c
-
-
-
-
- object.c
- 1
- ..\..\src\object.c
-
-
-
-
- scheduler.c
- 1
- ..\..\src\scheduler.c
-
-
-
-
- signal.c
- 1
- ..\..\src\signal.c
-
-
-
-
- thread.c
- 1
- ..\..\src\thread.c
-
-
-
-
- timer.c
- 1
- ..\..\src\timer.c
-
-
-
Applications
@@ -506,314 +431,7 @@
- Drivers
-
-
- 24LCxx.c
- 1
- Drivers\24LCxx.c
-
-
-
-
- FM25Lx.c
- 1
- Drivers\FM25Lx.c
-
-
-
-
- board.c
- 1
- Drivers\board.c
-
-
-
-
- drv_rtc.c
- 1
- Drivers\drv_rtc.c
-
-
-
-
- i2c.c
- 1
- Drivers\i2c.c
-
-
-
-
- sdio_sd.c
- 1
- Drivers\sdio_sd.c
-
-
-
-
- serial.c
- 1
- Drivers\serial.c
-
-
-
-
- stm32f2xx_it.c
- 1
- Drivers\stm32f2xx_it.c
-
-
-
-
- usart.c
- 1
- Drivers\usart.c
-
-
-
-
- STM32_StdPeriph
-
-
- system_stm32f2xx.c
- 1
- Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
-
-
-
-
- misc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
-
-
-
-
- stm32f2xx_adc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
-
-
-
-
- stm32f2xx_can.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
-
-
-
-
- stm32f2xx_crc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
-
-
-
-
- stm32f2xx_cryp.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
-
-
-
-
- stm32f2xx_cryp_aes.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
-
-
-
-
- stm32f2xx_cryp_des.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
-
-
-
-
- stm32f2xx_cryp_tdes.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
-
-
-
-
- stm32f2xx_dac.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
-
-
-
-
- stm32f2xx_dbgmcu.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
-
-
-
-
- stm32f2xx_dcmi.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
-
-
-
-
- stm32f2xx_dma.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
-
-
-
-
- stm32f2xx_exti.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
-
-
-
-
- stm32f2xx_flash.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
-
-
-
-
- stm32f2xx_fsmc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
-
-
-
-
- stm32f2xx_gpio.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
-
-
-
-
- stm32f2xx_hash.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
-
-
-
-
- stm32f2xx_hash_md5.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
-
-
-
-
- stm32f2xx_hash_sha1.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
-
-
-
-
- stm32f2xx_i2c.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
-
-
-
-
- stm32f2xx_iwdg.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
-
-
-
-
- stm32f2xx_pwr.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
-
-
-
-
- stm32f2xx_rcc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
-
-
-
-
- stm32f2xx_rng.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
-
-
-
-
- stm32f2xx_rtc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
-
-
-
-
- stm32f2xx_sdio.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
-
-
-
-
- stm32f2xx_spi.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
-
-
-
-
- stm32f2xx_syscfg.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
-
-
-
-
- stm32f2xx_tim.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
-
-
-
-
- stm32f2xx_usart.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
-
-
-
-
- stm32f2xx_wwdg.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
-
-
-
-
- startup_stm32f2xx.s
- 2
- Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\arm\startup_stm32f2xx.s
-
-
-
-
- cpu
-
-
- backtrace.c
- 1
- ..\..\libcpu\arm\common\backtrace.c
-
-
+ CPU
div0.c
@@ -830,9 +448,9 @@
- cpuport.c
+ backtrace.c
1
- ..\..\libcpu\arm\cortex-m3\cpuport.c
+ ..\..\libcpu\arm\common\backtrace.c
@@ -842,70 +460,11 @@
..\..\libcpu\arm\cortex-m3\context_rvds.S
-
-
- Filesystem
- dfs.c
+ cpuport.c
1
- ..\..\components\dfs\src\dfs.c
-
-
-
-
- dfs_file.c
- 1
- ..\..\components\dfs\src\dfs_file.c
-
-
-
-
- dfs_fs.c
- 1
- ..\..\components\dfs\src\dfs_fs.c
-
-
-
-
- dfs_posix.c
- 1
- ..\..\components\dfs\src\dfs_posix.c
-
-
-
-
- poll.c
- 1
- ..\..\components\dfs\src\poll.c
-
-
-
-
- select.c
- 1
- ..\..\components\dfs\src\select.c
-
-
-
-
- devfs.c
- 1
- ..\..\components\dfs\filesystems\devfs\devfs.c
-
-
-
-
- dfs_elm.c
- 1
- ..\..\components\dfs\filesystems\elmfat\dfs_elm.c
-
-
-
-
- ff.c
- 1
- ..\..\components\dfs\filesystems\elmfat\ff.c
+ ..\..\libcpu\arm\cortex-m3\cpuport.c
@@ -927,16 +486,9 @@
- completion.c
+ waitqueue.c
1
- ..\..\components\drivers\src\completion.c
-
-
-
-
- dataqueue.c
- 1
- ..\..\components\drivers\src\dataqueue.c
+ ..\..\components\drivers\src\waitqueue.c
@@ -948,9 +500,16 @@
- ringblk_buf.c
+ dataqueue.c
1
- ..\..\components\drivers\src\ringblk_buf.c
+ ..\..\components\drivers\src\dataqueue.c
+
+
+
+
+ completion.c
+ 1
+ ..\..\components\drivers\src\completion.c
@@ -962,9 +521,9 @@
- waitqueue.c
+ ringblk_buf.c
1
- ..\..\components\drivers\src\waitqueue.c
+ ..\..\components\drivers\src\ringblk_buf.c
@@ -975,64 +534,67 @@
+
+ Drivers
+
+
+ serial.c
+ 1
+ Drivers\serial.c
+
+
+
+
+ board.c
+ 1
+ Drivers\board.c
+
+
+
+
+ usart.c
+ 1
+ Drivers\usart.c
+
+
+
+
+ i2c.c
+ 1
+ Drivers\i2c.c
+
+
+
+
+ FM25Lx.c
+ 1
+ Drivers\FM25Lx.c
+
+
+
+
+ stm32f2xx_it.c
+ 1
+ Drivers\stm32f2xx_it.c
+
+
+
+
+ 24LCxx.c
+ 1
+ Drivers\24LCxx.c
+
+
+
+
+ drv_rtc.c
+ 1
+ Drivers\drv_rtc.c
+
+
+
finsh
-
-
- shell.c
- 1
- ..\..\components\finsh\shell.c
-
-
-
-
- cmd.c
- 1
- ..\..\components\finsh\cmd.c
-
-
-
-
- msh.c
- 1
- ..\..\components\finsh\msh.c
-
-
-
-
- msh_file.c
- 1
- ..\..\components\finsh\msh_file.c
-
-
-
-
- finsh_compiler.c
- 1
- ..\..\components\finsh\finsh_compiler.c
-
-
-
-
- finsh_error.c
- 1
- ..\..\components\finsh\finsh_error.c
-
-
-
-
- finsh_heap.c
- 1
- ..\..\components\finsh\finsh_heap.c
-
-
-
-
- finsh_init.c
- 1
- ..\..\components\finsh\finsh_init.c
-
-
finsh_node.c
@@ -1040,13 +602,6 @@
..\..\components\finsh\finsh_node.c
-
-
- finsh_ops.c
- 1
- ..\..\components\finsh\finsh_ops.c
-
-
finsh_parser.c
@@ -1056,9 +611,9 @@
- finsh_var.c
+ cmd.c
1
- ..\..\components\finsh\finsh_var.c
+ ..\..\components\finsh\cmd.c
@@ -1068,6 +623,55 @@
..\..\components\finsh\finsh_vm.c
+
+
+ shell.c
+ 1
+ ..\..\components\finsh\shell.c
+
+
+
+
+ finsh_var.c
+ 1
+ ..\..\components\finsh\finsh_var.c
+
+
+
+
+ finsh_compiler.c
+ 1
+ ..\..\components\finsh\finsh_compiler.c
+
+
+
+
+ finsh_heap.c
+ 1
+ ..\..\components\finsh\finsh_heap.c
+
+
+
+
+ finsh_ops.c
+ 1
+ ..\..\components\finsh\finsh_ops.c
+
+
+
+
+ finsh_error.c
+ 1
+ ..\..\components\finsh\finsh_error.c
+
+
+
+
+ msh.c
+ 1
+ ..\..\components\finsh\msh.c
+
+
finsh_token.c
@@ -1075,37 +679,110 @@
..\..\components\finsh\finsh_token.c
+
+
+ finsh_init.c
+ 1
+ ..\..\components\finsh\finsh_init.c
+
+
+
+
+ Kernel
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
+
+
+ mempool.c
+ 1
+ ..\..\src\mempool.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\src\timer.c
+
+
+
+
+ clock.c
+ 1
+ ..\..\src\clock.c
+
+
+
+
+ ipc.c
+ 1
+ ..\..\src\ipc.c
+
+
+
+
+ kservice.c
+ 1
+ ..\..\src\kservice.c
+
+
+
+
+ mem.c
+ 1
+ ..\..\src\mem.c
+
+
+
+
+ device.c
+ 1
+ ..\..\src\device.c
+
+
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
+
+
+
+
+ thread.c
+ 1
+ ..\..\src\thread.c
+
+
+
+
+ components.c
+ 1
+ ..\..\src\components.c
+
+
+
+
+ object.c
+ 1
+ ..\..\src\object.c
+
+
+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
libc
-
-
- libc.c
- 1
- ..\..\components\libc\compilers\armlibc\libc.c
-
-
-
-
- mem_std.c
- 1
- ..\..\components\libc\compilers\armlibc\mem_std.c
-
-
-
-
- stdio.c
- 1
- ..\..\components\libc\compilers\armlibc\stdio.c
-
-
-
-
- stubs.c
- 1
- ..\..\components\libc\compilers\armlibc\stubs.c
-
-
time.c
@@ -1114,6 +791,240 @@
+
+ Libraries
+
+
+ stm32f2xx_dcmi.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
+
+
+
+
+ stm32f2xx_wwdg.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
+
+
+
+
+ stm32f2xx_rng.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
+
+
+
+
+ stm32f2xx_hash_sha1.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
+
+
+
+
+ stm32f2xx_hash.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
+
+
+
+
+ stm32f2xx_pwr.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
+
+
+
+
+ stm32f2xx_cryp.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
+
+
+
+
+ stm32f2xx_fsmc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
+
+
+
+
+ stm32f2xx_hash_md5.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
+
+
+
+
+ stm32f2xx_rcc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
+
+
+
+
+ stm32f2xx_exti.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
+
+
+
+
+ stm32f2xx_rtc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
+
+
+
+
+ stm32f2xx_cryp_tdes.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
+
+
+
+
+ system_stm32f2xx.c
+ 1
+ Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
+
+
+
+
+ stm32f2xx_tim.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
+
+
+
+
+ stm32f2xx_spi.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
+
+
+
+
+ stm32f2xx_cryp_des.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
+
+
+
+
+ stm32f2xx_usart.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
+
+
+
+
+ stm32f2xx_crc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
+
+
+
+
+ misc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
+
+
+
+
+ stm32f2xx_can.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
+
+
+
+
+ startup_stm32f2xx.s
+ 2
+ Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\arm\startup_stm32f2xx.s
+
+
+
+
+ stm32f2xx_flash.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
+
+
+
+
+ stm32f2xx_gpio.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
+
+
+
+
+ stm32f2xx_dac.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
+
+
+
+
+ stm32f2xx_dma.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
+
+
+
+
+ stm32f2xx_sdio.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
+
+
+
+
+ stm32f2xx_cryp_aes.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
+
+
+
+
+ stm32f2xx_dbgmcu.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
+
+
+
+
+ stm32f2xx_syscfg.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
+
+
+
+
+ stm32f2xx_iwdg.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
+
+
+
+
+ stm32f2xx_i2c.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
+
+
+
+
+ stm32f2xx_adc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
+
+
+
diff --git a/bsp/stm32f20x/project.uvprojx b/bsp/stm32f20x/project.uvprojx
index 95caac5140..548fd7a663 100644
--- a/bsp/stm32f20x/project.uvprojx
+++ b/bsp/stm32f20x/project.uvprojx
@@ -1,39 +1,44 @@
+
2.1
+
### uVision Project, (C) Keil Software
+
RT-Thread STM32
0x4
ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
STM32F207VG
STMicroelectronics
- Keil.STM32F2xx_DFP.2.0.0
+ Keil.STM32F2xx_DFP.2.9.0
http://www.keil.com/pack
IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
- UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207VGTx$CMSIS\Flash\STM32F2xx_1024.FLM))
0
$$Device:STM32F207VGTx$Drivers\CMSIS\Device\ST\STM32F2xx\Include\stm32f2xx.h
- $$Device:STM32F207VGTx$CMSIS\SVD\STM32F20x.svd
0
0
- ST\STM32F2xx\
ST\STM32F2xx\
@@ -49,7 +54,7 @@
0
0
1
- 0
+ 1
.\build\
1
0
@@ -57,29 +62,35 @@
0
0
- 0
0
+ 0
+ 0
0
0
- 0
0
+ 0
+ 0
1
0
fromelf --bin !L --output rtthread.bin
- 0
0
+ 0
+ 0
0
-
0
@@ -93,8 +104,9 @@
0
0
3
- 1
SARMCM3.DLL
@@ -114,57 +126,24 @@
0
16
-
- 0
- 1
- 0
- 1
- 1
- 1
- 1
- 1
- 0
-
-
- 1
- 1
- 1
- 1
- 1
- 1
- 0
- 1
-
- 0
- 7
-
-
-
- Segger\JL2CM3.dll
-
1
0
0
- 0
+ 1
1
4099
+ 1
Segger\JL2CM3.dll
"" ()
- 0
@@ -196,7 +175,7 @@
0
0
"Cortex-M3"
- 0
0
0
@@ -211,6 +190,7 @@
0
0
0
+ 0
3
3
0
@@ -327,14 +307,14 @@
0x0
-
1
1
0
0
- 0
+ 1
0
0
0
@@ -342,11 +322,22 @@
0
0
0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
- RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER
- .;..\..\include;applications;.;Drivers;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common
+ USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+ applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;Drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include
@@ -357,11 +348,14 @@
0
0
0
+ 0
+ 0
+ 0
-
@@ -373,542 +367,59 @@
0
0x08000000
0x20000000
-
-
- Kernel
-
-
- clock.c
- 1
- ..\..\src\clock.c
-
-
-
-
- components.c
- 1
- ..\..\src\components.c
-
-
-
-
- cpu.c
- 1
- ..\..\src\cpu.c
-
-
-
-
- device.c
- 1
- ..\..\src\device.c
-
-
-
-
- idle.c
- 1
- ..\..\src\idle.c
-
-
-
-
- ipc.c
- 1
- ..\..\src\ipc.c
-
-
-
-
- irq.c
- 1
- ..\..\src\irq.c
-
-
-
-
- kservice.c
- 1
- ..\..\src\kservice.c
-
-
-
-
- mem.c
- 1
- ..\..\src\mem.c
-
-
-
-
- mempool.c
- 1
- ..\..\src\mempool.c
-
-
-
-
- object.c
- 1
- ..\..\src\object.c
-
-
-
-
- scheduler.c
- 1
- ..\..\src\scheduler.c
-
-
-
-
- signal.c
- 1
- ..\..\src\signal.c
-
-
-
-
- thread.c
- 1
- ..\..\src\thread.c
-
-
-
-
- timer.c
- 1
- ..\..\src\timer.c
-
-
-
Applications
-
-
- application.c
- 1
- applications\application.c
-
-
startup.c
1
applications\startup.c
-
-
-
- Drivers
-
- 24LCxx.c
+ application.c
1
- Drivers\24LCxx.c
-
-
-
-
- FM25Lx.c
- 1
- Drivers\FM25Lx.c
-
-
-
-
- board.c
- 1
- Drivers\board.c
-
-
-
-
- drv_rtc.c
- 1
- Drivers\drv_rtc.c
-
-
-
-
- i2c.c
- 1
- Drivers\i2c.c
-
-
-
-
- sdio_sd.c
- 1
- Drivers\sdio_sd.c
-
-
-
-
- serial.c
- 1
- Drivers\serial.c
-
-
-
-
- stm32f2xx_it.c
- 1
- Drivers\stm32f2xx_it.c
-
-
-
-
- usart.c
- 1
- Drivers\usart.c
+ applications\application.c
- STM32_StdPeriph
-
-
- system_stm32f2xx.c
- 1
- Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
-
-
-
-
- misc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
-
-
-
-
- stm32f2xx_adc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
-
-
-
-
- stm32f2xx_can.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
-
-
-
-
- stm32f2xx_crc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
-
-
-
-
- stm32f2xx_cryp.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
-
-
-
-
- stm32f2xx_cryp_aes.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
-
-
-
-
- stm32f2xx_cryp_des.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
-
-
-
-
- stm32f2xx_cryp_tdes.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
-
-
-
-
- stm32f2xx_dac.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
-
-
-
-
- stm32f2xx_dbgmcu.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
-
-
-
-
- stm32f2xx_dcmi.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
-
-
-
-
- stm32f2xx_dma.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
-
-
-
-
- stm32f2xx_exti.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
-
-
-
-
- stm32f2xx_flash.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
-
-
-
-
- stm32f2xx_fsmc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
-
-
-
-
- stm32f2xx_gpio.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
-
-
-
-
- stm32f2xx_hash.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
-
-
-
-
- stm32f2xx_hash_md5.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
-
-
-
-
- stm32f2xx_hash_sha1.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
-
-
-
-
- stm32f2xx_i2c.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
-
-
-
-
- stm32f2xx_iwdg.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
-
-
-
-
- stm32f2xx_pwr.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
-
-
-
-
- stm32f2xx_rcc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
-
-
-
-
- stm32f2xx_rng.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
-
-
-
-
- stm32f2xx_rtc.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
-
-
-
-
- stm32f2xx_sdio.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
-
-
-
-
- stm32f2xx_spi.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
-
-
-
-
- stm32f2xx_syscfg.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
-
-
-
-
- stm32f2xx_tim.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
-
-
-
-
- stm32f2xx_usart.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
-
-
-
-
- stm32f2xx_wwdg.c
- 1
- Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
-
-
-
-
- startup_stm32f2xx.s
- 2
- Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\arm\startup_stm32f2xx.s
-
-
-
-
- cpu
-
-
- backtrace.c
- 1
- ..\..\libcpu\arm\common\backtrace.c
-
-
+ CPU
div0.c
1
..\..\libcpu\arm\common\div0.c
-
-
+
+ backtrace.c
+ 1
+ ..\..\libcpu\arm\common\backtrace.c
+
showmem.c
1
..\..\libcpu\arm\common\showmem.c
-
-
-
- cpuport.c
- 1
- ..\..\libcpu\arm\cortex-m3\cpuport.c
-
-
-
context_rvds.S
2
..\..\libcpu\arm\cortex-m3\context_rvds.S
-
-
-
- Filesystem
-
- dfs.c
+ cpuport.c
1
- ..\..\components\dfs\src\dfs.c
-
-
-
-
- dfs_file.c
- 1
- ..\..\components\dfs\src\dfs_file.c
-
-
-
-
- dfs_fs.c
- 1
- ..\..\components\dfs\src\dfs_fs.c
-
-
-
-
- dfs_posix.c
- 1
- ..\..\components\dfs\src\dfs_posix.c
-
-
-
-
- poll.c
- 1
- ..\..\components\dfs\src\poll.c
-
-
-
-
- select.c
- 1
- ..\..\components\dfs\src\select.c
-
-
-
-
- devfs.c
- 1
- ..\..\components\dfs\filesystems\devfs\devfs.c
-
-
-
-
- dfs_elm.c
- 1
- ..\..\components\dfs\filesystems\elmfat\dfs_elm.c
-
-
-
-
- ff.c
- 1
- ..\..\components\dfs\filesystems\elmfat\ff.c
+ ..\..\libcpu\arm\cortex-m3\cpuport.c
@@ -920,61 +431,90 @@
1
..\..\components\drivers\misc\pin.c
-
-
rtc.c
1
..\..\components\drivers\rtc\rtc.c
-
-
+
+ waitqueue.c
+ 1
+ ..\..\components\drivers\src\waitqueue.c
+
+
+ dataqueue.c
+ 1
+ ..\..\components\drivers\src\dataqueue.c
+
+
+ pipe.c
+ 1
+ ..\..\components\drivers\src\pipe.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\components\drivers\src\ringbuffer.c
+
+
+ ringblk_buf.c
+ 1
+ ..\..\components\drivers\src\ringblk_buf.c
+
+
+ workqueue.c
+ 1
+ ..\..\components\drivers\src\workqueue.c
+
completion.c
1
..\..\components\drivers\src\completion.c
+
+
+ Drivers
- dataqueue.c
+ board.c
1
- ..\..\components\drivers\src\dataqueue.c
+ Drivers\board.c
-
-
- pipe.c
+ serial.c
1
- ..\..\components\drivers\src\pipe.c
+ Drivers\serial.c
-
-
- ringblk_buf.c
+ stm32f2xx_it.c
1
- ..\..\components\drivers\src\ringblk_buf.c
+ Drivers\stm32f2xx_it.c
-
-
- ringbuffer.c
+ drv_rtc.c
1
- ..\..\components\drivers\src\ringbuffer.c
+ Drivers\drv_rtc.c
-
-
- waitqueue.c
+ FM25Lx.c
1
- ..\..\components\drivers\src\waitqueue.c
+ Drivers\FM25Lx.c
-
-
- workqueue.c
+ usart.c
1
- ..\..\components\drivers\src\workqueue.c
+ Drivers\usart.c
+
+
+ i2c.c
+ 1
+ Drivers\i2c.c
+
+
+ 24LCxx.c
+ 1
+ Drivers\24LCxx.c
@@ -982,133 +522,144 @@
finsh
- shell.c
+ finsh_node.c
1
- ..\..\components\finsh\shell.c
+ ..\..\components\finsh\finsh_node.c
+
+
+ finsh_parser.c
+ 1
+ ..\..\components\finsh\finsh_parser.c
-
-
cmd.c
1
..\..\components\finsh\cmd.c
-
-
- msh.c
+ finsh_vm.c
1
- ..\..\components\finsh\msh.c
+ ..\..\components\finsh\finsh_vm.c
-
-
- msh_file.c
+ shell.c
1
- ..\..\components\finsh\msh_file.c
+ ..\..\components\finsh\shell.c
+
+
+ finsh_token.c
+ 1
+ ..\..\components\finsh\finsh_token.c
+
+
+ finsh_var.c
+ 1
+ ..\..\components\finsh\finsh_var.c
-
-
finsh_compiler.c
1
..\..\components\finsh\finsh_compiler.c
-
-
-
- finsh_error.c
- 1
- ..\..\components\finsh\finsh_error.c
-
-
-
finsh_heap.c
1
..\..\components\finsh\finsh_heap.c
-
-
+
+ finsh_ops.c
+ 1
+ ..\..\components\finsh\finsh_ops.c
+
+
+ finsh_error.c
+ 1
+ ..\..\components\finsh\finsh_error.c
+
+
+ msh.c
+ 1
+ ..\..\components\finsh\msh.c
+
finsh_init.c
1
..\..\components\finsh\finsh_init.c
+
+
+ Kernel
- finsh_node.c
+ thread.c
1
- ..\..\components\finsh\finsh_node.c
+ ..\..\src\thread.c
-
-
- finsh_ops.c
+ object.c
1
- ..\..\components\finsh\finsh_ops.c
+ ..\..\src\object.c
-
-
- finsh_parser.c
+ clock.c
1
- ..\..\components\finsh\finsh_parser.c
+ ..\..\src\clock.c
-
-
- finsh_var.c
+ device.c
1
- ..\..\components\finsh\finsh_var.c
+ ..\..\src\device.c
-
-
- finsh_vm.c
+ ipc.c
1
- ..\..\components\finsh\finsh_vm.c
+ ..\..\src\ipc.c
-
-
- finsh_token.c
+ timer.c
1
- ..\..\components\finsh\finsh_token.c
+ ..\..\src\timer.c
+
+
+ kservice.c
+ 1
+ ..\..\src\kservice.c
+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
+ mempool.c
+ 1
+ ..\..\src\mempool.c
+
+
+ components.c
+ 1
+ ..\..\src\components.c
+
+
+ mem.c
+ 1
+ ..\..\src\mem.c
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
libc
-
-
- libc.c
- 1
- ..\..\components\libc\compilers\armlibc\libc.c
-
-
-
-
- mem_std.c
- 1
- ..\..\components\libc\compilers\armlibc\mem_std.c
-
-
-
-
- stdio.c
- 1
- ..\..\components\libc\compilers\armlibc\stdio.c
-
-
-
-
- stubs.c
- 1
- ..\..\components\libc\compilers\armlibc\stubs.c
-
-
time.c
@@ -1117,7 +668,184 @@
+
+ Libraries
+
+
+ stm32f2xx_dcmi.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c
+
+
+ stm32f2xx_wwdg.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c
+
+
+ stm32f2xx_rng.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c
+
+
+ stm32f2xx_hash_sha1.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c
+
+
+ stm32f2xx_hash.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c
+
+
+ stm32f2xx_pwr.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c
+
+
+ stm32f2xx_cryp.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c
+
+
+ stm32f2xx_fsmc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c
+
+
+ stm32f2xx_hash_md5.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c
+
+
+ stm32f2xx_rcc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c
+
+
+ stm32f2xx_exti.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c
+
+
+ stm32f2xx_rtc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c
+
+
+ stm32f2xx_cryp_tdes.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c
+
+
+ system_stm32f2xx.c
+ 1
+ Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c
+
+
+ stm32f2xx_tim.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c
+
+
+ stm32f2xx_spi.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c
+
+
+ stm32f2xx_cryp_des.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c
+
+
+ stm32f2xx_usart.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c
+
+
+ stm32f2xx_crc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c
+
+
+ misc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c
+
+
+ stm32f2xx_can.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c
+
+
+ startup_stm32f2xx.s
+ 2
+ Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\arm\startup_stm32f2xx.s
+
+
+ stm32f2xx_flash.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c
+
+
+ stm32f2xx_gpio.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c
+
+
+ stm32f2xx_dac.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c
+
+
+ stm32f2xx_dma.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c
+
+
+ stm32f2xx_sdio.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c
+
+
+ stm32f2xx_cryp_aes.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c
+
+
+ stm32f2xx_dbgmcu.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c
+
+
+ stm32f2xx_syscfg.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c
+
+
+ stm32f2xx_iwdg.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c
+
+
+ stm32f2xx_i2c.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c
+
+
+ stm32f2xx_adc.c
+ 1
+ Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c
+
+
+
+
+
+
+
diff --git a/bsp/stm32f20x/rtconfig.h b/bsp/stm32f20x/rtconfig.h
index 8a2f3e4b6a..3790d931e7 100644
--- a/bsp/stm32f20x/rtconfig.h
+++ b/bsp/stm32f20x/rtconfig.h
@@ -16,8 +16,6 @@
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
/* Inter-Thread communication */
@@ -39,8 +37,9 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40001
+#define RT_VER_NUM 0x40003
#define ARCH_ARM
+#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M3
@@ -67,24 +66,6 @@
/* Device virtual file system */
-#define RT_USING_DFS
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 4
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_0
-#define RT_DFS_ELM_USE_LFN 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 1
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
-#define RT_DFS_ELM_REENTRANT
-#define RT_USING_DFS_DEVFS
/* Device Drivers */
@@ -93,28 +74,24 @@
#define RT_USING_PIN
#define RT_USING_RTC
-/* Using WiFi */
-
-
/* Using USB */
/* POSIX layer and C standard library */
-#define RT_USING_LIBC
-#define RT_USING_POSIX
+#define RT_LIBC_USING_TIME
/* Network */
/* Socket abstraction layer */
+/* Network interface device */
+
+
/* light weight TCP/IP stack */
-/* Modbus master and slave stack */
-
-
/* AT commands */
@@ -124,9 +101,6 @@
/* Utilities */
-/* ARM CMSIS */
-
-
/* RT-Thread online packages */
/* IoT - internet of things */
@@ -158,6 +132,9 @@
/* system packages */
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
/* peripheral libraries and drivers */
@@ -166,7 +143,11 @@
/* samples: kernel and components samples */
+
+/* games: games run on RT-Thread console */
+
#define SOC_STM32F2
#define RT_USING_UART1
+#define SOC_STM32F20X
#endif
diff --git a/bsp/stm32f20x/template.uvproj b/bsp/stm32f20x/template.uvproj
index 79c48c556f..9458edbfa3 100644
--- a/bsp/stm32f20x/template.uvproj
+++ b/bsp/stm32f20x/template.uvproj
@@ -10,6 +10,7 @@
RT-Thread STM32
0x4
ARM-ADS
+ 0
STM32F207VG
@@ -30,6 +31,7 @@
SFD\ST\STM32F2xx\STM32F2xx.sfr
+ 0
0
0
0
+ 0
+ 0
0
@@ -69,6 +73,8 @@
0
0
+ 0
+ 0
1
@@ -77,6 +83,8 @@
0
0
+ 0
+ 0
0
3
1
SARMCM3.DLL
@@ -124,6 +133,7 @@
1
1
0
+ 1
1
@@ -134,9 +144,11 @@
1
0
1
+ 0
+ 1
0
- 7
+ 4
1
4099
+ 0
Segger\JL2CM3.dll
"" ()
0
@@ -211,6 +228,7 @@
0
0
0
+ 0
3
3
0
@@ -334,7 +352,7 @@
1
0
0
- 0
+ 1
0
0
0
@@ -342,6 +360,17 @@
0
0
0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
0
0
0
+ 0
+ 0
+ 0
0
0x08000000
0x20000000
+ RT-Thread STM32
0x4
ARM-ADS
+ 0
STM32F207VG
STMicroelectronics
- Keil.STM32F2xx_DFP.2.0.0
+ Keil.STM32F2xx_DFP.2.9.0
http://www.keil.com/pack
IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
0
0
+ 0
+ 0
0
@@ -72,6 +75,8 @@
0
0
+ 0
+ 0
1
@@ -80,6 +85,8 @@
0
0
+ 0
+ 0
0
3
1
SARMCM3.DLL
@@ -117,57 +125,24 @@
0
16
-
- 0
- 1
- 0
- 1
- 1
- 1
- 1
- 1
- 0
-
-
- 1
- 1
- 1
- 1
- 1
- 1
- 0
- 1
-
- 0
- 7
-
-
-
- Segger\JL2CM3.dll
-
1
0
0
- 0
+ 1
1
4099
+ 1
Segger\JL2CM3.dll
"" ()
0
@@ -214,6 +189,7 @@
0
0
0
+ 0
3
3
0
@@ -337,7 +313,7 @@
1
0
0
- 0
+ 1
0
0
0
@@ -345,6 +321,17 @@
0
0
0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
0
0
0
+ 0
+ 0
+ 0
0
0x08000000
0x20000000
+
+
+
From 70b1c0e92f3a5de621281ada0045179dd0b9e715 Mon Sep 17 00:00:00 2001
From: Meco Man <920369182@qq.com>
Date: Sun, 21 Mar 2021 02:55:53 +0800
Subject: [PATCH 2/2] auto formatted
---
bsp/stm32f20x/Drivers/24LCxx.c | 192 ++---
bsp/stm32f20x/Drivers/FM25Lx.c | 214 ++---
bsp/stm32f20x/Drivers/FM25Lx.h | 52 +-
bsp/stm32f20x/Drivers/board.c | 56 +-
bsp/stm32f20x/Drivers/board.h | 44 +-
bsp/stm32f20x/Drivers/drv_rtc.c | 170 ++--
bsp/stm32f20x/Drivers/drv_rtc.h | 2 +-
bsp/stm32f20x/Drivers/i2c.c | 948 +++++++++++------------
bsp/stm32f20x/Drivers/i2c.h | 36 +-
bsp/stm32f20x/Drivers/sdio_sd.c | 602 +++++++-------
bsp/stm32f20x/Drivers/sdio_sd.h | 112 +--
bsp/stm32f20x/Drivers/serial.c | 566 +++++++-------
bsp/stm32f20x/Drivers/serial.h | 42 +-
bsp/stm32f20x/Drivers/stm32f2_eth.c | 554 ++++++-------
bsp/stm32f20x/Drivers/stm32f2xx_it.c | 10 +-
bsp/stm32f20x/Drivers/usart.c | 234 +++---
bsp/stm32f20x/Drivers/usart.h | 2 +-
bsp/stm32f20x/applications/application.c | 2 +-
bsp/stm32f20x/applications/startup.c | 70 +-
19 files changed, 1954 insertions(+), 1954 deletions(-)
diff --git a/bsp/stm32f20x/Drivers/24LCxx.c b/bsp/stm32f20x/Drivers/24LCxx.c
index 1903a85b82..1fdbc9b8d1 100644
--- a/bsp/stm32f20x/Drivers/24LCxx.c
+++ b/bsp/stm32f20x/Drivers/24LCxx.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -16,171 +16,171 @@
#define EE24LC024H
/*
- Note: If eeprom size lager then EE_MEM_SIZE byte, you must define EE_ADDR_SIZE == I2C_MEM_2Bytes
+ Note: If eeprom size lager then EE_MEM_SIZE byte, you must define EE_ADDR_SIZE == I2C_MEM_2Bytes
*/
#ifdef EE24LC024H
#define EE_ADDR_SIZE I2C_MEM_1Byte
-#define EE_MEM_SIZE 256
-#define EE_PageSize 16
+#define EE_MEM_SIZE 256
+#define EE_PageSize 16
#endif
static struct rt_device ee_dev;
uint32_t EE_ReadBuffer(void *pBuffer, rt_off_t ReadAddr, rt_size_t NumByteToRead)
{
- return I2C_IORW(I2C1, (uint8_t *)pBuffer, (uint16_t)NumByteToRead, (uint16_t)ReadAddr, EE_Address | 0x01, I2C_MEM_1Byte );
+ return I2C_IORW(I2C1, (uint8_t *)pBuffer, (uint16_t)NumByteToRead, (uint16_t)ReadAddr, EE_Address | 0x01, I2C_MEM_1Byte );
}
uint32_t EE_WritePage(void *pBuffer, uint16_t WriteAddr)
-{
- I2C_IORW(I2C1, (uint8_t *)pBuffer, EE_PageSize , WriteAddr, EE_Address , EE_ADDR_SIZE );
+{
+ I2C_IORW(I2C1, (uint8_t *)pBuffer, EE_PageSize , WriteAddr, EE_Address , EE_ADDR_SIZE );
- /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error )
- rt_kprintf("EE ACK failed\n");*/
- rt_thread_delay(50);
+ /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error )
+ rt_kprintf("EE ACK failed\n");*/
+ rt_thread_delay(50);
- return 0;
+ return 0;
}
uint32_t EE_WriteByte(void *pBuffer, uint16_t WriteAddr)
{
- I2C_IORW(I2C1, (uint8_t *)pBuffer, 1 , WriteAddr, EE_Address, EE_ADDR_SIZE );
+ I2C_IORW(I2C1, (uint8_t *)pBuffer, 1 , WriteAddr, EE_Address, EE_ADDR_SIZE );
- /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error )
- rt_kprintf("EE ACK failed\n");*/
- rt_thread_delay(50);
+ /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error )
+ rt_kprintf("EE ACK failed\n");*/
+ rt_thread_delay(50);
- return 0;
+ return 0;
}
Status EE_WriteBuffer(const void *pBuffer, rt_off_t WriteAddr, rt_size_t NumByteToWrite)
{
- uint8_t NumOfPage = 0, NumOfSingle = 0;
- uint16_t Addr = 0,count = 0;
- uint8_t *ptr = (uint8_t *)pBuffer;
-
- Addr = (uint16_t)(WriteAddr&0xFFFF);
+ uint8_t NumOfPage = 0, NumOfSingle = 0;
+ uint16_t Addr = 0,count = 0;
+ uint8_t *ptr = (uint8_t *)pBuffer;
- count = (uint16_t)(NumByteToWrite&0xFFFF);
-
- if ((WriteAddr + NumByteToWrite) > EE_MEM_SIZE)
- return Error;
+ Addr = (uint16_t)(WriteAddr&0xFFFF);
- while (count >= EE_PageSize)
- {
- EE_WritePage(ptr, Addr);
- Addr += EE_PageSize;
- count -= EE_PageSize;
- ptr += EE_PageSize;
- }
-
- while (count)
- {
- EE_WriteByte(ptr++, Addr++);
- count--;
- }
-
- return Success;
+ count = (uint16_t)(NumByteToWrite&0xFFFF);
+
+ if ((WriteAddr + NumByteToWrite) > EE_MEM_SIZE)
+ return Error;
+
+ while (count >= EE_PageSize)
+ {
+ EE_WritePage(ptr, Addr);
+ Addr += EE_PageSize;
+ count -= EE_PageSize;
+ ptr += EE_PageSize;
+ }
+
+ while (count)
+ {
+ EE_WriteByte(ptr++, Addr++);
+ count--;
+ }
+
+ return Success;
}
static rt_err_t ee24LCxx_init(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t ee24LCxx_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
{
- if (EE_ReadBuffer(buf, pos, size) == Success)
- return size;
- else
- return -1;
+ if (EE_ReadBuffer(buf, pos, size) == Success)
+ return size;
+ else
+ return -1;
}
static rt_size_t ee24LCxx_write(rt_device_t dev, rt_off_t pos, const void *buf, rt_size_t size)
{
- if (EE_WriteBuffer(buf, pos, size) == Success)
- return size;
- else
- return -1;
+ if (EE_WriteBuffer(buf, pos, size) == Success)
+ return size;
+ else
+ return -1;
}
static rt_err_t ee24LCxx_open(rt_device_t dev, rt_uint16_t oflag)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t ee24LCxx_close(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t ee24LCxx_control(rt_device_t dev, int cmd, void *args)
{
- return RT_EOK;
+ return RT_EOK;
}
void ee24LCxx_hw_init(void)
{
- uint32_t delay, i;
- I2C1_INIT();
+ uint32_t delay, i;
+ I2C1_INIT();
- for (i =0; i < 4; i++)
- {
- delay = 0xFFFFF;
- while (delay--);
- }
+ for (i =0; i < 4; i++)
+ {
+ delay = 0xFFFFF;
+ while (delay--);
+ }
- ee_dev.init = ee24LCxx_init;
- ee_dev.open = ee24LCxx_open;
- ee_dev.close = ee24LCxx_close;
- ee_dev.read = ee24LCxx_read;
- ee_dev.write = ee24LCxx_write;
- ee_dev.control = ee24LCxx_control;
- ee_dev.type = RT_Device_Class_Unknown;
+ ee_dev.init = ee24LCxx_init;
+ ee_dev.open = ee24LCxx_open;
+ ee_dev.close = ee24LCxx_close;
+ ee_dev.read = ee24LCxx_read;
+ ee_dev.write = ee24LCxx_write;
+ ee_dev.control = ee24LCxx_control;
+ ee_dev.type = RT_Device_Class_Unknown;
- rt_device_register(&ee_dev, "eeprom", RT_DEVICE_FLAG_RDWR);
+ rt_device_register(&ee_dev, "eeprom", RT_DEVICE_FLAG_RDWR);
}
void dump_ee(void)
{
- rt_device_t dev;
- char buf[EE_MEM_SIZE];
- int i, j;
+ rt_device_t dev;
+ char buf[EE_MEM_SIZE];
+ int i, j;
- dev = rt_device_find("eeprom");
- rt_device_read(dev, 0, buf, EE_MEM_SIZE );
+ dev = rt_device_find("eeprom");
+ rt_device_read(dev, 0, buf, EE_MEM_SIZE );
- for (i = 0; i < 16; i++)
- {
- for (j = 0; j < 16; j++)
- {
- rt_kprintf("0x%02X ", buf[ i*16+ j]);
- }
- rt_kprintf("\n");
- }
+ for (i = 0; i < 16; i++)
+ {
+ for (j = 0; j < 16; j++)
+ {
+ rt_kprintf("0x%02X ", buf[ i*16+ j]);
+ }
+ rt_kprintf("\n");
+ }
}
void ee_reset(void)
{
- char buf[EE_MEM_SIZE], read[EE_MEM_SIZE];
- int i;
- rt_device_t dev = rt_device_find("eeprom");
+ char buf[EE_MEM_SIZE], read[EE_MEM_SIZE];
+ int i;
+ rt_device_t dev = rt_device_find("eeprom");
- for (i = 0; i < EE_MEM_SIZE; i++)
- {
- buf[i] = 0xFF;
- read[i] = 0;
- }
- if (rt_device_write(dev, 0, buf, EE_MEM_SIZE ) == EE_MEM_SIZE)
- rt_kprintf("Write Success\n");
+ for (i = 0; i < EE_MEM_SIZE; i++)
+ {
+ buf[i] = 0xFF;
+ read[i] = 0;
+ }
+ if (rt_device_write(dev, 0, buf, EE_MEM_SIZE ) == EE_MEM_SIZE)
+ rt_kprintf("Write Success\n");
- rt_device_read(dev, 0, read, EE_MEM_SIZE );
+ rt_device_read(dev, 0, read, EE_MEM_SIZE );
- for (i = 0; i < EE_MEM_SIZE; i++)
- {
- if (buf[i] != read[i])
- rt_kprintf("EE Failed %X != %X at %d\n", buf[i], read[i], i);
- }
+ for (i = 0; i < EE_MEM_SIZE; i++)
+ {
+ if (buf[i] != read[i])
+ rt_kprintf("EE Failed %X != %X at %d\n", buf[i], read[i], i);
+ }
}
#ifdef RT_USING_FINSH
diff --git a/bsp/stm32f20x/Drivers/FM25Lx.c b/bsp/stm32f20x/Drivers/FM25Lx.c
index b1437d7707..e59af25fd4 100644
--- a/bsp/stm32f20x/Drivers/FM25Lx.c
+++ b/bsp/stm32f20x/Drivers/FM25Lx.c
@@ -26,7 +26,7 @@ void rt_hw_spi2_baud_rate(uint16_t SPI_BaudRatePrescaler)
/* FM25L256 using SPI2 */
void fm25_spi_cfg()
{
- GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
SPI_InitTypeDef SPI_InitStructure;
/* Enable SPI Periph clock */
@@ -36,24 +36,24 @@ void fm25_spi_cfg()
//Setup GPIO
GPIO_InitStructure.GPIO_Pin = FM25_SPI_SCK | FM25_SPI_MISO | FM25_SPI_MOSI;
- /*Connect Pin to AF*/
- GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource3, GPIO_AF_SPI3);
- GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource4, GPIO_AF_SPI3);
- GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource5, GPIO_AF_SPI3);
+ /*Connect Pin to AF*/
+ GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource3, GPIO_AF_SPI3);
+ GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource4, GPIO_AF_SPI3);
+ GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource5, GPIO_AF_SPI3);
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
- GPIO_Init(FM25_SPI_GPIO, &GPIO_InitStructure);
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+ GPIO_Init(FM25_SPI_GPIO, &GPIO_InitStructure);
- /* CS pin: PB12 */
+ /* CS pin: PB12 */
GPIO_InitStructure.GPIO_Pin = FM25_SPI_NSS_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(FM25_SPI_NSS_GPIO, &GPIO_InitStructure);
- CS_HIGH();
+ CS_HIGH();
- SPI_Cmd(FM25_SPI, DISABLE);
+ SPI_Cmd(FM25_SPI, DISABLE);
/*------------------------ SPI configuration ------------------------*/
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
@@ -72,23 +72,23 @@ void fm25_spi_cfg()
SPI_Cmd(FM25_SPI, ENABLE);
//SPI_CalculateCRC(FM25_SPI, DISABLE);
- fram_lock = rt_sem_create("framlock", 1, RT_IPC_FLAG_FIFO);
+ fram_lock = rt_sem_create("framlock", 1, RT_IPC_FLAG_FIFO);
}
static uint8_t spi_readwrite(uint8_t data)
{
int32_t timeout = 0xFFFFF;
- //rt_kprintf("State 0x%X\n", SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE));
- //Wait until the transmit buffer is empty
+ //rt_kprintf("State 0x%X\n", SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE));
+ //Wait until the transmit buffer is empty
while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE) == RESET && --timeout >0);
- if( timeout <= 0 ){ spi_timeout_cnt++; return 0;}
+ if( timeout <= 0 ){ spi_timeout_cnt++; return 0;}
// Send the byte
SPI_I2S_SendData(FM25_SPI, data);
- timeout = 0xFFFFF;
+ timeout = 0xFFFFF;
//Wait until a data is received
while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_RXNE) == RESET && --timeout >0);
- if( timeout <= 0 ){ spi_timeout_cnt++; return 0;}
+ if( timeout <= 0 ){ spi_timeout_cnt++; return 0;}
// Get the received data
data = SPI_I2S_ReceiveData(FM25_SPI);
@@ -110,29 +110,29 @@ rt_size_t fm25_read(rt_device_t dev, rt_off_t offset, void * buf, rt_size_t size
{
uint32_t index;
- uint8_t *buffer = (uint8_t*) buf;
+ uint8_t *buffer = (uint8_t*) buf;
fram_lock();
//spi_config();
- //rt_kprintf("READ: %d, size=%d\n", offset, size);
+ //rt_kprintf("READ: %d, size=%d\n", offset, size);
CS_LOW();
- spi_readwrite( FM25_READ);
- spi_readwrite( (offset >> 8)&0xFF );
- spi_readwrite( offset & 0xFF );
+ spi_readwrite( FM25_READ);
+ spi_readwrite( (offset >> 8)&0xFF );
+ spi_readwrite( offset & 0xFF );
for(index=0; index 0 )
- {
- fram_unlock();
- spi_timeout_cnt = 0;
- rt_kprintf("Read time out\n");
- return -1;
- }
+ if( spi_timeout_cnt > 0 )
+ {
+ fram_unlock();
+ spi_timeout_cnt = 0;
+ rt_kprintf("Read time out\n");
+ return -1;
+ }
- offset++;
+ offset++;
}
CS_HIGH();
@@ -145,33 +145,33 @@ rt_size_t fm25_write(rt_device_t dev, rt_off_t offset, const void * buf, rt_size
{
uint32_t index = size;
- uint8_t *buffer = (uint8_t*) buf;
+ uint8_t *buffer = (uint8_t*) buf;
fram_lock();
//spi_config();
- //rt_kprintf("WRITE: %d, size=%d\n", offset, size);
- CS_LOW();
+ //rt_kprintf("WRITE: %d, size=%d\n", offset, size);
+ CS_LOW();
spi_readwrite( FM25_WREN );
- CS_HIGH();
- CS_LOW();
- spi_readwrite( FM25_WRITE);
- spi_readwrite( (offset >> 8)&0xFF );
- spi_readwrite( offset & 0xFF );
- while( index > 0 )
- {
- spi_readwrite( *buffer++ );
-
- if( spi_timeout_cnt > 0 )
- {
- fram_unlock();
- rt_kprintf("Write time out\n");
- spi_timeout_cnt = 0;
- return -1;
- }
- index--;
- offset++;
- }
CS_HIGH();
- //rt_thread_delay(100);
+ CS_LOW();
+ spi_readwrite( FM25_WRITE);
+ spi_readwrite( (offset >> 8)&0xFF );
+ spi_readwrite( offset & 0xFF );
+ while( index > 0 )
+ {
+ spi_readwrite( *buffer++ );
+
+ if( spi_timeout_cnt > 0 )
+ {
+ fram_unlock();
+ rt_kprintf("Write time out\n");
+ spi_timeout_cnt = 0;
+ return -1;
+ }
+ index--;
+ offset++;
+ }
+ CS_HIGH();
+ //rt_thread_delay(100);
fram_unlock();
@@ -179,36 +179,36 @@ rt_size_t fm25_write(rt_device_t dev, rt_off_t offset, const void * buf, rt_size
}
static rt_err_t fm25_init(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t fm25_open(rt_device_t dev, rt_uint16_t oflag)
{
- char i;
- SPI_Cmd(FM25_SPI, ENABLE);
+ char i;
+ SPI_Cmd(FM25_SPI, ENABLE);
- if( oflag != RT_DEVICE_FLAG_RDONLY )
- {
- CS_LOW();
- spi_readwrite( FM25_WRSR );
- spi_readwrite( FM25_WPEN );
- CS_HIGH();
- //rt_kprintf("RDSR=0x%X\n", fm25_read_status());
+ if( oflag != RT_DEVICE_FLAG_RDONLY )
+ {
+ CS_LOW();
+ spi_readwrite( FM25_WRSR );
+ spi_readwrite( FM25_WPEN );
+ CS_HIGH();
+ //rt_kprintf("RDSR=0x%X\n", fm25_read_status());
- }
- return RT_EOK;
+ }
+ return RT_EOK;
}
static rt_err_t fm25_close(rt_device_t dev)
{
- CS_LOW();
+ CS_LOW();
spi_readwrite( FM25_WRDI );
CS_HIGH();
- SPI_Cmd(FM25_SPI, DISABLE);
+ SPI_Cmd(FM25_SPI, DISABLE);
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args)
{
- RT_ASSERT(dev != RT_NULL);
+ RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
@@ -219,30 +219,30 @@ static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args)
geometry->bytes_per_sector = 1;
geometry->block_size = 1;
- geometry->sector_count = 8192;
-
+ geometry->sector_count = 8192;
+
}
- return RT_EOK;
+ return RT_EOK;
}
-static struct rt_device spi_flash_device;
+static struct rt_device spi_flash_device;
void fm25_hw_init()
{
- int i = 0xFFFFF;
- fm25_spi_cfg();
+ int i = 0xFFFFF;
+ fm25_spi_cfg();
- while(i--);
- //spi_config();
- CS_LOW();
+ while(i--);
+ //spi_config();
+ CS_LOW();
spi_readwrite( FM25_WRDI );
CS_HIGH();
- spi_flash_device.type = RT_Device_Class_Block;
+ spi_flash_device.type = RT_Device_Class_Block;
spi_flash_device.init = fm25_init;
spi_flash_device.open = fm25_open;
spi_flash_device.close = fm25_close;
- spi_flash_device.read = fm25_read;
+ spi_flash_device.read = fm25_read;
spi_flash_device.write = fm25_write;
spi_flash_device.control = fm25_control;
/* no private */
@@ -255,17 +255,17 @@ void fm25_hw_init()
int fram_test(int x)
{
- //rt_kprintf("SR=0x%X\nCR1=0x%X\nCR2=0x%X\n", FM25_SPI->SR, FM25_SPI->CR1,FM25_SPI->CR2);
- rt_device_t device = RT_NULL;
- char buf[256];
- char read[256];
- int i, j;
+ //rt_kprintf("SR=0x%X\nCR1=0x%X\nCR2=0x%X\n", FM25_SPI->SR, FM25_SPI->CR1,FM25_SPI->CR2);
+ rt_device_t device = RT_NULL;
+ char buf[256];
+ char read[256];
+ int i, j;
- for(i =0; i< 256; i++ )
- {
- buf[i] = i;
- read[i] = 0;
- }
+ for(i =0; i< 256; i++ )
+ {
+ buf[i] = i;
+ read[i] = 0;
+ }
// step 1:find device
device = rt_device_find("fram0");
if( device == RT_NULL)
@@ -273,22 +273,22 @@ int fram_test(int x)
rt_kprintf("device %s: not found!\r\n");
return RT_ERROR;
}
- device->open(device,RT_DEVICE_FLAG_RDWR);
+ device->open(device,RT_DEVICE_FLAG_RDWR);
- for( j = 0; j < FM25_MAXSIZE; j+= 256 )
- //j = 256*x;
- {
- //rt_kprintf("RDSR=0x%X\n", fm25_read_status());
- device->write(device,j, buf,256);
- device->read(device,j, read,256);
- for(i =0; i< 256; i++ )
- {
- if( buf[i] != read[i] )
- rt_kprintf("error at %d: %d!=%d\n", i, buf[i], read[i]);
- }
- }
- device->close(device);
- rt_kprintf("Finsh test\n");
+ for( j = 0; j < FM25_MAXSIZE; j+= 256 )
+ //j = 256*x;
+ {
+ //rt_kprintf("RDSR=0x%X\n", fm25_read_status());
+ device->write(device,j, buf,256);
+ device->read(device,j, read,256);
+ for(i =0; i< 256; i++ )
+ {
+ if( buf[i] != read[i] )
+ rt_kprintf("error at %d: %d!=%d\n", i, buf[i], read[i]);
+ }
+ }
+ device->close(device);
+ rt_kprintf("Finsh test\n");
}
#ifdef RT_USING_FINSH
#include
diff --git a/bsp/stm32f20x/Drivers/FM25Lx.h b/bsp/stm32f20x/Drivers/FM25Lx.h
index 3f714ac8da..6d7e9ec08a 100644
--- a/bsp/stm32f20x/Drivers/FM25Lx.h
+++ b/bsp/stm32f20x/Drivers/FM25Lx.h
@@ -1,14 +1,14 @@
#ifndef FM25LX_H
#define FM25LX_H
-#define FM25_WREN 0x06
-#define FM25_WRDI 0x04
-#define FM25_RDSR 0x05
-#define FM25_WRSR 0x01
-#define FM25_READ 0x03
-#define FM25_WRITE 0x02
-#define FM25_WEL 0x02
-#define FM25_WPEN 0x80
+#define FM25_WREN 0x06
+#define FM25_WRDI 0x04
+#define FM25_RDSR 0x05
+#define FM25_WRSR 0x01
+#define FM25_READ 0x03
+#define FM25_WRITE 0x02
+#define FM25_WEL 0x02
+#define FM25_WPEN 0x80
#define FM25CL64B
//#define FM25LC256
@@ -19,25 +19,25 @@
#define FM25_MAXSIZE 32768
#endif
-#define FM25_SPI SPI3
-#define FM25_SPI_GPIO GPIOB
-#define FM25_SPI_MOSI GPIO_Pin_5
-#define FM25_SPI_MISO GPIO_Pin_4
-#define FM25_SPI_SCK GPIO_Pin_3
-#define FM25_SPI_NSS_GPIO GPIOD
-#define FM25_SPI_NSS_PIN GPIO_Pin_10
-#define FM25_SPI_CLK RCC_APB1Periph_SPI3
-#define FM25_SPI_GPIO_CLK RCC_AHB1Periph_GPIOB
-#define FM25_SPI_NSS_GPIO_CLK RCC_AHB1Periph_GPIOD
+#define FM25_SPI SPI3
+#define FM25_SPI_GPIO GPIOB
+#define FM25_SPI_MOSI GPIO_Pin_5
+#define FM25_SPI_MISO GPIO_Pin_4
+#define FM25_SPI_SCK GPIO_Pin_3
+#define FM25_SPI_NSS_GPIO GPIOD
+#define FM25_SPI_NSS_PIN GPIO_Pin_10
+#define FM25_SPI_CLK RCC_APB1Periph_SPI3
+#define FM25_SPI_GPIO_CLK RCC_AHB1Periph_GPIOB
+#define FM25_SPI_NSS_GPIO_CLK RCC_AHB1Periph_GPIOD
-#define FM25_SPI_DMA_CLK RCC_AHB1Periph_DMA1
-#define FM25_SPI_DMA_Channel DMA_Channel_0
-#define FM25_SPI_RX_DMA_Stream DMA1_Stream0
-#define FM25_SPI_RX_DMA_IRQ DMA1_Stream0_IRQn
+#define FM25_SPI_DMA_CLK RCC_AHB1Periph_DMA1
+#define FM25_SPI_DMA_Channel DMA_Channel_0
+#define FM25_SPI_RX_DMA_Stream DMA1_Stream0
+#define FM25_SPI_RX_DMA_IRQ DMA1_Stream0_IRQn
#define FM25_SPI_RX_DMA_FLAG DMA_IT_TCIF0
-#define FM25_SPI_TX_DMA_Stream DMA1_Stream5
-#define FM25_SPI_TX_DMA_IRQ DMA1_Stream5_IRQn
+#define FM25_SPI_TX_DMA_Stream DMA1_Stream5
+#define FM25_SPI_TX_DMA_IRQ DMA1_Stream5_IRQn
#define FM25_SPI_TX_DMA_FLAG DMA_IT_TCIF5
-#define FM25_SPI_DR_Base 0x4003C00C
+#define FM25_SPI_DR_Base 0x4003C00C
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/stm32f20x/Drivers/board.c b/bsp/stm32f20x/Drivers/board.c
index e3cfdbbc12..0b2d214540 100644
--- a/bsp/stm32f20x/Drivers/board.c
+++ b/bsp/stm32f20x/Drivers/board.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -30,16 +30,16 @@
void SD_LowLevel_DeInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
-
+
/*!< Disable SDIO Clock */
SDIO_ClockCmd(DISABLE);
-
+
/*!< Set Power State to OFF */
SDIO_SetPowerState(SDIO_PowerState_OFF);
/*!< DeInitializes the SDIO peripheral */
SDIO_DeInit();
-
+
/* Disable the SDIO APB2 Clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE);
@@ -66,7 +66,7 @@ void SD_LowLevel_DeInit(void)
}
/**
- * @brief Initializes the SD Card and put it into StandBy State (Ready for
+ * @brief Initializes the SD Card and put it into StandBy State (Ready for
* data transfer).
* @param None
* @retval None
@@ -101,7 +101,7 @@ void SD_LowLevel_Init(void)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOC, &GPIO_InitStructure);
-
+
/*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
@@ -154,7 +154,7 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
/* DMA2 Stream3 or Stream6 enable */
DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE);
-
+
}
/**
@@ -219,11 +219,11 @@ uint32_t SD_DMAEndOfTransferStatus(void)
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
- /* Set the Vector Table base location at 0x20000000 */
- NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+ /* Set the Vector Table base location at 0x20000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else /* VECT_TAB_FLASH */
- /* Set the Vector Table base location at 0x08000000 */
- NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+ /* Set the Vector Table base location at 0x08000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
}
@@ -236,15 +236,15 @@ void NVIC_Configuration(void)
*******************************************************************************/
void SysTick_Configuration(void)
{
- RCC_ClocksTypeDef rcc_clocks;
- rt_uint32_t cnts;
+ RCC_ClocksTypeDef rcc_clocks;
+ rt_uint32_t cnts;
- RCC_GetClocksFreq(&rcc_clocks);
+ RCC_GetClocksFreq(&rcc_clocks);
- cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+ cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
- SysTick_Config(cnts);
- SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+ SysTick_Config(cnts);
+ SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
}
/**
@@ -253,13 +253,13 @@ void SysTick_Configuration(void)
*/
void SysTick_Handler(void)
{
- /* enter interrupt */
- rt_interrupt_enter();
+ /* enter interrupt */
+ rt_interrupt_enter();
- rt_tick_increase();
+ rt_tick_increase();
- /* leave interrupt */
- rt_interrupt_leave();
+ /* leave interrupt */
+ rt_interrupt_leave();
}
/**
@@ -267,15 +267,15 @@ void SysTick_Handler(void)
*/
void rt_hw_board_init()
{
- /* NVIC Configuration */
- NVIC_Configuration();
+ /* NVIC Configuration */
+ NVIC_Configuration();
- /* Configure the SysTick */
- SysTick_Configuration();
+ /* Configure the SysTick */
+ SysTick_Configuration();
- rt_hw_usart_init();
+ rt_hw_usart_init();
#ifdef RT_USING_CONSOLE
- rt_console_set_device(CONSOLE_DEVICE);
+ rt_console_set_device(CONSOLE_DEVICE);
#endif
}
diff --git a/bsp/stm32f20x/Drivers/board.h b/bsp/stm32f20x/Drivers/board.h
index 63a97b6b1c..9b58dd81c7 100644
--- a/bsp/stm32f20x/Drivers/board.h
+++ b/bsp/stm32f20x/Drivers/board.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -16,32 +16,32 @@
/* board configuration */
// SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
-// Default: 1
-#define STM32_USE_SDIO 1
+// Default: 1
+#define STM32_USE_SDIO 1
/* whether use board external SRAM memory */
// Use external SRAM memory on the board
-// Enable External SRAM memory
+// Enable External SRAM memory
#define STM32_EXT_SRAM 0
-// Begin Address of External SRAM
-// Default: 0x68000000
+// Begin Address of External SRAM
+// Default: 0x68000000
#define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */
-// End Address of External SRAM
-// Default: 0x68080000
+// End Address of External SRAM
+// Default: 0x68080000
#define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */
//
// Internal SRAM memory size[Kbytes] <8-128>
-// Default: 64
+// Default: 64
#define STM32_SRAM_SIZE 128
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
// Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
-// Default: 1
-#define STM32_CONSOLE_USART 1
+// Default: 1
+#define STM32_CONSOLE_USART 1
// Ethernet Interface: <0=> Microchip ENC28J60
-#define STM32_ETH_IF 0
+#define STM32_ETH_IF 0
void rt_hw_board_led_on(int n);
void rt_hw_board_led_off(int n);
@@ -64,21 +64,21 @@ void rt_hw_board_init(void);
#define SD_DETECT_PIN GPIO_Pin_0 /* PB.0 */
#define SD_DETECT_GPIO_PORT GPIOB /* GPIOB */
#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOB
-
+
#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
-/**
+/**
* @brief SDIO Intialization Frequency (400KHz max)
*/
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
-/**
- * @brief SDIO Data Transfer Frequency (25MHz max)
+/**
+ * @brief SDIO Data Transfer Frequency (25MHz max)
*/
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
#define SD_SDIO_DMA DMA2
#define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2
-
-#define SD_SDIO_DMA_STREAM3 3
+
+#define SD_SDIO_DMA_STREAM3 3
//#define SD_SDIO_DMA_STREAM6 6
#ifdef SD_SDIO_DMA_STREAM3
@@ -88,7 +88,7 @@ void rt_hw_board_init(void);
#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3
#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3
#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3
- #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3
+ #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3
#elif defined SD_SDIO_DMA_STREAM6
#define SD_SDIO_DMA_STREAM DMA2_Stream6
#define SD_SDIO_DMA_CHANNEL DMA_Channel_4
@@ -96,11 +96,11 @@ void rt_hw_board_init(void);
#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6
#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6
#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6
- #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6
+ #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6
#endif /* SD_SDIO_DMA_STREAM3 */
void SD_LowLevel_DeInit(void);
-void SD_LowLevel_Init(void);
+void SD_LowLevel_Init(void);
void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize);
void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize);
diff --git a/bsp/stm32f20x/Drivers/drv_rtc.c b/bsp/stm32f20x/Drivers/drv_rtc.c
index 6078a15249..4e5093ee53 100644
--- a/bsp/stm32f20x/Drivers/drv_rtc.c
+++ b/bsp/stm32f20x/Drivers/drv_rtc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -43,20 +43,20 @@ static struct rt_device rtc;
static time_t rt_mktime(struct tm *tm)
{
- long res;
- int year;
- year = tm->tm_year - 70;
+ long res;
+ int year;
+ year = tm->tm_year - 70;
- res = YEAR * year + DAY * ((year + 1) / 4);
- res += month[tm->tm_mon];
+ res = YEAR * year + DAY * ((year + 1) / 4);
+ res += month[tm->tm_mon];
- if (tm->tm_mon > 1 && ((year + 2) % 4))
- res -= DAY;
- res += DAY * (tm->tm_mday - 1);
- res += HOUR * tm->tm_hour;
- res += MINUTE * tm->tm_min;
- res += tm->tm_sec;
- return res;
+ if (tm->tm_mon > 1 && ((year + 2) % 4))
+ res -= DAY;
+ res += DAY * (tm->tm_mday - 1);
+ res += HOUR * tm->tm_hour;
+ res += MINUTE * tm->tm_min;
+ res += tm->tm_sec;
+ return res;
}
static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
@@ -76,7 +76,7 @@ static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_siz
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{
time_t *time;
- struct tm ti,*to;
+ struct tm ti,*to;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
@@ -84,17 +84,17 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
case RT_DEVICE_CTRL_RTC_GET_TIME:
time = (time_t *)args;
/* read device */
- //RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStructure, &RTC_DateStructure);
- RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure);
- RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure);
- ti.tm_sec = RTC_TimeStructure.RTC_Seconds;
- ti.tm_min = RTC_TimeStructure.RTC_Minutes;
- ti.tm_hour = RTC_TimeStructure.RTC_Hours;
- //ti.tm_wday = (RTC_DateStructure.RTC_WeekDay==7)?0:RTC_DateStructure.RTC_WeekDay;
- ti.tm_mon = RTC_DateStructure.RTC_Month -1;
- ti.tm_mday = RTC_DateStructure.RTC_Date;
- ti.tm_year = RTC_DateStructure.RTC_Year + 70;
- *time = rt_mktime(&ti);
+ //RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStructure, &RTC_DateStructure);
+ RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure);
+ RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure);
+ ti.tm_sec = RTC_TimeStructure.RTC_Seconds;
+ ti.tm_min = RTC_TimeStructure.RTC_Minutes;
+ ti.tm_hour = RTC_TimeStructure.RTC_Hours;
+ //ti.tm_wday = (RTC_DateStructure.RTC_WeekDay==7)?0:RTC_DateStructure.RTC_WeekDay;
+ ti.tm_mon = RTC_DateStructure.RTC_Month -1;
+ ti.tm_mday = RTC_DateStructure.RTC_Date;
+ ti.tm_year = RTC_DateStructure.RTC_Year + 70;
+ *time = rt_mktime(&ti);
//*time = RTC_GetCounter();
break;
@@ -104,10 +104,10 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
time = (time_t *)args;
/* Enable the PWR clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
- /* Allow access to RTC */
- PWR_BackupAccessCmd(ENABLE);
+ /* Allow access to RTC */
+ PWR_BackupAccessCmd(ENABLE);
/* Wait until last write operation on RTC registers has finished */
//RTC_WaitForLastTask();
@@ -115,22 +115,22 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
/* Change the current time */
//RTC_SetCounter(*time);
- to = gmtime(time);
- RTC_TimeStructure.RTC_Seconds = to->tm_sec;
- RTC_TimeStructure.RTC_Minutes = to->tm_min;
- RTC_TimeStructure.RTC_Hours = to->tm_hour;
- //RTC_DateStructure.RTC_WeekDay =(ti->tm_wday==0)?7:ti->tm_wday;
- RTC_DateStructure.RTC_Month = to->tm_mon + 1;
- RTC_DateStructure.RTC_Date = to->tm_mday;
- RTC_DateStructure.RTC_Year = to->tm_year - 70;
- RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure);
- RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure);
+ to = gmtime(time);
+ RTC_TimeStructure.RTC_Seconds = to->tm_sec;
+ RTC_TimeStructure.RTC_Minutes = to->tm_min;
+ RTC_TimeStructure.RTC_Hours = to->tm_hour;
+ //RTC_DateStructure.RTC_WeekDay =(ti->tm_wday==0)?7:ti->tm_wday;
+ RTC_DateStructure.RTC_Month = to->tm_mon + 1;
+ RTC_DateStructure.RTC_Date = to->tm_mday;
+ RTC_DateStructure.RTC_Year = to->tm_year - 70;
+ RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure);
+ RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure);
/* Wait until last write operation on RTC registers has finished */
//RTC_WaitForLastTask();
RTC_WriteBackupRegister(RTC_BKP_DR1, 0xA5A5);
- //BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
+ //BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
}
break;
}
@@ -147,75 +147,75 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
*******************************************************************************/
int RTC_Config(void)
{
- u32 count=0x200000;
- /* Enable the PWR clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+ u32 count=0x200000;
+ /* Enable the PWR clock */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
- /* Allow access to RTC */
- PWR_BackupAccessCmd(ENABLE);
+ /* Allow access to RTC */
+ PWR_BackupAccessCmd(ENABLE);
- RCC_LSEConfig(RCC_LSE_ON);
+ RCC_LSEConfig(RCC_LSE_ON);
- /* Wait till LSE is ready */
- while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) );
+ /* Wait till LSE is ready */
+ while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) );
if ( count == 0 )
{
return -1;
}
- /* Select the RTC Clock Source */
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+ /* Select the RTC Clock Source */
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
- SynchPrediv = 0xFF;
- AsynchPrediv = 0x7F;
+ SynchPrediv = 0xFF;
+ AsynchPrediv = 0x7F;
- /* Enable the RTC Clock */
- RCC_RTCCLKCmd(ENABLE);
+ /* Enable the RTC Clock */
+ RCC_RTCCLKCmd(ENABLE);
- /* Wait for RTC APB registers synchronisation */
- RTC_WaitForSynchro();
+ /* Wait for RTC APB registers synchronisation */
+ RTC_WaitForSynchro();
- /* Enable The TimeStamp */
- //RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE);
+ /* Enable The TimeStamp */
+ //RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE);
- return 0;
+ return 0;
}
int RTC_Configuration(void)
{
- if(RTC_Config() < 0 )
- return -1;
+ if(RTC_Config() < 0 )
+ return -1;
- /* Set the Time */
- RTC_TimeStructure.RTC_Hours = 0;
- RTC_TimeStructure.RTC_Minutes = 0;
- RTC_TimeStructure.RTC_Seconds = 0;
+ /* Set the Time */
+ RTC_TimeStructure.RTC_Hours = 0;
+ RTC_TimeStructure.RTC_Minutes = 0;
+ RTC_TimeStructure.RTC_Seconds = 0;
- /* Set the Date */
- RTC_DateStructure.RTC_Month = 1;
- RTC_DateStructure.RTC_Date = 1;
- RTC_DateStructure.RTC_Year = 0;
- RTC_DateStructure.RTC_WeekDay = 4;
+ /* Set the Date */
+ RTC_DateStructure.RTC_Month = 1;
+ RTC_DateStructure.RTC_Date = 1;
+ RTC_DateStructure.RTC_Year = 0;
+ RTC_DateStructure.RTC_WeekDay = 4;
- /* Calendar Configuration */
- RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv;
- RTC_InitStructure.RTC_SynchPrediv = SynchPrediv;
- RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24;
- RTC_Init(&RTC_InitStructure);
+ /* Calendar Configuration */
+ RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv;
+ RTC_InitStructure.RTC_SynchPrediv = SynchPrediv;
+ RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24;
+ RTC_Init(&RTC_InitStructure);
- /* Set Current Time and Date */
- RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure);
- RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure);
- if (RTC_Init(&RTC_InitStructure) == ERROR)
- return -1;
+ /* Set Current Time and Date */
+ RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure);
+ RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure);
+ if (RTC_Init(&RTC_InitStructure) == ERROR)
+ return -1;
return 0;
}
void rt_hw_rtc_init(void)
{
- rtc.type = RT_Device_Class_RTC;
+ rtc.type = RT_Device_Class_RTC;
if (RTC_ReadBackupRegister(RTC_BKP_DR1) != 0xA5A5)
{
@@ -234,11 +234,11 @@ void rt_hw_rtc_init(void)
}
/* register rtc device */
- rtc.init = RT_NULL;
- rtc.open = rt_rtc_open;
- rtc.close = RT_NULL;
- rtc.read = rt_rtc_read;
- rtc.write = RT_NULL;
+ rtc.init = RT_NULL;
+ rtc.open = rt_rtc_open;
+ rtc.close = RT_NULL;
+ rtc.read = rt_rtc_read;
+ rtc.write = RT_NULL;
rtc.control = rt_rtc_control;
/* no private */
diff --git a/bsp/stm32f20x/Drivers/drv_rtc.h b/bsp/stm32f20x/Drivers/drv_rtc.h
index 8f6c9a00a0..0d0ad288fc 100644
--- a/bsp/stm32f20x/Drivers/drv_rtc.h
+++ b/bsp/stm32f20x/Drivers/drv_rtc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/stm32f20x/Drivers/i2c.c b/bsp/stm32f20x/Drivers/i2c.c
index e1b4b02ffa..9b2f4ed866 100644
--- a/bsp/stm32f20x/Drivers/i2c.c
+++ b/bsp/stm32f20x/Drivers/i2c.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,15 +14,15 @@
#include "stm32f2xx_i2c.h"
#include "stm32f2xx_dma.h"
-#define EV_SB 1
-#define EV_ADDR (1<<1)
-#define EV_STOPF (1<<2)
-#define EV_BTF (1<<3)
-#define ERR_ARLO (1<<4)
-#define ERR_AF (1<<5)
-#define ERR_OVR (1<<6)
-#define ERR_PECERR (1<<7)
-#define ERR_BERR (1<<8)
+#define EV_SB 1
+#define EV_ADDR (1<<1)
+#define EV_STOPF (1<<2)
+#define EV_BTF (1<<3)
+#define ERR_ARLO (1<<4)
+#define ERR_AF (1<<5)
+#define ERR_OVR (1<<6)
+#define ERR_PECERR (1<<7)
+#define ERR_BERR (1<<8)
#define I2C_COMPLETE (1<<9)
#define I2C_BUSY 1
@@ -66,7 +66,7 @@ void dump_i2c_register(I2C_TypeDef* I2Cx)
else
I2C_TRACE("======I2C2======\n");
I2C_TRACE("CR1: 0x%x\tCR2: 0x%x\n", I2Cx->CR1, I2Cx->CR2);
- I2C_TRACE("SR1: 0x%x\tSR2: 0x%x\n", I2Cx->SR1, I2Cx->SR2);
+ I2C_TRACE("SR1: 0x%x\tSR2: 0x%x\n", I2Cx->SR1, I2Cx->SR2);
}
@@ -75,532 +75,532 @@ Status I2C_AcknowledgePolling(I2C_TypeDef* I2Cx ,uint8_t Addr)
{
uint32_t timeout = 0xFFFF, ret;
uint16_t tmp;
- ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER );
-
- if( ret == RT_EOK )
- {
- do{
- if( timeout-- <= 0 )
- {
- I2C_ClearFlag(I2Cx,I2C_FLAG_AF);
- I2Cx->CR1 |= CR1_STOP_Set;
- rt_mutex_release(i2c_mux);
- return Error;
- }
-
- I2Cx->CR1 |= CR1_START_Set;
- tmp = I2Cx->SR1;//MSB
- I2Cx->DR = Addr;
-
- }while((I2Cx->SR1&0x0002) != 0x0002);
-
- I2C_ClearFlag(I2Cx,I2C_FLAG_AF);
- I2Cx->CR1 |= CR1_STOP_Set;
- while ((I2Cx->CR1&0x200) == 0x200);
- rt_kprintf( "AcknowledgePolling OK\n");
- rt_mutex_release(i2c_mux);
- return Success;
- }
- else
- return Error;
-}
+ ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER );
-/*
- Only 1 byte READ using Interrupt or Polling otherwise using DMA
+ if( ret == RT_EOK )
+ {
+ do{
+ if( timeout-- <= 0 )
+ {
+ I2C_ClearFlag(I2Cx,I2C_FLAG_AF);
+ I2Cx->CR1 |= CR1_STOP_Set;
+ rt_mutex_release(i2c_mux);
+ return Error;
+ }
+
+ I2Cx->CR1 |= CR1_START_Set;
+ tmp = I2Cx->SR1;//MSB
+ I2Cx->DR = Addr;
+
+ }while((I2Cx->SR1&0x0002) != 0x0002);
+
+ I2C_ClearFlag(I2Cx,I2C_FLAG_AF);
+ I2Cx->CR1 |= CR1_STOP_Set;
+ while ((I2Cx->CR1&0x200) == 0x200);
+ rt_kprintf( "AcknowledgePolling OK\n");
+ rt_mutex_release(i2c_mux);
+ return Success;
+ }
+ else
+ return Error;
+}
+
+/*
+ Only 1 byte READ using Interrupt or Polling otherwise using DMA
*/
void I2C1_EV_IRQHandler()
{
- __IO uint16_t regSR1, regSR2;
- __IO uint32_t regSR;
- int i=10;
+ __IO uint16_t regSR1, regSR2;
+ __IO uint32_t regSR;
+ int i=10;
- rt_interrupt_enter();
- //rt_hw_led_on(10);
- regSR1 = I2C1->SR1;
- regSR2 = I2C1->SR2;
- regSR = (regSR2 << 16) | regSR1;
- //rt_kprintf("EV=> SR1: 0x%x\tSR2: 0x%x\tSR: 0x%x status: %d\n", regSR1, regSR2, regSR, i2cStatus);
-
- if( (regSR & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT) //EV5
- {
+ rt_interrupt_enter();
+ //rt_hw_led_on(10);
+ regSR1 = I2C1->SR1;
+ regSR2 = I2C1->SR2;
+ regSR = (regSR2 << 16) | regSR1;
+ //rt_kprintf("EV=> SR1: 0x%x\tSR2: 0x%x\tSR: 0x%x status: %d\n", regSR1, regSR2, regSR, i2cStatus);
- if( i2cStatus == S1 ) //Send TX Command
- {
- I2C1->DR = DevAddr & 0xFE;
- i2cStatus = S2;
- }
- else if( i2cStatus == S4 ) //Send RX Command
- {
- I2C1->DR = DevAddr | 0x01;
- i2cStatus = S5;
- }
+ if( (regSR & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT) //EV5
+ {
+
+ if( i2cStatus == S1 ) //Send TX Command
+ {
+ I2C1->DR = DevAddr & 0xFE;
+ i2cStatus = S2;
+ }
+ else if( i2cStatus == S4 ) //Send RX Command
+ {
+ I2C1->DR = DevAddr | 0x01;
+ i2cStatus = S5;
+ }
- regSR1 = 0;
- regSR2 = 0;
+ regSR1 = 0;
+ regSR2 = 0;
- }
- if( (regSR & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)== I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) //EV6
- {
- switch( i2cStatus )
- {
- case S2: //Send 1st memory address phase
- {
- //I2C_DMACmd(I2C1, ENABLE);
- I2C1->DR = MemAddr[0];
- if( memtype == I2C_MEM_1Byte )
- i2cStatus = S2_2;
- else if( memtype == I2C_MEM_2Bytes )
- i2cStatus = S2_1;
- }
- break;
- case S5: //Set RX buffer phase
- {
- if( i2cFlag == I2C_READ_DMA )
- {
- I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_RX);
- I2C1->CR2 |= CR2_LAST_Set | CR2_DMAEN_Set;
- DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
- }
- else if( i2cFlag == I2C_READ_INTERRUPT )
- {
- I2C1->CR2 |= I2C_IT_BUF;
- I2C1->CR1 &= CR1_ACK_Reset;
- /* Program the STOP */
- I2C1->CR1 |= CR1_STOP_Set;
- }
- i2cStatus = S6;
- }
- break;
- }
-
- regSR1 = 0;
- regSR2 = 0;
- //dump_i2c_register(I2C1);
- }
- if((regSR & I2C_EVENT_MASTER_BYTE_RECEIVED) == I2C_EVENT_MASTER_BYTE_RECEIVED) //EV7
- {
- //Interrupt RX complete phase
- if( i2cStatus == S6 && i2cFlag == I2C_READ_INTERRUPT )
- {
- *i2c_buf = I2C1->DR;
- i2cStatus = S_STOP;
- rt_event_send(&i2c_event, I2C_COMPLETE);
- }
- }
- if( (regSR & I2C_EVENT_MASTER_BYTE_TRANSMITTED) == I2C_EVENT_MASTER_BYTE_TRANSMITTED ) //EV8_2
- {
- //Start TX/RX phase
- if(i2cStatus == S3)
- {
- DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 );
- DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
- switch (i2cFlag)
- {
- case I2C_WRITE:
- i2cStatus = S_STOP;
- I2C1->CR1 |= CR1_STOP_Set;
- rt_event_send(&i2c_event, I2C_COMPLETE);
- break;
+ }
+ if( (regSR & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)== I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) //EV6
+ {
+ switch( i2cStatus )
+ {
+ case S2: //Send 1st memory address phase
+ {
+ //I2C_DMACmd(I2C1, ENABLE);
+ I2C1->DR = MemAddr[0];
+ if( memtype == I2C_MEM_1Byte )
+ i2cStatus = S2_2;
+ else if( memtype == I2C_MEM_2Bytes )
+ i2cStatus = S2_1;
+ }
+ break;
+ case S5: //Set RX buffer phase
+ {
+ if( i2cFlag == I2C_READ_DMA )
+ {
+ I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_RX);
+ I2C1->CR2 |= CR2_LAST_Set | CR2_DMAEN_Set;
+ DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
+ }
+ else if( i2cFlag == I2C_READ_INTERRUPT )
+ {
+ I2C1->CR2 |= I2C_IT_BUF;
+ I2C1->CR1 &= CR1_ACK_Reset;
+ /* Program the STOP */
+ I2C1->CR1 |= CR1_STOP_Set;
+ }
+ i2cStatus = S6;
+ }
+ break;
+ }
- case I2C_READ_DMA:
- i2cStatus = S4;
- I2C1->CR1 |= CR1_START_Set;
- break;
+ regSR1 = 0;
+ regSR2 = 0;
+ //dump_i2c_register(I2C1);
+ }
+ if((regSR & I2C_EVENT_MASTER_BYTE_RECEIVED) == I2C_EVENT_MASTER_BYTE_RECEIVED) //EV7
+ {
+ //Interrupt RX complete phase
+ if( i2cStatus == S6 && i2cFlag == I2C_READ_INTERRUPT )
+ {
+ *i2c_buf = I2C1->DR;
+ i2cStatus = S_STOP;
+ rt_event_send(&i2c_event, I2C_COMPLETE);
+ }
+ }
+ if( (regSR & I2C_EVENT_MASTER_BYTE_TRANSMITTED) == I2C_EVENT_MASTER_BYTE_TRANSMITTED ) //EV8_2
+ {
+ //Start TX/RX phase
+ if(i2cStatus == S3)
+ {
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 );
+ DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
+ switch (i2cFlag)
+ {
+ case I2C_WRITE:
+ i2cStatus = S_STOP;
+ I2C1->CR1 |= CR1_STOP_Set;
+ rt_event_send(&i2c_event, I2C_COMPLETE);
+ break;
- case I2C_READ_POLLING:
- i2cStatus = S_STOP;
- rt_event_send(&i2c_event, I2C_COMPLETE);
- I2C1->CR2 &= ~(CR2_LAST_Set | I2C_IT_EVT | CR2_DMAEN_Set);
- I2C1->CR1 |= CR1_START_Set;
- break;
+ case I2C_READ_DMA:
+ i2cStatus = S4;
+ I2C1->CR1 |= CR1_START_Set;
+ break;
- case I2C_READ_INTERRUPT:
- i2cStatus = S4;
- I2C1->CR1 |= CR1_START_Set;
- break;
- }
- }
- if( i2cStatus == S2_1 ) //Send 2nd memory address
- {
- if( memtype == I2C_MEM_2Bytes ) //memory address has 2 bytes
- {
- I2C1->DR = MemAddr[1];
- i2cStatus = S2_2;
- }
- if( i2cFlag == I2C_READ_POLLING || i2cFlag == I2C_READ_DMA || i2cFlag == I2C_READ_INTERRUPT)
- {
- i2cStatus = S3;
- }
- }
- if( i2cStatus == S2_2 ) //Set TX DAM phase
- {
- I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_TX);
- I2C1->CR2 |= CR2_DMAEN_Set;
- i2cStatus = S3;
- }
- }
+ case I2C_READ_POLLING:
+ i2cStatus = S_STOP;
+ rt_event_send(&i2c_event, I2C_COMPLETE);
+ I2C1->CR2 &= ~(CR2_LAST_Set | I2C_IT_EVT | CR2_DMAEN_Set);
+ I2C1->CR1 |= CR1_START_Set;
+ break;
- rt_interrupt_leave();
+ case I2C_READ_INTERRUPT:
+ i2cStatus = S4;
+ I2C1->CR1 |= CR1_START_Set;
+ break;
+ }
+ }
+ if( i2cStatus == S2_1 ) //Send 2nd memory address
+ {
+ if( memtype == I2C_MEM_2Bytes ) //memory address has 2 bytes
+ {
+ I2C1->DR = MemAddr[1];
+ i2cStatus = S2_2;
+ }
+ if( i2cFlag == I2C_READ_POLLING || i2cFlag == I2C_READ_DMA || i2cFlag == I2C_READ_INTERRUPT)
+ {
+ i2cStatus = S3;
+ }
+ }
+ if( i2cStatus == S2_2 ) //Set TX DAM phase
+ {
+ I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_TX);
+ I2C1->CR2 |= CR2_DMAEN_Set;
+ i2cStatus = S3;
+ }
+ }
+
+ rt_interrupt_leave();
}
void DMA1_Stream6_IRQHandler(void) //I2C1 TX
{
- rt_interrupt_enter();
- if (DMA_GetITStatus(I2C1_DMA_CHANNEL_TX, DMA_IT_TCIF6))
+ rt_interrupt_enter();
+ if (DMA_GetITStatus(I2C1_DMA_CHANNEL_TX, DMA_IT_TCIF6))
{
- I2C_TRACE("TXTC\n");
- DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 );
-
+ I2C_TRACE("TXTC\n");
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 );
+
}
- rt_interrupt_leave();
+ rt_interrupt_leave();
}
void DMA1_Stream0_IRQHandler(void) //I2C1 RX
{
- rt_interrupt_enter();
+ rt_interrupt_enter();
- if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TCIF0))
+ if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TCIF0))
{
- I2C_TRACE("RXTC\n");
- /* clear DMA flag */
- DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TCIF0 );
- DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, DISABLE);
- DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
- if( i2cStatus == S6 )
- {
- i2cStatus = S_STOP;
- I2C1->CR1 |= CR1_STOP_Set;
- rt_event_send(&i2c_event, I2C_COMPLETE);
- }
+ I2C_TRACE("RXTC\n");
+ /* clear DMA flag */
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TCIF0 );
+ DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, DISABLE);
+ DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
+ if( i2cStatus == S6 )
+ {
+ i2cStatus = S_STOP;
+ I2C1->CR1 |= CR1_STOP_Set;
+ rt_event_send(&i2c_event, I2C_COMPLETE);
+ }
+ }
+ if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_HTIF0))
+ {
+ I2C_TRACE("RXHT\n");
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_HTIF0 );
+ }
+ if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TEIF0))
+ {
+ I2C_TRACE("RXTE\n");
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TEIF0 );
+ }
+ if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_FEIF0))
+ {
+ I2C_TRACE("RXFE\n");
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_FEIF0 );
+ }
+ if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_DMEIF0))
+ {
+ I2C_TRACE("RXDME\n");
+ DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_DMEIF0 );
}
- if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_HTIF0))
- {
- I2C_TRACE("RXHT\n");
- DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_HTIF0 );
- }
- if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TEIF0))
- {
- I2C_TRACE("RXTE\n");
- DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TEIF0 );
- }
- if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_FEIF0))
- {
- I2C_TRACE("RXFE\n");
- DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_FEIF0 );
- }
- if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_DMEIF0))
- {
- I2C_TRACE("RXDME\n");
- DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_DMEIF0 );
- }
- rt_interrupt_leave();
+ rt_interrupt_leave();
}
void I2C1_ER_IRQHandler()
{
- __IO uint16_t regSR1, regSR2;
-
- i2cErrorNo = 0;
- regSR1 = I2C1->SR1;
- I2C_TRACE("I2C Error SR1= 0x%X CR1 = 0x%X\n" , regSR1, I2C1->CR1);
- if( (regSR1 & SR1_AF_Set) == SR1_AF_Set)
- {
- I2C1->SR1 &= ~SR1_AF_Set;
- i2cErrorNo |= ERR_AF;
- I2C_TRACE("ACK failure\n");
- }
- if( (regSR1 & SR1_BERR_Set) == SR1_BERR_Set)
- {
- I2C1->SR1 &= ~SR1_BERR_Set;
- i2cErrorNo |= ERR_BERR;
- I2C_TRACE("Bus Error\n");
- }
- if( (regSR1 & SR1_ARLO_Set) == SR1_ARLO_Set)
- {
- I2C1->SR1 &= ~SR1_ARLO_Set;
- i2cErrorNo |= ERR_ARLO;
- I2C_TRACE("Arblitation lost\n");
- }
- //dump_i2c_register(I2C1);
+ __IO uint16_t regSR1, regSR2;
+
+ i2cErrorNo = 0;
+ regSR1 = I2C1->SR1;
+ I2C_TRACE("I2C Error SR1= 0x%X CR1 = 0x%X\n" , regSR1, I2C1->CR1);
+ if( (regSR1 & SR1_AF_Set) == SR1_AF_Set)
+ {
+ I2C1->SR1 &= ~SR1_AF_Set;
+ i2cErrorNo |= ERR_AF;
+ I2C_TRACE("ACK failure\n");
+ }
+ if( (regSR1 & SR1_BERR_Set) == SR1_BERR_Set)
+ {
+ I2C1->SR1 &= ~SR1_BERR_Set;
+ i2cErrorNo |= ERR_BERR;
+ I2C_TRACE("Bus Error\n");
+ }
+ if( (regSR1 & SR1_ARLO_Set) == SR1_ARLO_Set)
+ {
+ I2C1->SR1 &= ~SR1_ARLO_Set;
+ i2cErrorNo |= ERR_ARLO;
+ I2C_TRACE("Arblitation lost\n");
+ }
+ //dump_i2c_register(I2C1);
}
Status I2C_Free_Bus(I2C_TypeDef* I2Cx, u32 timeout )
{
- /*u32 i = 0;
- u16 tmp = 0;
- GPIO_InitTypeDef GPIO_InitStructure;
+ /*u32 i = 0;
+ u16 tmp = 0;
+ GPIO_InitTypeDef GPIO_InitStructure;
- tmp = I2Cx->SR2;
+ tmp = I2Cx->SR2;
- while( tmp & SR2_BUSY )
- {
- if( i++ < timeout )
- {
- if( I2Cx == I2C1 )
- {
- //rt_kprintf("Free Bus!\n");
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
+ while( tmp & SR2_BUSY )
+ {
+ if( i++ < timeout )
+ {
+ if( I2Cx == I2C1 )
+ {
+ //rt_kprintf("Free Bus!\n");
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
- GPIO_SetBits(GPIOB, GPIO_Pin_6);
- GPIO_SetBits(GPIOB, GPIO_Pin_7);
-
- }
- else if( I2Cx == I2C2 )
- {
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
+ GPIO_SetBits(GPIOB, GPIO_Pin_6);
+ GPIO_SetBits(GPIOB, GPIO_Pin_7);
- GPIO_ResetBits(GPIOB, GPIO_Pin_10);
- }
- rt_thread_delay(10);
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
- I2C_Cmd(I2Cx, DISABLE);
- I2C_Cmd(I2Cx, ENABLE);
- }
- else
- return Error;
- tmp = I2Cx->SR2;
- } */
- return Success;
+ }
+ else if( I2Cx == I2C2 )
+ {
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ GPIO_ResetBits(GPIOB, GPIO_Pin_10);
+ }
+ rt_thread_delay(10);
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+ I2C_Cmd(I2Cx, DISABLE);
+ I2C_Cmd(I2Cx, ENABLE);
+ }
+ else
+ return Error;
+ tmp = I2Cx->SR2;
+ } */
+ return Success;
}
/*
- I2Cx: I2C1 or I2C2 (Now it only support I2C1)
- pBuffer: Buffer point
- NumByteToRW: Number of bytes read/write
+ I2Cx: I2C1 or I2C2 (Now it only support I2C1)
+ pBuffer: Buffer point
+ NumByteToRW: Number of bytes read/write
memAddr: 1-2 bytes memory address
- SlaveAddress: device address
- MemType: 1 = memory address size 1 bytes, 2 = memory address size 2 bytes
+ SlaveAddress: device address
+ MemType: 1 = memory address size 1 bytes, 2 = memory address size 2 bytes
*/
Status I2C_IORW(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t NumByteToRW, uint16_t memAddr, uint8_t SlaveAddress, uint8_t MemType )
{
- uint32_t ev, Timeout=0xFFFF;
+ uint32_t ev, Timeout=0xFFFF;
uint16_t temp, temp2;
- static uint32_t call_cnt = 0, i;
- Status ret;
+ static uint32_t call_cnt = 0, i;
+ Status ret;
- ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER );
- if( ret == RT_EOK )
- {
- ret = Success;
- DevAddr = SlaveAddress;
- BufSize = NumByteToRW;
- i2c_buf = pBuffer;
- memtype = MemType;
+ ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER );
+ if( ret == RT_EOK )
+ {
+ ret = Success;
+ DevAddr = SlaveAddress;
+ BufSize = NumByteToRW;
+ i2c_buf = pBuffer;
+ memtype = MemType;
- MemAddr = (uint8_t*)&memAddr;
- I2CDirection = I2C_DIRECTION_TX;
-
- I2CMode = DMA;
-
- i2cStatus = S1;
- if( SlaveAddress & 0x01 )
- {
- if( BufSize == 1 )
- i2cFlag = I2C_READ_INTERRUPT; //I2C_READ_POLLING;
- else
- i2cFlag = I2C_READ_DMA;
- }
- else
- i2cFlag = I2C_WRITE;
- I2Cx->CR2 |= I2C_IT_ERR | I2C_IT_EVT;// | CR2_DMAEN_Set;
-
- I2Cx->CR1 |= CR1_START_Set;
+ MemAddr = (uint8_t*)&memAddr;
+ I2CDirection = I2C_DIRECTION_TX;
- Timeout = 0xFFFF;
- if( rt_event_recv( &i2c_event, I2C_COMPLETE, RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &ev ) != RT_EOK ) {ret = Error; goto i2cError;}
-
- if( i2cFlag == I2C_READ_POLLING )
- {
- while ((I2Cx->SR1&0x0001) != 0x0001)
- if (Timeout-- == 0) {ret = Error; goto i2cError;}
- Timeout = 0xFFFF;
- I2Cx->DR = DevAddr;
- /* Wait until ADDR is set: EV6 */
- while ((I2Cx->SR1&0x0002) != 0x0002)
- {
- if (Timeout-- == 0){ret = Error; goto i2cError;}
- }
- /* Clear ACK bit */
- I2Cx->CR1 &= CR1_ACK_Reset;
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
- /* Clear ADDR flag */
- temp = I2Cx->SR2;
- /* Program the STOP */
- I2Cx->CR1 |= CR1_STOP_Set;
- /* Re-enable IRQs */
- __enable_irq();
- /* Wait until a data is received in DR register (RXNE = 1) EV7 */
- while ((I2Cx->SR1 & 0x00040) != 0x000040)if (Timeout-- == 0){ret = Error; goto i2cError;}
- /* Read the data */
- *i2c_buf = I2Cx->DR;
- /* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
- while ((I2Cx->CR1&0x200) == 0x200)if (Timeout-- == 0){ret = Error; goto i2cError;}
- /* Enable Acknowledgement to be ready for another reception */
- I2Cx->CR1 |= CR1_ACK_Set;
- }
- else
- {
- while ((I2Cx->CR1&0x200) == 0x200)
- {
- if (Timeout-- == 0) {ret = Error; break;}
- }
- if( i2cFlag == I2C_READ_INTERRUPT )
- I2Cx->CR1 |= CR1_ACK_Set;
- }
- i2cError:
- if( ret == Error )
- {
- /* TODO: i2c error handler */
- /* Need check i2cErrorNo and Reset I2C bus */
- }
- I2Cx->CR2 &= ~CR2_FREQ_Reset;
- //dump_i2c_register(I2C1);
- rt_mutex_release(i2c_mux);
- return ret;
- }
- else
- return Error;
+ I2CMode = DMA;
+
+ i2cStatus = S1;
+ if( SlaveAddress & 0x01 )
+ {
+ if( BufSize == 1 )
+ i2cFlag = I2C_READ_INTERRUPT; //I2C_READ_POLLING;
+ else
+ i2cFlag = I2C_READ_DMA;
+ }
+ else
+ i2cFlag = I2C_WRITE;
+ I2Cx->CR2 |= I2C_IT_ERR | I2C_IT_EVT;// | CR2_DMAEN_Set;
+
+ I2Cx->CR1 |= CR1_START_Set;
+
+ Timeout = 0xFFFF;
+ if( rt_event_recv( &i2c_event, I2C_COMPLETE, RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &ev ) != RT_EOK ) {ret = Error; goto i2cError;}
+
+ if( i2cFlag == I2C_READ_POLLING )
+ {
+ while ((I2Cx->SR1&0x0001) != 0x0001)
+ if (Timeout-- == 0) {ret = Error; goto i2cError;}
+ Timeout = 0xFFFF;
+ I2Cx->DR = DevAddr;
+ /* Wait until ADDR is set: EV6 */
+ while ((I2Cx->SR1&0x0002) != 0x0002)
+ {
+ if (Timeout-- == 0){ret = Error; goto i2cError;}
+ }
+ /* Clear ACK bit */
+ I2Cx->CR1 &= CR1_ACK_Reset;
+ /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
+ software sequence must complete before the current byte end of transfer */
+ __disable_irq();
+ /* Clear ADDR flag */
+ temp = I2Cx->SR2;
+ /* Program the STOP */
+ I2Cx->CR1 |= CR1_STOP_Set;
+ /* Re-enable IRQs */
+ __enable_irq();
+ /* Wait until a data is received in DR register (RXNE = 1) EV7 */
+ while ((I2Cx->SR1 & 0x00040) != 0x000040)if (Timeout-- == 0){ret = Error; goto i2cError;}
+ /* Read the data */
+ *i2c_buf = I2Cx->DR;
+ /* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
+ while ((I2Cx->CR1&0x200) == 0x200)if (Timeout-- == 0){ret = Error; goto i2cError;}
+ /* Enable Acknowledgement to be ready for another reception */
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ else
+ {
+ while ((I2Cx->CR1&0x200) == 0x200)
+ {
+ if (Timeout-- == 0) {ret = Error; break;}
+ }
+ if( i2cFlag == I2C_READ_INTERRUPT )
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ i2cError:
+ if( ret == Error )
+ {
+ /* TODO: i2c error handler */
+ /* Need check i2cErrorNo and Reset I2C bus */
+ }
+ I2Cx->CR2 &= ~CR2_FREQ_Reset;
+ //dump_i2c_register(I2C1);
+ rt_mutex_release(i2c_mux);
+ return ret;
+ }
+ else
+ return Error;
}
void I2C1_INIT()
{
- GPIO_InitTypeDef GPIO_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
I2C_InitTypeDef I2C_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
- if( i2c1_init_flag == 0 )
- {
- /* Enable the I2C clock */
- RCC_APB1PeriphClockCmd(I2C1_CLK, ENABLE);
- /* GPIOB clock enable */
- RCC_AHB1PeriphClockCmd(I2C1_GPIO_CLK, ENABLE);
- /* Enable the DMA1 clock */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
-
- //Reset GPIO
- GPIO_InitStructure.GPIO_Pin = I2C1_SDA_PIN | I2C1_SCL_PIN;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_Init(I2C1_GPIO_PORT, &GPIO_InitStructure);
-
- /* Connect PXx to I2C_SCL*/
- GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SDA_SOURCE, GPIO_AF_I2C1);
-
- /* Connect PXx to I2C_SDA*/
- GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SCL_SOURCE, GPIO_AF_I2C1);
-
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(I2C1_CLK, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(I2C1_CLK, DISABLE);
-
- I2C_DeInit(I2C1);
- I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
- I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
- I2C_InitStructure.I2C_OwnAddress1 = OwnAddress1;
- I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
- I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
- I2C_InitStructure.I2C_ClockSpeed = ClockSpeed;
- I2C_Init(I2C1, &I2C_InitStructure);
-
- I2C_Cmd(I2C1, ENABLE);
-
- /* Configure and enable I2C1 event interrupt -------------------------------*/
- NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- /* Configure and enable I2C1 DMA interrupt -------------------------------*/
- NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_TX_IRQn;
- NVIC_Init(&NVIC_InitStructure);
-
- NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_RX_IRQn;
- NVIC_Init(&NVIC_InitStructure);
-
- /* Configure and enable I2C1 error interrupt -------------------------------*/
- NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
- NVIC_Init(&NVIC_InitStructure);
-
- /* I2C1 TX DMA Channel configuration */
- DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
- DMA_DeInit(I2C1_DMA_CHANNEL_TX);
- I2CDMA_InitStructure.DMA_Channel = DMA_Channel_1;
- I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address;
- I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */
- I2CDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; /* This parameter will be configured durig communication */
- I2CDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */
- I2CDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- I2CDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
- I2CDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
- I2CDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
- I2CDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
- I2CDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
- //I2CDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
- I2CDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
- I2CDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
- I2CDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
- I2CDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
- DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure);
-
- /* I2C1 RX DMA Channel configuration */
- DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
- DMA_DeInit(I2C1_DMA_CHANNEL_RX);
- DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure);
-
- //I2C_AcknowledgePolling(I2C1, 0x70);
-
- rt_event_init(&i2c_event, "i2c_event", RT_IPC_FLAG_FIFO );
- i2c_mux = rt_mutex_create("i2c_mux", RT_IPC_FLAG_FIFO );
- i2c1_init_flag = 1;
- }
+ if( i2c1_init_flag == 0 )
+ {
+ /* Enable the I2C clock */
+ RCC_APB1PeriphClockCmd(I2C1_CLK, ENABLE);
+ /* GPIOB clock enable */
+ RCC_AHB1PeriphClockCmd(I2C1_GPIO_CLK, ENABLE);
+ /* Enable the DMA1 clock */
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
+
+ //Reset GPIO
+ GPIO_InitStructure.GPIO_Pin = I2C1_SDA_PIN | I2C1_SCL_PIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+ GPIO_Init(I2C1_GPIO_PORT, &GPIO_InitStructure);
+
+ /* Connect PXx to I2C_SCL*/
+ GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SDA_SOURCE, GPIO_AF_I2C1);
+
+ /* Connect PXx to I2C_SDA*/
+ GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SCL_SOURCE, GPIO_AF_I2C1);
+
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(I2C1_CLK, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(I2C1_CLK, DISABLE);
+
+ I2C_DeInit(I2C1);
+ I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+ I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+ I2C_InitStructure.I2C_OwnAddress1 = OwnAddress1;
+ I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+ I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+ I2C_InitStructure.I2C_ClockSpeed = ClockSpeed;
+ I2C_Init(I2C1, &I2C_InitStructure);
+
+ I2C_Cmd(I2C1, ENABLE);
+
+ /* Configure and enable I2C1 event interrupt -------------------------------*/
+ NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+ /* Configure and enable I2C1 DMA interrupt -------------------------------*/
+ NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_TX_IRQn;
+ NVIC_Init(&NVIC_InitStructure);
+
+ NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_RX_IRQn;
+ NVIC_Init(&NVIC_InitStructure);
+
+ /* Configure and enable I2C1 error interrupt -------------------------------*/
+ NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+ NVIC_Init(&NVIC_InitStructure);
+
+ /* I2C1 TX DMA Channel configuration */
+ DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
+ DMA_DeInit(I2C1_DMA_CHANNEL_TX);
+ I2CDMA_InitStructure.DMA_Channel = DMA_Channel_1;
+ I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address;
+ I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */
+ I2CDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; /* This parameter will be configured durig communication */
+ I2CDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */
+ I2CDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ I2CDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+ I2CDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ I2CDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ I2CDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+ I2CDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+ //I2CDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+ I2CDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
+ I2CDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
+ I2CDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
+ I2CDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
+ DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure);
+
+ /* I2C1 RX DMA Channel configuration */
+ DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
+ DMA_DeInit(I2C1_DMA_CHANNEL_RX);
+ DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure);
+
+ //I2C_AcknowledgePolling(I2C1, 0x70);
+
+ rt_event_init(&i2c_event, "i2c_event", RT_IPC_FLAG_FIFO );
+ i2c_mux = rt_mutex_create("i2c_mux", RT_IPC_FLAG_FIFO );
+ i2c1_init_flag = 1;
+ }
}
void I2C_DMAConfig(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t BufferSize, uint32_t Direction)
{
-
- I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)pBuffer;
- I2CDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
- /* Initialize the DMA with the new parameters */
+
+ I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)pBuffer;
+ I2CDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
+ /* Initialize the DMA with the new parameters */
if (Direction == I2C_DIRECTION_TX)
{
/* Configure the DMA Tx Channel with the buffer address and the buffer size */
I2CDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
if (I2Cx == I2C1)
- {
+ {
I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address;
- //DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
- DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure);
- DMA_Cmd(I2C1_DMA_CHANNEL_TX, ENABLE);
- }
+ //DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
+ DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure);
+ DMA_Cmd(I2C1_DMA_CHANNEL_TX, ENABLE);
+ }
else
- {
+ {
I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C2_DR_Address;
- //DMA_Cmd(I2C2_DMA_CHANNEL_TX, DISABLE);
- DMA_Init(I2C2_DMA_CHANNEL_TX, &I2CDMA_InitStructure);
- DMA_Cmd(I2C2_DMA_CHANNEL_TX, ENABLE);
- }
+ //DMA_Cmd(I2C2_DMA_CHANNEL_TX, DISABLE);
+ DMA_Init(I2C2_DMA_CHANNEL_TX, &I2CDMA_InitStructure);
+ DMA_Cmd(I2C2_DMA_CHANNEL_TX, ENABLE);
+ }
}
else /* Reception */
@@ -609,19 +609,19 @@ void I2C_DMAConfig(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t BufferSize, uin
I2CDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
if (I2Cx == I2C1)
- {
+ {
I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address;
- //DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
- DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure);
- DMA_Cmd(I2C1_DMA_CHANNEL_RX, ENABLE);
- }
- else
- {
+ //DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
+ DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure);
+ DMA_Cmd(I2C1_DMA_CHANNEL_RX, ENABLE);
+ }
+ else
+ {
I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C2_DR_Address;
- // DMA_Cmd(I2C2_DMA_CHANNEL_RX, DISABLE);
- DMA_Init(I2C2_DMA_CHANNEL_RX, &I2CDMA_InitStructure);
- DMA_Cmd(I2C2_DMA_CHANNEL_RX, ENABLE);
- }
+ // DMA_Cmd(I2C2_DMA_CHANNEL_RX, DISABLE);
+ DMA_Init(I2C2_DMA_CHANNEL_RX, &I2CDMA_InitStructure);
+ DMA_Cmd(I2C2_DMA_CHANNEL_RX, ENABLE);
+ }
}
}
diff --git a/bsp/stm32f20x/Drivers/i2c.h b/bsp/stm32f20x/Drivers/i2c.h
index 3d2c9d871f..e1a6b57427 100644
--- a/bsp/stm32f20x/Drivers/i2c.h
+++ b/bsp/stm32f20x/Drivers/i2c.h
@@ -5,17 +5,17 @@
/* Exported constants --------------------------------------------------------*/
-#define SR1_AF_Set ((uint16_t)0x0400)
-#define SR1_ARLO_Set ((uint16_t)0x0200)
-#define SR1_BERR_Set ((uint16_t)0x0100)
-#define SR1_ADDR_Set ((uint16_t)0x0002)
-#define SR1_SB_Set ((uint16_t)0x0001)
+#define SR1_AF_Set ((uint16_t)0x0400)
+#define SR1_ARLO_Set ((uint16_t)0x0200)
+#define SR1_BERR_Set ((uint16_t)0x0100)
+#define SR1_ADDR_Set ((uint16_t)0x0002)
+#define SR1_SB_Set ((uint16_t)0x0001)
-#define SR2_BUSY ((uint16_t)0x0002)
-#define SR2_MSL ((uint16_t)0x0001)
+#define SR2_BUSY ((uint16_t)0x0002)
+#define SR2_MSL ((uint16_t)0x0001)
-#define CR1_SWRST_Set ((uint16_t)0x8000)
+#define CR1_SWRST_Set ((uint16_t)0x8000)
/* I2C SPE mask */
#define CR1_PE_Set ((uint16_t)0x0001)
#define CR1_PE_Reset ((uint16_t)0xFFFE)
@@ -97,12 +97,12 @@
#define I2C1_DMA_CHANNEL_TX DMA1_Stream6
#define I2C1_DMA_CHANNEL_RX DMA1_Stream0
-#define I2C1_DMA_TX_IRQn DMA1_Stream6_IRQn
+#define I2C1_DMA_TX_IRQn DMA1_Stream6_IRQn
#define I2C1_DMA_RX_IRQn DMA1_Stream0_IRQn
-
+
#define I2C2_DMA_CHANNEL_TX DMA1_Stream2
#define I2C2_DMA_CHANNEL_RX DMA1_Stream7
-#define I2C2_DMA_TX_IRQn DMA1_Stream2_IRQn
+#define I2C2_DMA_TX_IRQn DMA1_Stream2_IRQn
#define I2C2_DMA_RX_IRQn DMA1_Stream7_IRQn
#define I2C1_DR_Address 0x40005410
@@ -112,20 +112,20 @@
#define I2C1_SCL_PIN GPIO_Pin_6
#define I2C1_SDA_SOURCE GPIO_PinSource7
#define I2C1_SCL_SOURCE GPIO_PinSource6
-#define I2C1_GPIO_PORT GPIOB
-#define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB
+#define I2C1_GPIO_PORT GPIOB
+#define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB
#define I2C1_CLK RCC_APB1Periph_I2C1
#define I2C2_SDA_PIN GPIO_Pin_11
#define I2C2_SCL_PIN GPIO_Pin_10
#define I2C2_SDA_SOURCE GPIO_PinSource11
#define I2C2_SCL_SOURCE GPIO_PinSource10
-#define I2C2_GPIO_PORT GPIOB
-#define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB
+#define I2C2_GPIO_PORT GPIOB
+#define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB
#define I2C2_CLK RCC_APB1Periph_I2C1
-#define I2C_MEM_1Byte 1
-#define I2C_MEM_2Bytes 2
+#define I2C_MEM_1Byte 1
+#define I2C_MEM_2Bytes 2
typedef enum
{
@@ -144,4 +144,4 @@ void I2C1_INIT();
Status I2C_AcknowledgePolling(I2C_TypeDef* I2Cx ,uint8_t Addr);
Status I2C_IORW(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t NumByteToRead, uint16_t memAddr, uint8_t SlaveAddress , uint8_t MemType );
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/stm32f20x/Drivers/sdio_sd.c b/bsp/stm32f20x/Drivers/sdio_sd.c
index 4c0689768b..9eab300e0f 100644
--- a/bsp/stm32f20x/Drivers/sdio_sd.c
+++ b/bsp/stm32f20x/Drivers/sdio_sd.c
@@ -4,160 +4,160 @@
* @author MCD Application Team
* @version V4.6.1
* @date 18-April-2011
- * @brief This file provides a set of functions needed to manage the SDIO SD
+ * @brief This file provides a set of functions needed to manage the SDIO SD
* Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
- * to know about the boards supporting this memory).
- *
- *
+ * to know about the boards supporting this memory).
+ *
+ *
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
- * It implements a high level communication layer for read and write
- * from/to this memory. The needed STM32 hardware resources (SDIO and
- * GPIO) are defined in stm32xx_eval.h file, and the initialization is
- * performed in SD_LowLevel_Init() function declared in stm32xx_eval.c
+ * It implements a high level communication layer for read and write
+ * from/to this memory. The needed STM32 hardware resources (SDIO and
+ * GPIO) are defined in stm32xx_eval.h file, and the initialization is
+ * performed in SD_LowLevel_Init() function declared in stm32xx_eval.c
* file.
- * You can easily tailor this driver to any other development board,
- * by just adapting the defines for hardware resources and
+ * You can easily tailor this driver to any other development board,
+ * by just adapting the defines for hardware resources and
* SD_LowLevel_Init() function.
- *
+ *
* A - SD Card Initialization and configuration
- * ============================================
- * - To initialize the SD Card, use the SD_Init() function. It
- * Initializes the SD Card and put it into StandBy State (Ready
+ * ============================================
+ * - To initialize the SD Card, use the SD_Init() function. It
+ * Initializes the SD Card and put it into StandBy State (Ready
* for data transfer). This function provide the following operations:
- *
+ *
* 1 - Apply the SD Card initialization process at 400KHz and check
- * the SD Card type (Standard Capacity or High Capacity). You
- * can change or adapt this frequency by adjusting the
- * "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file.
+ * the SD Card type (Standard Capacity or High Capacity). You
+ * can change or adapt this frequency by adjusting the
+ * "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file.
* The SD Card frequency (SDIO_CK) is computed as follows:
- *
- * +---------------------------------------------+
+ *
+ * +---------------------------------------------+
* | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
- * +---------------------------------------------+
- *
- * In initialization mode and according to the SD Card standard,
- * make sure that the SDIO_CK frequency don't exceed 400KHz.
- *
+ * +---------------------------------------------+
+ *
+ * In initialization mode and according to the SD Card standard,
+ * make sure that the SDIO_CK frequency don't exceed 400KHz.
+ *
* 2 - Get the SD CID and CSD data. All these information are
* managed by the SDCardInfo structure. This structure provide
- * also ready computed SD Card capacity and Block size.
+ * also ready computed SD Card capacity and Block size.
*
* 3 - Configure the SD Card Data transfer frequency. By Default,
* the card transfer frequency is set to 24MHz. You can change
- * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV"
+ * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV"
* define inside the stm32xx_eval.h file.
* The SD Card frequency (SDIO_CK) is computed as follows:
- *
- * +---------------------------------------------+
+ *
+ * +---------------------------------------------+
* | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
- * +---------------------------------------------+
- *
- * In transfer mode and according to the SD Card standard,
+ * +---------------------------------------------+
+ *
+ * In transfer mode and according to the SD Card standard,
* make sure that the SDIO_CK frequency don't exceed 25MHz
* and 50MHz in High-speed mode switch.
* To be able to use a frequency higher than 24MHz, you should
- * use the SDIO peripheral in bypass mode. Refer to the
+ * use the SDIO peripheral in bypass mode. Refer to the
* corresponding reference manual for more details.
- *
+ *
* 4 - Select the corresponding SD Card according to the address
* read with the step 2.
- *
- * 5 - Configure the SD Card in wide bus mode: 4-bits data.
+ *
+ * 5 - Configure the SD Card in wide bus mode: 4-bits data.
*
* B - SD Card Read operation
- * ==========================
+ * ==========================
* - You can read SD card by using two function: SD_ReadBlock() and
* SD_ReadMultiBlocks() functions. These functions support only
* 512-byte block length.
* - The SD_ReadBlock() function read only one block (512-byte). This
- * function can transfer the data using DMA controller or using
- * polling mode. To select between DMA or polling mode refer to
+ * function can transfer the data using DMA controller or using
+ * polling mode. To select between DMA or polling mode refer to
* "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
* file and uncomment the corresponding line. By default the SD DMA
- * mode is selected
- * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple
- * of 512-byte).
+ * mode is selected
+ * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple
+ * of 512-byte).
* - Any read operation should be followed by two functions to check
* if the DMA Controller and SD Card status.
* - SD_ReadWaitOperation(): this function insure that the DMA
* controller has finished all data transfer.
- * - SD_GetStatus(): to check that the SD Card has finished the
+ * - SD_GetStatus(): to check that the SD Card has finished the
* data transfer and it is ready for data.
- *
+ *
* - The DMA transfer is finished by the SDIO Data End interrupt. User
* has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
- * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
- *
+ * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
+ *
* C - SD Card Write operation
- * ===========================
+ * ===========================
* - You can write SD card by using two function: SD_WriteBlock() and
* SD_WriteMultiBlocks() functions. These functions support only
- * 512-byte block length.
+ * 512-byte block length.
* - The SD_WriteBlock() function write only one block (512-byte). This
- * function can transfer the data using DMA controller or using
- * polling mode. To select between DMA or polling mode refer to
+ * function can transfer the data using DMA controller or using
+ * polling mode. To select between DMA or polling mode refer to
* "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
* file and uncomment the corresponding line. By default the SD DMA
- * mode is selected
- * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple
- * of 512-byte).
+ * mode is selected
+ * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple
+ * of 512-byte).
* - Any write operation should be followed by two functions to check
* if the DMA Controller and SD Card status.
* - SD_ReadWaitOperation(): this function insure that the DMA
* controller has finished all data transfer.
- * - SD_GetStatus(): to check that the SD Card has finished the
- * data transfer and it is ready for data.
- *
+ * - SD_GetStatus(): to check that the SD Card has finished the
+ * data transfer and it is ready for data.
+ *
* - The DMA transfer is finished by the SDIO Data End interrupt. User
* has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
- * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
-
- *
+ * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
+
+ *
* D - SD card status
- * ==================
+ * ==================
* - At any time, you can check the SD Card status and get the SD card
* state by using the SD_GetStatus() function. This function checks
* first if the SD card is still connected and then get the internal
- * SD Card transfer state.
- * - You can also get the SD card SD Status register by using the
- * SD_SendSDStatus() function.
- *
+ * SD Card transfer state.
+ * - You can also get the SD card SD Status register by using the
+ * SD_SendSDStatus() function.
+ *
* E - Programming Model
- * =====================
+ * =====================
* Status = SD_Init(); // Initialization Step as described in section A
- *
+ *
* // SDIO Interrupt ENABLE
* NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
* NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
* NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
* NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
* NVIC_Init(&NVIC_InitStructure);
- *
+ *
* // Write operation as described in Section C
* Status = SD_WriteBlock(buffer, address, 512);
* Status = SD_WaitWriteOperation();
- * while(SD_GetStatus() != SD_TRANSFER_OK);
- *
+ * while(SD_GetStatus() != SD_TRANSFER_OK);
+ *
* Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
* Status = SD_WaitWriteOperation();
- * while(SD_GetStatus() != SD_TRANSFER_OK);
- *
+ * while(SD_GetStatus() != SD_TRANSFER_OK);
+ *
* // Read operation as described in Section B
* Status = SD_ReadBlock(buffer, address, 512);
* Status = SD_WaitReadOperation();
* while(SD_GetStatus() != SD_TRANSFER_OK);
- *
+ *
* Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
* Status = SD_WaitReadOperation();
- * while(SD_GetStatus() != SD_TRANSFER_OK);
- *
- *
+ * while(SD_GetStatus() != SD_TRANSFER_OK);
+ *
+ *
* STM32 SDIO Pin assignment
- * =========================
+ * =========================
* +-----------------------------------------------------------+
* | Pin assignment |
* +-----------------------------+---------------+-------------+
@@ -170,11 +170,11 @@
* | SDIO CLK | CLK | 5 |
* | | GND | 6 (0 V) |
* | SDIO D0 | D0 | 7 |
- * | SDIO D1 | D1 | 8 |
- * +-----------------------------+---------------+-------------+
- *
- * @endverbatim
- *
+ * | SDIO D1 | D1 | 8 |
+ * +-----------------------------+---------------+-------------+
+ *
+ * @endverbatim
+ *
******************************************************************************
* @attention
*
@@ -186,8 +186,8 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* © COPYRIGHT 2011 STMicroelectronics
/* set sector size to 512 */
-#define SECTOR_SIZE 512
+#define SECTOR_SIZE 512
static struct rt_device sdcard_device;
//static SD_CardInfo SDCardInfo;
@@ -2516,44 +2516,44 @@ static rt_uint8_t _sdcard_buffer[SECTOR_SIZE];
/* RT-Thread Device Driver Interface */
static rt_err_t rt_sdcard_init(rt_device_t dev)
{
-/* NVIC_InitTypeDef NVIC_InitStructure;
+/* NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure); */
+ NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure); */
- if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
- {
- rt_kprintf("init sd lock semaphore failed\n");
- }
- else
- rt_kprintf("SD Card init OK\n");
+ if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
+ {
+ rt_kprintf("init sd lock semaphore failed\n");
+ }
+ else
+ rt_kprintf("SD Card init OK\n");
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
- SD_Error status;
- rt_uint32_t retry;
- rt_uint32_t factor;
+ SD_Error status;
+ rt_uint32_t retry;
+ rt_uint32_t factor;
- if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1;
- else factor = SECTOR_SIZE;
- //rt_kprintf("sd: read 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer ,pos, size);
- rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
+ if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1;
+ else factor = SECTOR_SIZE;
+ //rt_kprintf("sd: read 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer ,pos, size);
+ rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
retry = 3;
while(retry)
@@ -2571,8 +2571,8 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
(uint8_t*)_sdcard_buffer, SECTOR_SIZE);
status = SD_WaitReadOperation();
- while(SD_GetStatus() != SD_TRANSFER_OK);
- if (status != SD_OK) break;
+ while(SD_GetStatus() != SD_TRANSFER_OK);
+ if (status != SD_OK) break;
/* copy to the buffer */
rt_memcpy(((rt_uint8_t*)buffer + index * SECTOR_SIZE), _sdcard_buffer, SECTOR_SIZE);
@@ -2590,49 +2590,49 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
status = SD_ReadMultiBlocks((part.offset + pos) * factor,
(uint8_t*)buffer, SECTOR_SIZE, size);
}
- status = SD_WaitReadOperation();
- while(SD_GetStatus() != SD_TRANSFER_OK);
- /*rt_kprintf("===DUMP SECTOR %d===\n",pos);
- {
- int i, j;
- char* tmp = (char*)buffer;
- for(i =0; i < 32;i++)
- {
- rt_kprintf("%2d: ",i);
- for(j= 0; j < 16;j++)
- rt_kprintf("%02X ",tmp[i*16+j]);
- rt_kprintf("\n");
- }
- } */
+ status = SD_WaitReadOperation();
+ while(SD_GetStatus() != SD_TRANSFER_OK);
+ /*rt_kprintf("===DUMP SECTOR %d===\n",pos);
+ {
+ int i, j;
+ char* tmp = (char*)buffer;
+ for(i =0; i < 32;i++)
+ {
+ rt_kprintf("%2d: ",i);
+ for(j= 0; j < 16;j++)
+ rt_kprintf("%02X ",tmp[i*16+j]);
+ rt_kprintf("\n");
+ }
+ } */
}
if (status == SD_OK) break;
retry --;
}
- rt_sem_release(&sd_lock);
- if (status == SD_OK) return size;
+ rt_sem_release(&sd_lock);
+ if (status == SD_OK) return size;
- rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer);
- return 0;
+ rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer);
+ return 0;
}
static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
- SD_Error status;
- rt_uint32_t factor;
+ SD_Error status;
+ rt_uint32_t factor;
- if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1;
- else factor = SECTOR_SIZE;
+ if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1;
+ else factor = SECTOR_SIZE;
- //rt_kprintf("sd: write 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer , pos, size);
- rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
-
- /* read all sectors */
- if (((rt_uint32_t)buffer % 4 != 0) ||
+ //rt_kprintf("sd: write 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer , pos, size);
+ rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
+
+ /* read all sectors */
+ if (((rt_uint32_t)buffer % 4 != 0) ||
((rt_uint32_t)buffer > 0x20080000))
- {
- rt_uint32_t index;
+ {
+ rt_uint32_t index;
/* which is not alignment with 4 or not chip SRAM */
for (index = 0; index < size; index ++)
@@ -2643,14 +2643,14 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
status = SD_WriteBlock((part.offset + index + pos) * factor,
(uint8_t*)_sdcard_buffer, SECTOR_SIZE);
- status = SD_WaitWriteOperation();
- while(SD_GetStatus() != SD_TRANSFER_OK);
+ status = SD_WaitWriteOperation();
+ while(SD_GetStatus() != SD_TRANSFER_OK);
if (status != SD_OK) break;
}
- }
- else
- {
+ }
+ else
+ {
if (size == 1)
{
status = SD_WriteBlock((part.offset + pos) * factor,
@@ -2662,15 +2662,15 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
(uint8_t*)buffer, SECTOR_SIZE, size);
}
- status = SD_WaitWriteOperation();
+ status = SD_WaitWriteOperation();
while(SD_GetStatus() != SD_TRANSFER_OK);
- }
- rt_sem_release(&sd_lock);
+ }
+ rt_sem_release(&sd_lock);
- if (status == SD_OK) return size;
+ if (status == SD_OK) return size;
- rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer);
- return 0;
+ rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer);
+ return 0;
}
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
@@ -2686,89 +2686,89 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
geometry->bytes_per_sector = 512;
geometry->block_size = SDCardInfo.CardBlockSize;
- if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
- geometry->sector_count = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024;
- else
- geometry->sector_count = SDCardInfo.CardCapacity/SDCardInfo.CardBlockSize;
+ if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+ geometry->sector_count = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024;
+ else
+ geometry->sector_count = SDCardInfo.CardCapacity/SDCardInfo.CardBlockSize;
}
- return RT_EOK;
+ return RT_EOK;
}
void rt_hw_sdcard_init()
{
NVIC_InitTypeDef NVIC_InitStructure;
- if (SD_Init() == SD_OK)
- {
- SD_Error status;
- rt_uint8_t *sector;
+ if (SD_Init() == SD_OK)
+ {
+ SD_Error status;
+ rt_uint8_t *sector;
- /*status = SD_GetCardInfo(&SDCardInfo);
- if (status != SD_OK) goto __return;
+ /*status = SD_GetCardInfo(&SDCardInfo);
+ if (status != SD_OK) goto __return;
- status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16));
- if (status != SD_OK) goto __return;
+ status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16));
+ if (status != SD_OK) goto __return;
- SD_EnableWideBusOperation(SDIO_BusWide_4b);
- SD_SetDeviceMode(SD_DMA_MODE); */
+ SD_EnableWideBusOperation(SDIO_BusWide_4b);
+ SD_SetDeviceMode(SD_DMA_MODE); */
- // SDIO Interrupt ENABLE
- NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
+ // SDIO Interrupt ENABLE
+ NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
- /* get the first sector to read partition table */
- sector = (rt_uint8_t*) rt_malloc (512);
- if (sector == RT_NULL)
- {
- rt_kprintf("allocate partition sector buffer failed\n");
- return;
- }
- status = SD_ReadBlock(0, (uint8_t*)sector, 512);
- status = SD_WaitReadOperation();
+ /* get the first sector to read partition table */
+ sector = (rt_uint8_t*) rt_malloc (512);
+ if (sector == RT_NULL)
+ {
+ rt_kprintf("allocate partition sector buffer failed\n");
+ return;
+ }
+ status = SD_ReadBlock(0, (uint8_t*)sector, 512);
+ status = SD_WaitReadOperation();
while(SD_GetStatus() != SD_TRANSFER_OK);
- if (status == SD_OK)
- {
- /* get the first partition */
- if (dfs_filesystem_get_partition(&part, sector, 0) != 0)
+ if (status == SD_OK)
+ {
+ /* get the first partition */
+ if (dfs_filesystem_get_partition(&part, sector, 0) != 0)
{
/* there is no partition */
part.offset = 0;
part.size = 0;
}
- }
- else
- {
- /* there is no partition table */
- part.offset = 0;
- part.size = 0;
- }
+ }
+ else
+ {
+ /* there is no partition table */
+ part.offset = 0;
+ part.size = 0;
+ }
- /* release sector buffer */
- rt_free(sector);
+ /* release sector buffer */
+ rt_free(sector);
- /* register sdcard device */
- sdcard_device.type = RT_Device_Class_Block;
- sdcard_device.init = rt_sdcard_init;
- sdcard_device.open = rt_sdcard_open;
- sdcard_device.close = rt_sdcard_close;
- sdcard_device.read = rt_sdcard_read;
- sdcard_device.write = rt_sdcard_write;
- sdcard_device.control = rt_sdcard_control;
+ /* register sdcard device */
+ sdcard_device.type = RT_Device_Class_Block;
+ sdcard_device.init = rt_sdcard_init;
+ sdcard_device.open = rt_sdcard_open;
+ sdcard_device.close = rt_sdcard_close;
+ sdcard_device.read = rt_sdcard_read;
+ sdcard_device.write = rt_sdcard_write;
+ sdcard_device.control = rt_sdcard_control;
- /* no private */
- sdcard_device.user_data = &SDCardInfo;
+ /* no private */
+ sdcard_device.user_data = &SDCardInfo;
- rt_device_register(&sdcard_device, "sd0",
- RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
+ rt_device_register(&sdcard_device, "sd0",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
- return;
- }
+ return;
+ }
__return:
- rt_kprintf("sdcard init failed\n");
+ rt_kprintf("sdcard init failed\n");
}
diff --git a/bsp/stm32f20x/Drivers/sdio_sd.h b/bsp/stm32f20x/Drivers/sdio_sd.h
index c4ee35eb07..6a732a5e52 100644
--- a/bsp/stm32f20x/Drivers/sdio_sd.h
+++ b/bsp/stm32f20x/Drivers/sdio_sd.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @version V4.6.1
* @date 18-April-2011
- * @brief This file contains all the functions prototypes for the SD Card
+ * @brief This file contains all the functions prototypes for the SD Card
* stm32_eval_sdio_sd driver firmware library.
******************************************************************************
* @attention
@@ -17,8 +17,8 @@
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* © COPYRIGHT 2011 STMicroelectronics
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
- rt_uint32_t address, rt_uint32_t size);
+ rt_uint32_t address, rt_uint32_t size);
/**
* @addtogroup STM32
@@ -26,252 +26,252 @@ static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
/* RT-Thread Device Interface */
static rt_err_t rt_serial_init (rt_device_t dev)
{
- struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
- if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
- {
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- rt_memset(uart->int_rx->rx_buffer, 0,
- sizeof(uart->int_rx->rx_buffer));
- uart->int_rx->read_index = 0;
- uart->int_rx->save_index = 0;
- }
+ if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+ {
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_memset(uart->int_rx->rx_buffer, 0,
+ sizeof(uart->int_rx->rx_buffer));
+ uart->int_rx->read_index = 0;
+ uart->int_rx->save_index = 0;
+ }
- if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
- {
- RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
- uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
+ if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
+ uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
- /* init data node memory pool */
- rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
- uart->dma_tx->data_node_mem_pool,
- sizeof(uart->dma_tx->data_node_mem_pool),
- sizeof(struct stm32_serial_data_node));
- }
+ /* init data node memory pool */
+ rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
+ uart->dma_tx->data_node_mem_pool,
+ sizeof(uart->dma_tx->data_node_mem_pool),
+ sizeof(struct stm32_serial_data_node));
+ }
- /* Enable USART */
- USART_Cmd(uart->uart_device, ENABLE);
+ /* Enable USART */
+ USART_Cmd(uart->uart_device, ENABLE);
- dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
- }
+ dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+ }
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct stm32_serial_device* uart;
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct stm32_serial_device* uart;
- ptr = buffer;
- err_code = RT_EOK;
- uart = (struct stm32_serial_device*)dev->user_data;
+ ptr = buffer;
+ err_code = RT_EOK;
+ uart = (struct stm32_serial_device*)dev->user_data;
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* interrupt mode Rx */
- while (size)
- {
- rt_base_t level;
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* interrupt mode Rx */
+ while (size)
+ {
+ rt_base_t level;
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
- if (uart->int_rx->read_index != uart->int_rx->save_index)
- {
- /* read a character */
- *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
- size--;
+ if (uart->int_rx->read_index != uart->int_rx->save_index)
+ {
+ /* read a character */
+ *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+ size--;
- /* move to next position */
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
- else
- {
- /* set error code */
- err_code = -RT_EEMPTY;
+ /* move to next position */
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+ else
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ break;
+ }
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- }
- }
- else
- {
- /* polling mode */
- while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
- {
- while (uart->uart_device->SR & USART_FLAG_RXNE)
- {
- *ptr = uart->uart_device->DR & 0xff;
- ptr ++;
- }
- }
- }
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+ }
+ else
+ {
+ /* polling mode */
+ while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+ {
+ while (uart->uart_device->SR & USART_FLAG_RXNE)
+ {
+ *ptr = uart->uart_device->DR & 0xff;
+ ptr ++;
+ }
+ }
+ }
- /* set error code */
- rt_set_errno(err_code);
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+ /* set error code */
+ rt_set_errno(err_code);
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
- rt_uint32_t address, rt_uint32_t size)
+ rt_uint32_t address, rt_uint32_t size)
{
- RT_ASSERT(dma_channel != RT_NULL);
+ RT_ASSERT(dma_channel != RT_NULL);
- /* disable DMA */
- DMA_Cmd(dma_channel, DISABLE);
+ /* disable DMA */
+ DMA_Cmd(dma_channel, DISABLE);
- /* set buffer address */
- dma_channel->M0AR = address;
- /* set size */
- dma_channel->NDTR = size;
+ /* set buffer address */
+ dma_channel->M0AR = address;
+ /* set size */
+ dma_channel->NDTR = size;
- /* enable DMA */
- DMA_Cmd(dma_channel, ENABLE);
+ /* enable DMA */
+ DMA_Cmd(dma_channel, ENABLE);
}
static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct stm32_serial_device* uart;
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct stm32_serial_device* uart;
- err_code = RT_EOK;
- ptr = (rt_uint8_t*)buffer;
- uart = (struct stm32_serial_device*)dev->user_data;
+ err_code = RT_EOK;
+ ptr = (rt_uint8_t*)buffer;
+ uart = (struct stm32_serial_device*)dev->user_data;
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- /* interrupt mode Tx, does not support */
- RT_ASSERT(0);
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
- {
- /* DMA mode Tx */
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /* interrupt mode Tx, does not support */
+ RT_ASSERT(0);
+ }
+ else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ /* DMA mode Tx */
- /* allocate a data node */
- struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
- rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
- if (data_node == RT_NULL)
- {
- /* set error code */
- err_code = -RT_ENOMEM;
- }
- else
- {
- rt_uint32_t level;
+ /* allocate a data node */
+ struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
+ rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
+ if (data_node == RT_NULL)
+ {
+ /* set error code */
+ err_code = -RT_ENOMEM;
+ }
+ else
+ {
+ rt_uint32_t level;
- /* fill data node */
- data_node->data_ptr = ptr;
- data_node->data_size = size;
+ /* fill data node */
+ data_node->data_ptr = ptr;
+ data_node->data_size = size;
- /* insert to data link */
- data_node->next = RT_NULL;
+ /* insert to data link */
+ data_node->next = RT_NULL;
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
- data_node->prev = uart->dma_tx->list_tail;
- if (uart->dma_tx->list_tail != RT_NULL)
- uart->dma_tx->list_tail->next = data_node;
- uart->dma_tx->list_tail = data_node;
+ data_node->prev = uart->dma_tx->list_tail;
+ if (uart->dma_tx->list_tail != RT_NULL)
+ uart->dma_tx->list_tail->next = data_node;
+ uart->dma_tx->list_tail = data_node;
- if (uart->dma_tx->list_head == RT_NULL)
- {
- /* start DMA to transmit data */
- uart->dma_tx->list_head = data_node;
+ if (uart->dma_tx->list_head == RT_NULL)
+ {
+ /* start DMA to transmit data */
+ uart->dma_tx->list_head = data_node;
- /* Enable DMA Channel */
- rt_serial_enable_dma(uart->dma_tx->dma_channel,
- (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
- uart->dma_tx->list_head->data_size);
- }
+ /* Enable DMA Channel */
+ rt_serial_enable_dma(uart->dma_tx->dma_channel,
+ (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+ uart->dma_tx->list_head->data_size);
+ }
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- }
- }
- else
- {
- /* polling mode */
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- if (*ptr == '\n')
- {
- while (!(uart->uart_device->SR & USART_FLAG_TXE));
- uart->uart_device->DR = '\r';
- }
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+ }
+ else
+ {
+ /* polling mode */
+ if (dev->flag & RT_DEVICE_FLAG_STREAM)
+ {
+ /* stream mode */
+ while (size)
+ {
+ if (*ptr == '\n')
+ {
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = '\r';
+ }
- while (!(uart->uart_device->SR & USART_FLAG_TXE));
- uart->uart_device->DR = (*ptr & 0x1FF);
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = (*ptr & 0x1FF);
- ++ptr; --size;
- }
- }
- else
- {
- /* write data directly */
- while (size)
- {
- while (!(uart->uart_device->SR & USART_FLAG_TXE));
- uart->uart_device->DR = (*ptr & 0x1FF);
+ ++ptr; --size;
+ }
+ }
+ else
+ {
+ /* write data directly */
+ while (size)
+ {
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = (*ptr & 0x1FF);
- ++ptr; --size;
- }
- }
- }
+ ++ptr; --size;
+ }
+ }
+ }
- /* set error code */
- rt_set_errno(err_code);
+ /* set error code */
+ rt_set_errno(err_code);
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
{
- struct stm32_serial_device* uart;
+ struct stm32_serial_device* uart;
- RT_ASSERT(dev != RT_NULL);
+ RT_ASSERT(dev != RT_NULL);
- uart = (struct stm32_serial_device*)dev->user_data;
- switch (cmd)
- {
- case RT_DEVICE_CTRL_SUSPEND:
- /* suspend device */
- dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
- USART_Cmd(uart->uart_device, DISABLE);
- break;
+ uart = (struct stm32_serial_device*)dev->user_data;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_SUSPEND:
+ /* suspend device */
+ dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+ USART_Cmd(uart->uart_device, DISABLE);
+ break;
- case RT_DEVICE_CTRL_RESUME:
- /* resume device */
- dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
- USART_Cmd(uart->uart_device, ENABLE);
- break;
- }
+ case RT_DEVICE_CTRL_RESUME:
+ /* resume device */
+ dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+ USART_Cmd(uart->uart_device, ENABLE);
+ break;
+ }
- return RT_EOK;
+ return RT_EOK;
}
/*
@@ -280,87 +280,87 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
*/
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
{
- RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(device != RT_NULL);
- if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
- (flag & RT_DEVICE_FLAG_INT_TX))
- {
- RT_ASSERT(0);
- }
+ if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+ (flag & RT_DEVICE_FLAG_INT_TX))
+ {
+ RT_ASSERT(0);
+ }
- device->type = RT_Device_Class_Char;
- device->rx_indicate = RT_NULL;
- device->tx_complete = RT_NULL;
- device->init = rt_serial_init;
- device->open = rt_serial_open;
- device->close = rt_serial_close;
- device->read = rt_serial_read;
- device->write = rt_serial_write;
- device->control = rt_serial_control;
- device->user_data = serial;
+ device->type = RT_Device_Class_Char;
+ device->rx_indicate = RT_NULL;
+ device->tx_complete = RT_NULL;
+ device->init = rt_serial_init;
+ device->open = rt_serial_open;
+ device->close = rt_serial_close;
+ device->read = rt_serial_read;
+ device->write = rt_serial_write;
+ device->control = rt_serial_control;
+ device->user_data = serial;
- /* register a character device */
- return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+ /* register a character device */
+ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/* ISR for serial interrupt */
void rt_hw_serial_isr(rt_device_t device)
{
- struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
- if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
- {
- /* interrupt mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+ if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+ {
+ /* interrupt mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
- /* save on rx buffer */
- while (uart->uart_device->SR & USART_FLAG_RXNE)
- {
- rt_base_t level;
+ /* save on rx buffer */
+ while (uart->uart_device->SR & USART_FLAG_RXNE)
+ {
+ rt_base_t level;
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
- /* save character */
- uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
- uart->int_rx->save_index ++;
- if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->save_index = 0;
+ /* save character */
+ uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
+ uart->int_rx->save_index ++;
+ if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->save_index = 0;
- /* if the next position is read index, discard this 'read char' */
- if (uart->int_rx->save_index == uart->int_rx->read_index)
- {
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
+ /* if the next position is read index, discard this 'read char' */
+ if (uart->int_rx->save_index == uart->int_rx->read_index)
+ {
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- }
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
- /* clear interrupt */
- USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+ /* clear interrupt */
+ USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
- /* invoke callback */
- if (device->rx_indicate != RT_NULL)
- {
- rt_size_t rx_length;
+ /* invoke callback */
+ if (device->rx_indicate != RT_NULL)
+ {
+ rt_size_t rx_length;
- /* get rx length */
- rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
- UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
- uart->int_rx->save_index - uart->int_rx->read_index;
+ /* get rx length */
+ rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+ UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+ uart->int_rx->save_index - uart->int_rx->read_index;
- device->rx_indicate(device, rx_length);
- }
- }
+ device->rx_indicate(device, rx_length);
+ }
+ }
- if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
- {
- /* clear interrupt */
- USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
- }
+ if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+ {
+ /* clear interrupt */
+ USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+ }
}
/*
@@ -368,47 +368,47 @@ void rt_hw_serial_isr(rt_device_t device)
*/
void rt_hw_serial_dma_tx_isr(rt_device_t device)
{
- rt_uint32_t level;
- struct stm32_serial_data_node* data_node;
- struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+ rt_uint32_t level;
+ struct stm32_serial_data_node* data_node;
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
- /* DMA mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
+ /* DMA mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
- /* get the first data node */
- data_node = uart->dma_tx->list_head;
- RT_ASSERT(data_node != RT_NULL);
+ /* get the first data node */
+ data_node = uart->dma_tx->list_head;
+ RT_ASSERT(data_node != RT_NULL);
- /* invoke call to notify tx complete */
- if (device->tx_complete != RT_NULL)
- device->tx_complete(device, data_node->data_ptr);
+ /* invoke call to notify tx complete */
+ if (device->tx_complete != RT_NULL)
+ device->tx_complete(device, data_node->data_ptr);
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
- /* remove list head */
- uart->dma_tx->list_head = data_node->next;
- if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
- uart->dma_tx->list_tail = RT_NULL;
+ /* remove list head */
+ uart->dma_tx->list_head = data_node->next;
+ if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
+ uart->dma_tx->list_tail = RT_NULL;
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
- /* release data node memory */
- rt_mp_free(data_node);
+ /* release data node memory */
+ rt_mp_free(data_node);
- if (uart->dma_tx->list_head != RT_NULL)
- {
- /* transmit next data node */
- rt_serial_enable_dma(uart->dma_tx->dma_channel,
- (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
- uart->dma_tx->list_head->data_size);
- }
- else
- {
- /* no data to be transmitted, disable DMA */
- DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
- }
+ if (uart->dma_tx->list_head != RT_NULL)
+ {
+ /* transmit next data node */
+ rt_serial_enable_dma(uart->dma_tx->dma_channel,
+ (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+ uart->dma_tx->list_head->data_size);
+ }
+ else
+ {
+ /* no data to be transmitted, disable DMA */
+ DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
+ }
}
/*@}*/
diff --git a/bsp/stm32f20x/Drivers/serial.h b/bsp/stm32f20x/Drivers/serial.h
index 8ab56b4839..4df341a0e3 100644
--- a/bsp/stm32f20x/Drivers/serial.h
+++ b/bsp/stm32f20x/Drivers/serial.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -17,45 +17,45 @@
/* STM32F10x library definitions */
#include
-#define UART_RX_BUFFER_SIZE 64
-#define UART_TX_DMA_NODE_SIZE 4
+#define UART_RX_BUFFER_SIZE 64
+#define UART_TX_DMA_NODE_SIZE 4
/* data node for Tx Mode */
struct stm32_serial_data_node
{
- rt_uint8_t *data_ptr;
- rt_size_t data_size;
- struct stm32_serial_data_node *next, *prev;
+ rt_uint8_t *data_ptr;
+ rt_size_t data_size;
+ struct stm32_serial_data_node *next, *prev;
};
struct stm32_serial_dma_tx
{
- /* DMA Channel */
- DMA_Stream_TypeDef* dma_channel;
+ /* DMA Channel */
+ DMA_Stream_TypeDef* dma_channel;
- /* data list head and tail */
- struct stm32_serial_data_node *list_head, *list_tail;
+ /* data list head and tail */
+ struct stm32_serial_data_node *list_head, *list_tail;
- /* data node memory pool */
- struct rt_mempool data_node_mp;
- rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
- (sizeof(struct stm32_serial_data_node) + sizeof(void*))];
+ /* data node memory pool */
+ struct rt_mempool data_node_mp;
+ rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
+ (sizeof(struct stm32_serial_data_node) + sizeof(void*))];
};
struct stm32_serial_int_rx
{
- rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
- rt_uint32_t read_index, save_index;
+ rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
+ rt_uint32_t read_index, save_index;
};
struct stm32_serial_device
{
- USART_TypeDef* uart_device;
+ USART_TypeDef* uart_device;
- /* rx structure */
- struct stm32_serial_int_rx* int_rx;
+ /* rx structure */
+ struct stm32_serial_int_rx* int_rx;
- /* tx structure */
- struct stm32_serial_dma_tx* dma_tx;
+ /* tx structure */
+ struct stm32_serial_dma_tx* dma_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
diff --git a/bsp/stm32f20x/Drivers/stm32f2_eth.c b/bsp/stm32f20x/Drivers/stm32f2_eth.c
index 1876c5bcaa..c774e16ed2 100644
--- a/bsp/stm32f20x/Drivers/stm32f2_eth.c
+++ b/bsp/stm32f20x/Drivers/stm32f2_eth.c
@@ -10,14 +10,14 @@
#include "stm32f2x7_eth.h"
#include "stm32f2x7_eth_conf.h"
-#define STM32_ETH_DEBUG 0
+#define STM32_ETH_DEBUG 0
//#define CHECKSUM_BY_HARDWARE /* don't ues hardware checksum. */
/* MII and RMII mode selection, for STM322xG-EVAL Board(MB786) RevB ***********/
-//#define MII_MODE
+//#define MII_MODE
#define RMII_MODE // In this case the System clock frequency is configured
- // to 100 MHz, for more details refer to system_stm32f2xx.c
+ // to 100 MHz, for more details refer to system_stm32f2xx.c
#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM322xG-EVAL Board */
@@ -27,10 +27,10 @@
extern ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
/* Ethernet Receive buffers */
-extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
+extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
/* Ethernet Transmit buffers */
-extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
+extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
/* Global pointers to track current transmit and receive descriptors */
extern ETH_DMADESCTypeDef *DMATxDescToSet;
@@ -42,11 +42,11 @@ extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
#define MAX_ADDR_LEN 6
struct rt_stm32_eth
{
- /* inherit from ethernet device */
- struct eth_device parent;
+ /* inherit from ethernet device */
+ struct eth_device parent;
- /* interface address info. */
- rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
+ /* interface address info. */
+ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct rt_stm32_eth stm32_eth_device;
static struct rt_semaphore tx_wait;
@@ -61,29 +61,29 @@ void ETH_IRQHandler(void)
{
rt_uint32_t status;
- status = ETH->DMASR;
+ status = ETH->DMASR;
- /* Frame received */
- if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET)
- {
- rt_err_t result;
- //rt_kprintf("Frame comming\n");
- /* Clear the interrupt flags. */
- /* Clear the Eth DMA Rx IT pending bits */
- ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
+ /* Frame received */
+ if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET)
+ {
+ rt_err_t result;
+ //rt_kprintf("Frame comming\n");
+ /* Clear the interrupt flags. */
+ /* Clear the Eth DMA Rx IT pending bits */
+ ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
- /* a frame has been received */
- result = eth_device_ready(&(stm32_eth_device.parent));
- if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result );
- //RT_ASSERT(result == RT_EOK);
- }
- if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
- {
- ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
- }
-
- ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
-//
+ /* a frame has been received */
+ result = eth_device_ready(&(stm32_eth_device.parent));
+ if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result );
+ //RT_ASSERT(result == RT_EOK);
+ }
+ if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
+ {
+ ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
+ }
+
+ ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
+//
}
@@ -91,244 +91,244 @@ void ETH_IRQHandler(void)
/* initialize the interface */
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
- int i;
+ int i;
- /* MAC address configuration */
- ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
-
- /* Initialize Tx Descriptors list: Chain Mode */
- ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
- /* Initialize Rx Descriptors list: Chain Mode */
- ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
+ /* MAC address configuration */
+ ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
- /* Enable Ethernet Rx interrrupt */
- {
- for(i=0; iDMASR );
-// rt_kprintf("ETH Init\n");
+ //rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
+// rt_kprintf("ETH Init\n");
return RT_EOK;
}
static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{
- return RT_EOK;
+ return RT_EOK;
}
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
- rt_set_errno(-RT_ENOSYS);
- return 0;
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
}
static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
- rt_set_errno(-RT_ENOSYS);
- return 0;
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
}
static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{
- switch(cmd)
- {
- case NIOCTL_GADDR:
- /* get mac address */
- if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
- else return -RT_ERROR;
- break;
+ switch(cmd)
+ {
+ case NIOCTL_GADDR:
+ /* get mac address */
+ if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+ else return -RT_ERROR;
+ break;
- default :
- break;
- }
+ default :
+ break;
+ }
- return RT_EOK;
+ return RT_EOK;
}
void show_frame(struct pbuf *q)
{
- int i = 0;
- int j = 0;
- char *ptr = q->payload;
+ int i = 0;
+ int j = 0;
+ char *ptr = q->payload;
- for( i = 0; i < q->len; i++ )
- rt_kprintf("0x%02X ", *(ptr++));
- rt_kprintf("\n");
+ for( i = 0; i < q->len; i++ )
+ rt_kprintf("0x%02X ", *(ptr++));
+ rt_kprintf("\n");
}
/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
{
- rt_err_t ret;
- struct pbuf *q;
- uint32_t l = 0;
- u8 *buffer ;
-
- if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK)
- {
- buffer = (u8 *)(DMATxDescToSet->Buffer1Addr);
- for(q = p; q != NULL; q = q->next)
- {
- //show_frame(q);
- rt_memcpy((u8_t*)&buffer[l], q->payload, q->len);
- l = l + q->len;
- }
- if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR )
- rt_kprintf("Tx Error\n");
- //rt_sem_release(xTxSemaphore);
- rt_sem_release(&tx_wait);
- //rt_kprintf("Tx packet, len = %d\n", l);
- }
- else
- {
- rt_kprintf("Tx Timeout\n");
- return ret;
- }
+ rt_err_t ret;
+ struct pbuf *q;
+ uint32_t l = 0;
+ u8 *buffer ;
- /* Return SUCCESS */
- return RT_EOK;
+ if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK)
+ {
+ buffer = (u8 *)(DMATxDescToSet->Buffer1Addr);
+ for(q = p; q != NULL; q = q->next)
+ {
+ //show_frame(q);
+ rt_memcpy((u8_t*)&buffer[l], q->payload, q->len);
+ l = l + q->len;
+ }
+ if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR )
+ rt_kprintf("Tx Error\n");
+ //rt_sem_release(xTxSemaphore);
+ rt_sem_release(&tx_wait);
+ //rt_kprintf("Tx packet, len = %d\n", l);
+ }
+ else
+ {
+ rt_kprintf("Tx Timeout\n");
+ return ret;
+ }
+
+ /* Return SUCCESS */
+ return RT_EOK;
}
/* reception packet. */
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{
- struct pbuf *p, *q;
- u16_t len;
- uint32_t l=0,i =0;
- FrameTypeDef frame;
- static framecnt = 1;
- u8 *buffer;
- __IO ETH_DMADESCTypeDef *DMARxNextDesc;
-
- p = RT_NULL;
-
-// rt_kprintf("ETH rx\n");
- /* Get received frame */
- frame = ETH_Get_Received_Frame_interrupt();
-
- if( frame.length > 0 )
- {
- /* check that frame has no error */
- if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET)
- {
- //rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length);
- /* Obtain the size of the packet and put it into the "len" variable. */
- len = frame.length;
- buffer = (u8 *)frame.buffer;
-
- /* We allocate a pbuf chain of pbufs from the pool. */
- p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
- //p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
+ struct pbuf *p, *q;
+ u16_t len;
+ uint32_t l=0,i =0;
+ FrameTypeDef frame;
+ static framecnt = 1;
+ u8 *buffer;
+ __IO ETH_DMADESCTypeDef *DMARxNextDesc;
- /* Copy received frame from ethernet driver buffer to stack buffer */
- if (p != NULL)
- {
- for (q = p; q != NULL; q = q->next)
- {
- rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
- l = l + q->len;
- }
- }
- }
-
- /* Release descriptors to DMA */
- /* Check if received frame with multiple DMA buffer segments */
- if (DMA_RX_FRAME_infos->Seg_Count > 1)
- {
- DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc;
- }
- else
- {
- DMARxNextDesc = frame.descriptor;
- }
-
- /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
- for (i=0; iSeg_Count; i++)
- {
- DMARxNextDesc->Status = ETH_DMARxDesc_OWN;
- DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr);
- }
-
- /* Clear Segment_Count */
- DMA_RX_FRAME_infos->Seg_Count =0;
-
-
- /* When Rx Buffer unavailable flag is set: clear it and resume reception */
- if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
- {
- /* Clear RBUS ETHERNET DMA flag */
- ETH->DMASR = ETH_DMASR_RBUS;
-
- /* Resume DMA reception */
- ETH->DMARPDR = 0;
- }
- }
- return p;
+ p = RT_NULL;
+
+// rt_kprintf("ETH rx\n");
+ /* Get received frame */
+ frame = ETH_Get_Received_Frame_interrupt();
+
+ if( frame.length > 0 )
+ {
+ /* check that frame has no error */
+ if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET)
+ {
+ //rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length);
+ /* Obtain the size of the packet and put it into the "len" variable. */
+ len = frame.length;
+ buffer = (u8 *)frame.buffer;
+
+ /* We allocate a pbuf chain of pbufs from the pool. */
+ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+ //p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
+
+ /* Copy received frame from ethernet driver buffer to stack buffer */
+ if (p != NULL)
+ {
+ for (q = p; q != NULL; q = q->next)
+ {
+ rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
+ l = l + q->len;
+ }
+ }
+ }
+
+ /* Release descriptors to DMA */
+ /* Check if received frame with multiple DMA buffer segments */
+ if (DMA_RX_FRAME_infos->Seg_Count > 1)
+ {
+ DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc;
+ }
+ else
+ {
+ DMARxNextDesc = frame.descriptor;
+ }
+
+ /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
+ for (i=0; iSeg_Count; i++)
+ {
+ DMARxNextDesc->Status = ETH_DMARxDesc_OWN;
+ DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr);
+ }
+
+ /* Clear Segment_Count */
+ DMA_RX_FRAME_infos->Seg_Count =0;
+
+
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
+ {
+ /* Clear RBUS ETHERNET DMA flag */
+ ETH->DMASR = ETH_DMASR_RBUS;
+
+ /* Resume DMA reception */
+ ETH->DMARPDR = 0;
+ }
+ }
+ return p;
}
static void NVIC_Configuration(void)
{
- NVIC_InitTypeDef NVIC_InitStructure;
-
- /* 2 bit for pre-emption priority, 2 bits for subpriority */
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
- /* Enable the Ethernet global Interrupt */
- NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
+ NVIC_InitTypeDef NVIC_InitStructure;
+
+ /* 2 bit for pre-emption priority, 2 bits for subpriority */
+ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+ /* Enable the Ethernet global Interrupt */
+ NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
}
/*
@@ -383,15 +383,15 @@ static void GPIO_Configuration(void)
ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12
ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13
- **** Just for MII Mode ****
- ETH_MII_CRS ----------------------> PA0
- ETH_MII_COL ----------------------> PA3
- ETH_MII_TX_CLK -------------------> PC3
- ETH_MII_RX_ER --------------------> PB10
- ETH_MII_RXD2 ---------------------> PB0
- ETH_MII_RXD3 ---------------------> PB1
- ETH_MII_TXD2 ---------------------> PC2
- ETH_MII_TXD3 ---------------------> PB8
+ **** Just for MII Mode ****
+ ETH_MII_CRS ----------------------> PA0
+ ETH_MII_COL ----------------------> PA3
+ ETH_MII_TX_CLK -------------------> PC3
+ ETH_MII_RX_ER --------------------> PB10
+ ETH_MII_RXD2 ---------------------> PB0
+ ETH_MII_RXD3 ---------------------> PB1
+ ETH_MII_TXD2 ---------------------> PC2
+ ETH_MII_TXD3 ---------------------> PB8
*/
/* Configure PC1, PC4 and PC5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5;
@@ -450,7 +450,7 @@ static void ETH_MACDMA_Config(void)
/* Enable ETHERNET clock */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
- RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
+ RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
/* Reset ETHERNET on AHB Bus */
ETH_DeInit();
@@ -468,9 +468,9 @@ static void ETH_MACDMA_Config(void)
/* Fill ETH_InitStructure parametrs */
/*------------------------ MAC -----------------------------------*/
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
- //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
+ //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
- // ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
+ // ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
@@ -484,95 +484,95 @@ static void ETH_MACDMA_Config(void)
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif
- /*------------------------ DMA -----------------------------------*/
-
- /* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
- the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
+ /*------------------------ DMA -----------------------------------*/
+
+ /* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
+ the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
- ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
- ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
- ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
-
- ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
- ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
+ ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+ ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+
+ ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+ ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
- ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
- ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
- ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
+ ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+ ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
+ ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
/* Configure Ethernet */
if( ETH_Init(Ð_InitStructure, DP83848_PHY_ADDRESS) == ETH_ERROR )
- rt_kprintf("ETH init error, may be no link\n");
+ rt_kprintf("ETH init error, may be no link\n");
/* Enable the Ethernet Rx Interrupt */
ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R , ENABLE);
}
-#define DevID_SNo0 (*((rt_uint32_t *)0x1FFF7A10));
-#define DevID_SNo1 (*((rt_uint32_t *)0x1FFF7A10+32));
+#define DevID_SNo0 (*((rt_uint32_t *)0x1FFF7A10));
+#define DevID_SNo1 (*((rt_uint32_t *)0x1FFF7A10+32));
#define DevID_SNo2 (*((rt_uint32_t *)0x1FFF7A10+64));
void rt_hw_stm32_eth_init(void)
{
- GPIO_Configuration();
- NVIC_Configuration();
- ETH_MACDMA_Config();
+ GPIO_Configuration();
+ NVIC_Configuration();
+ ETH_MACDMA_Config();
stm32_eth_device.dev_addr[0] = 0x00;
stm32_eth_device.dev_addr[1] = 0x60;
stm32_eth_device.dev_addr[2] = 0x6e;
- {
- uint32_t cpu_id[3] = {0};
- cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0;
-
- // generate MAC addr from 96bit unique ID (only for test)
- stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF);
- stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF);
- stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF);
+ {
+ uint32_t cpu_id[3] = {0};
+ cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0;
-// stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7);
-// stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8);
-// stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9);
- }
+ // generate MAC addr from 96bit unique ID (only for test)
+ stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF);
+ stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF);
+ stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF);
- stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
- stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
- stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
- stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
- stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
- stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
- stm32_eth_device.parent.parent.user_data = RT_NULL;
+// stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7);
+// stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8);
+// stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9);
+ }
- stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
- stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
+ stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
+ stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
+ stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
+ stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
+ stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
+ stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
+ stm32_eth_device.parent.parent.user_data = RT_NULL;
- /* init tx semaphore */
- rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO);
+ stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
+ stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
- /* register eth device */
- eth_device_init(&(stm32_eth_device.parent), "e0");
+ /* init tx semaphore */
+ rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO);
+
+ /* register eth device */
+ eth_device_init(&(stm32_eth_device.parent), "e0");
}
static char led = 0;
void dp83483()
{
- uint16_t bsr,sts, bcr, phycr;
+ uint16_t bsr,sts, bcr, phycr;
- bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR);
- sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
- bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR);
- phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
+ bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR);
+ sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
+ bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR);
+ phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
- rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr);
+ rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr);
- rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) );
- rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) );
+ rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) );
+ rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) );
- rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
+ rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
- //ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led));
- led = (led==7)?0:7;
+ //ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led));
+ led = (led==7)?0:7;
}
#ifdef RT_USING_FINSH
diff --git a/bsp/stm32f20x/Drivers/stm32f2xx_it.c b/bsp/stm32f20x/Drivers/stm32f2xx_it.c
index 6126d7173d..3a482fa747 100644
--- a/bsp/stm32f20x/Drivers/stm32f2xx_it.c
+++ b/bsp/stm32f20x/Drivers/stm32f2xx_it.c
@@ -1,11 +1,11 @@
/**
******************************************************************************
- * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c
+ * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
+ * This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
@@ -19,7 +19,7 @@
*
* © COPYRIGHT 2011 STMicroelectronics