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[bsp] format drivers code

This commit is contained in:
Meco Man 2024-03-23 21:14:37 -04:00
parent 1dc436feca
commit 814c37d4e3
59 changed files with 457 additions and 457 deletions
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2
bsp/allwinner/libraries/drivers/touch/drv_touch.c
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@ -1,5 +1,5 @@
/*
* COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
* COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd
* All rights reserved.
* Change Logs:
* Date Author Notes

2
bsp/allwinner/libraries/drivers/touch/drv_touch.h
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@ -1,5 +1,5 @@
/*
* COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
* COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd
* All rights reserved.
* Change Logs:
* Date Author Notes

16
bsp/avr32/drivers/drv_soft_i2c.c
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@ -50,11 +50,11 @@ static void avr32_set_sda(void *data, rt_int32_t state)
struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data;
if (state)
{
gpio_set_gpio_open_drain_pin(cfg->sda);
gpio_set_gpio_open_drain_pin(cfg->sda);
}
else
{
gpio_clr_gpio_open_drain_pin(cfg->sda);
gpio_clr_gpio_open_drain_pin(cfg->sda);
}
}
@ -69,11 +69,11 @@ static void avr32_set_scl(void *data, rt_int32_t state)
struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data;
if (state)
{
gpio_set_gpio_open_drain_pin(cfg->scl);
gpio_set_gpio_open_drain_pin(cfg->scl);
}
else
{
gpio_clr_gpio_open_drain_pin(cfg->scl);
gpio_clr_gpio_open_drain_pin(cfg->scl);
}
}
@ -126,10 +126,10 @@ static rt_err_t avr32_i2c_bus_unlock(const struct avr32_soft_i2c_config *cfg)
{
while (i++ < 9)
{
gpio_set_gpio_open_drain_pin(cfg->scl);
rt_hw_us_delay(100);
gpio_clr_gpio_open_drain_pin(cfg->scl);
rt_hw_us_delay(100);
gpio_set_gpio_open_drain_pin(cfg->scl);
rt_hw_us_delay(100);
gpio_clr_gpio_open_drain_pin(cfg->scl);
rt_hw_us_delay(100);
}
}
if (PIN_LOW == gpio_get_gpio_open_drain_pin_output_value(cfg->sda))

2
bsp/ft2004/drivers/drv_sdctrl.c
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@ -598,7 +598,7 @@ int rthw_sdctrl_init(void)
#endif
normalIrqFlgs |= NORMAL_IRQ_CC;
/* register handler、irq enable bit and wait callback */
/* register handler irq enable bit and wait callback */
FSdCtrl_SetHandler(ft_sdctrl_p, FTSDCTRL_CMDIRQID, rthw_sdctrl_nomarl_callback, ft_sdctrl_p);
FSdCtrl_NormalIrqSet(ft_sdctrl_p, normalIrqFlgs);
FSdCtrl_CmdWaitRegister(ft_sdctrl_p, rthw_sdctrl_cmd_wait);

4
bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c
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@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-06-05 zengjianwei first version
* Date Author Notes
* 2023-06-05 zengjianwei first version
*/
#include <board.h>

2
bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c
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@ -19,7 +19,7 @@
#define LOG_TAG "drv.sdio"
#include "drv_log.h"
#define SDIO_DMA_USE_IPC 0//1:使用ipc做同步
#define SDIO_DMA_USE_IPC 0//1:使用ipc做同步
/* card status of R1 definitions */
#define SD_R1_OUT_OF_RANGE BIT(31) /* command's argument was out of the allowed range */

148
bsp/mipssim/drivers/drv_uart.h
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@ -15,100 +15,100 @@
#include <rthw.h>
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* interrupt enable register */
#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
#define IER_IME 0x8 /* Modem状态中断使能 */
#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
#define IER_IME 0x8 /* Modem状态中断使能 */
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
// 线路控制寄存器
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
#endif

16
bsp/mm32l07x/drivers/drv_uart.c
View File

@ -36,7 +36,7 @@ struct mm32_uart
};
static rt_err_t mm32_uart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
struct serial_configure *cfg)
{
struct mm32_uart *uart;
UART_InitTypeDef UART_InitStructure;
@ -60,7 +60,7 @@ static rt_err_t mm32_uart_configure(struct rt_serial_device *serial,
}
static rt_err_t mm32_uart_control(struct rt_serial_device *serial,
int cmd, void *arg)
int cmd, void *arg)
{
struct mm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
@ -70,12 +70,12 @@ static rt_err_t mm32_uart_control(struct rt_serial_device *serial,
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->irq);
UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irq);
/* enable interrupt */
/* enable interrupt */
UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE);
break;
}
@ -215,8 +215,8 @@ int rt_hw_uart_init(void)
#ifdef BSP_USING_UART1
UART1PINconfigStepA();
uart = &uart1;
uart->uart = UART1;
uart->irq = UART1_IRQn;
uart->uart = UART1;
uart->irq = UART1_IRQn;
config.baud_rate = BAUD_RATE_115200;
serial1.ops = &mm32_uart_ops;
serial1.config = config;
@ -229,8 +229,8 @@ int rt_hw_uart_init(void)
#ifdef BSP_USING_UART2
UART2PINconfigStepA();
uart = &uart2;
uart->uart = UART2;
uart->irq = UART2_IRQn;
uart->uart = UART2;
uart->irq = UART2_IRQn;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &mm32_uart_ops;
serial2.config = config;

16
bsp/mm32l3xx/drivers/drv_uart.c
View File

@ -67,12 +67,12 @@ static rt_err_t mm32_uart_control(struct rt_serial_device *serial, int cmd, void
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->irq);
UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irq);
/* enable interrupt */
/* enable interrupt */
UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE);
break;
}
@ -167,7 +167,7 @@ static void UART1PINconfigStepA(void)
/* Enable UART clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
}
@ -193,7 +193,7 @@ static void UART2PINconfigStepA(void)
/* Enable UART clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
}
@ -219,8 +219,8 @@ int rt_hw_uart_init(void)
#ifdef BSP_USING_UART1
UART1PINconfigStepA();
uart = &uart1;
uart->uart = UART1;
uart->irq = UART1_IRQn;
uart->uart = UART1;
uart->irq = UART1_IRQn;
config.baud_rate = BAUD_RATE_115200;
serial1.ops = &mm32_uart_ops;
serial1.config = config;
@ -234,8 +234,8 @@ int rt_hw_uart_init(void)
#ifdef BSP_USING_UART2
UART2PINconfigStepA();
uart = &uart2;
uart->uart = UART2;
uart->irq = UART2_IRQn;
uart->uart = UART2;
uart->irq = UART2_IRQn;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &mm32_uart_ops;
serial2.config = config;

6
bsp/nxp/imx/imx6ull-smart/drivers/drv_touch.c
View File

@ -293,9 +293,9 @@ static rt_size_t gt911_read_point(struct rt_touch_device *touch, void *buf, rt_s
off_set = read_index * 8;
read_id = read_buf[off_set] & 0x0f;
pre_id[read_index] = read_id;
input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */
input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */
input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */
input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */
input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */
input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */
gt911_touch_down(buf, read_id, input_x, input_y, input_w);
}

2
bsp/rm48x50/drivers/drv_uart.c
View File

@ -194,7 +194,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
_sci2_serial.ops = &_sci_ops;
_sci2_serial.config = config;

6
bsp/smartfusion2/drivers/drv_uart.c
View File

@ -52,7 +52,7 @@ void uart1_rx_handler(mss_uart_instance_t *this_uart)
}
static rt_err_t sf2_uart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
struct serial_configure *cfg)
{
uint32_t baudRate;
uint8_t datBits, parity, stopBits;
@ -96,11 +96,11 @@ static rt_err_t sf2_uart_configure(struct rt_serial_device *serial,
else
MSS_UART_set_rx_handler(uart->uart, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE);
return RT_EOK;
return RT_EOK;
}
static rt_err_t sf2_uart_control(struct rt_serial_device *serial,
int cmd, void *arg)
int cmd, void *arg)
{
struct sf2_uart* uart;