Merge pull request #5019 from Jackistang/master

serial: add CTS/RTS flowcontrol.
This commit is contained in:
Bernard Xiong 2021-09-11 08:48:42 +08:00 committed by GitHub
commit 7c526cea93
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2 changed files with 19 additions and 2 deletions

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@ -107,10 +107,22 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
uart = rt_container_of(serial, struct stm32_uart, serial); uart = rt_container_of(serial, struct stm32_uart, serial);
uart->handle.Instance = uart->config->Instance; uart->handle.Instance = uart->config->Instance;
uart->handle.Init.BaudRate = cfg->baud_rate; uart->handle.Init.BaudRate = cfg->baud_rate;
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
uart->handle.Init.Mode = UART_MODE_TX_RX; uart->handle.Init.Mode = UART_MODE_TX_RX;
uart->handle.Init.OverSampling = UART_OVERSAMPLING_16; uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
switch (cfg->flowcontrol)
{
case RT_SERIAL_FLOWCONTROL_NONE:
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
break;
case RT_SERIAL_FLOWCONTROL_CTSRTS:
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
break;
default:
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
break;
}
switch (cfg->data_bits) switch (cfg->data_bits)
{ {
case DATA_BITS_8: case DATA_BITS_8:

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@ -77,6 +77,9 @@
#define RT_SERIAL_TX_DATAQUEUE_SIZE 2048 #define RT_SERIAL_TX_DATAQUEUE_SIZE 2048
#define RT_SERIAL_TX_DATAQUEUE_LWM 30 #define RT_SERIAL_TX_DATAQUEUE_LWM 30
#define RT_SERIAL_FLOWCONTROL_CTSRTS 1
#define RT_SERIAL_FLOWCONTROL_NONE 0
/* Default config for serial_configure structure */ /* Default config for serial_configure structure */
#define RT_SERIAL_CONFIG_DEFAULT \ #define RT_SERIAL_CONFIG_DEFAULT \
{ \ { \
@ -87,6 +90,7 @@
BIT_ORDER_LSB, /* LSB first sent */ \ BIT_ORDER_LSB, /* LSB first sent */ \
NRZ_NORMAL, /* Normal mode */ \ NRZ_NORMAL, /* Normal mode */ \
RT_SERIAL_RB_BUFSZ, /* Buffer size */ \ RT_SERIAL_RB_BUFSZ, /* Buffer size */ \
RT_SERIAL_FLOWCONTROL_NONE, /* Off flowcontrol */ \
0 \ 0 \
} }
@ -100,7 +104,8 @@ struct serial_configure
rt_uint32_t bit_order :1; rt_uint32_t bit_order :1;
rt_uint32_t invert :1; rt_uint32_t invert :1;
rt_uint32_t bufsz :16; rt_uint32_t bufsz :16;
rt_uint32_t reserved :6; rt_uint32_t flowcontrol :1;
rt_uint32_t reserved :5;
}; };
/* /*