[components][sdio] Support DDR mode
This commit is contained in:
tyx
guo
parent
556b14ed47
commit
782b9dd45a
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@ -22,82 +22,82 @@ extern "C" {
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* EXT_CSD fields
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*/
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#define EXT_CSD_FLUSH_CACHE 32 /* W */
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#define EXT_CSD_CACHE_CTRL 33 /* R/W */
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#define EXT_CSD_FLUSH_CACHE 32 /* W */
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#define EXT_CSD_CACHE_CTRL 33 /* R/W */
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#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
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#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
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#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
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#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
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#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
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#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
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#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
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#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
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#define EXT_CSD_HPI_MGMT 161 /* R/W */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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#define EXT_CSD_BKOPS_EN 163 /* R/W */
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#define EXT_CSD_BKOPS_START 164 /* W */
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#define EXT_CSD_SANITIZE_START 165 /* W */
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#define EXT_CSD_WR_REL_PARAM 166 /* RO */
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#define EXT_CSD_RPMB_MULT 168 /* RO */
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#define EXT_CSD_BOOT_WP 173 /* R/W */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_PART_CONFIG 179 /* R/W */
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#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_POWER_CLASS 187 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_STRUCTURE 194 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
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#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
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#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
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#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
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#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
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#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
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#define EXT_CSD_HPI_MGMT 161 /* R/W */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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#define EXT_CSD_BKOPS_EN 163 /* R/W */
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#define EXT_CSD_BKOPS_START 164 /* W */
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#define EXT_CSD_SANITIZE_START 165 /* W */
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#define EXT_CSD_WR_REL_PARAM 166 /* RO */
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#define EXT_CSD_RPMB_MULT 168 /* RO */
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#define EXT_CSD_BOOT_WP 173 /* R/W */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_PART_CONFIG 179 /* R/W */
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#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_POWER_CLASS 187 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_STRUCTURE 194 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
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#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
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#define EXT_CSD_PWR_CL_52_195 200 /* RO */
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#define EXT_CSD_PWR_CL_26_195 201 /* RO */
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#define EXT_CSD_PWR_CL_52_360 202 /* RO */
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#define EXT_CSD_PWR_CL_26_360 203 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
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#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
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#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
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#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_BOOT_MULT 226 /* RO */
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#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
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#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
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#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
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#define EXT_CSD_TRIM_MULT 232 /* RO */
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#define EXT_CSD_PWR_CL_200_195 236 /* RO */
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#define EXT_CSD_PWR_CL_200_360 237 /* RO */
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#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
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#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
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#define EXT_CSD_BKOPS_STATUS 246 /* RO */
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#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
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#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
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#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
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#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
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#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
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#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
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#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
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#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
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#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
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#define EXT_CSD_HPI_FEATURES 503 /* RO */
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#define EXT_CSD_PWR_CL_52_195 200 /* RO */
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#define EXT_CSD_PWR_CL_26_195 201 /* RO */
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#define EXT_CSD_PWR_CL_52_360 202 /* RO */
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#define EXT_CSD_PWR_CL_26_360 203 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
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#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
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#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
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#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_BOOT_MULT 226 /* RO */
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#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
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#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
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#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
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#define EXT_CSD_TRIM_MULT 232 /* RO */
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#define EXT_CSD_PWR_CL_200_195 236 /* RO */
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#define EXT_CSD_PWR_CL_200_360 237 /* RO */
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#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
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#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
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#define EXT_CSD_BKOPS_STATUS 246 /* RO */
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#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
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#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
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#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
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#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
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#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
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#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
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#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
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#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
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#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
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#define EXT_CSD_HPI_FEATURES 503 /* RO */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
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#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
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#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
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#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
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#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
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#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
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#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
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#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
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#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
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#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
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@ -125,18 +125,18 @@ extern "C" {
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#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
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EXT_CSD_CARD_TYPE_HS400_1_2V)
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
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#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
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#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
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#define EXT_CSD_TIMING_HS 1 /* High speed */
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#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
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#define EXT_CSD_TIMING_HS 1 /* High speed */
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#define EXT_CSD_TIMING_HS200 2 /* HS200 */
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#define EXT_CSD_TIMING_HS400 3 /* HS400 */
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#define EXT_CSD_SEC_ER_EN BIT(0)
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#define EXT_CSD_SEC_ER_EN BIT(0)
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#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
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#define EXT_CSD_SEC_GB_CL_EN BIT(4)
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#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
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@ -145,9 +145,9 @@ extern "C" {
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#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
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#define EXT_CSD_NO_POWER_NOTIFICATION 0
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#define EXT_CSD_POWER_ON 1
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#define EXT_CSD_POWER_OFF_SHORT 2
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#define EXT_CSD_POWER_OFF_LONG 3
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#define EXT_CSD_POWER_ON 1
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#define EXT_CSD_POWER_OFF_SHORT 2
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#define EXT_CSD_POWER_OFF_LONG 3
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#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
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#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
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@ -45,7 +45,8 @@ struct rt_mmcsd_io_cfg {
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#define MMCSD_BUS_WIDTH_1 0
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#define MMCSD_BUS_WIDTH_4 2
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#define MMCSD_BUS_WIDTH_8 3
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#define MMCSD_DDR_BUS_WIDTH_4 4
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#define MMCSD_DDR_BUS_WIDTH_8 5
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};
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struct rt_mmcsd_host;
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@ -90,6 +91,9 @@ struct rt_mmcsd_host {
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#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI)
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#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */
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#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */
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#define MMCSD_SUP_HIGHSPEED_DDR (1 << 6) /* support high speed(DDR) */
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#define MMCSD_SUP_HIGHSPEED_HS200 (1 << 7) /* support high speed HS200 */
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#define MMCSD_SUP_HIGHSPEED_HS400 (1 << 8) /* support high speed HS400 */
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rt_uint32_t max_seg_size; /* maximum size of one dma segment */
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rt_uint32_t max_dma_segs; /* maximum number of dma segments in one request */
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@ -290,10 +290,19 @@ out:
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static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd)
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{
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rt_uint32_t ext_csd_bits[] = {
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EXT_CSD_DDR_BUS_WIDTH_8,
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EXT_CSD_DDR_BUS_WIDTH_4,
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EXT_CSD_BUS_WIDTH_8,
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EXT_CSD_BUS_WIDTH_4,
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EXT_CSD_BUS_WIDTH_1
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};
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rt_uint32_t bus_widths[] = {
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MMCSD_DDR_BUS_WIDTH_8,
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MMCSD_DDR_BUS_WIDTH_4,
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MMCSD_BUS_WIDTH_8,
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MMCSD_BUS_WIDTH_4,
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MMCSD_BUS_WIDTH_1
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};
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struct rt_mmcsd_host *host = card->host;
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unsigned idx, trys, bus_width = 0;
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int err = 0;
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@ -317,12 +326,25 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd)
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* bail out early if corresponding bus capable wasn't
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* set by drivers.
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*/
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if ((!(host->flags & MMCSD_BUSWIDTH_8) &&
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ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8) ||
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(!(host->flags & MMCSD_BUSWIDTH_4) &&
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(ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_4 ||
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ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8)))
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continue;
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if ((!((host->flags & MMCSD_BUSWIDTH_8) &&
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(host->flags & MMCSD_SUP_HIGHSPEED_DDR)) &&
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ext_csd_bits[idx] == EXT_CSD_DDR_BUS_WIDTH_8) ||
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(!((host->flags & MMCSD_BUSWIDTH_4) &&
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(host->flags & MMCSD_SUP_HIGHSPEED_DDR)) &&
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ext_csd_bits[idx] == EXT_CSD_DDR_BUS_WIDTH_4) ||
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(!(host->flags & MMCSD_BUSWIDTH_8) &&
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ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_8) ||
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(!(host->flags & MMCSD_BUSWIDTH_4) &&
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ext_csd_bits[idx] == EXT_CSD_BUS_WIDTH_4))
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continue;
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if (host->flags & MMCSD_SUP_HIGHSPEED_DDR)
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{
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/* HS_TIMING must be set to "0x1" before setting BUS_WIDTH for dual-data-rate(DDR) operation */
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err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS);
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if (err)
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LOG_E("switch to speed mode width hight speed failed!");
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}
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err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_BUS_WIDTH,
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@ -330,6 +352,7 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd)
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if (err)
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continue;
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bus_width = bus_widths[idx];
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for(trys = 0; trys < 5; trys++){
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mmcsd_set_bus_width(host, bus_width);
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mmcsd_delay_ms(10);
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@ -342,14 +365,20 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd)
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break;
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} else {
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switch(ext_csd_bits[idx]){
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case 0:
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LOG_E("switch to bus width 1 bit failed!");
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case EXT_CSD_DDR_BUS_WIDTH_8:
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LOG_E("switch to bus width DDR 8 bit failed!");
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break;
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case 1:
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case EXT_CSD_DDR_BUS_WIDTH_4:
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LOG_E("switch to bus width DDR 4 bit failed!");
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break;
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case EXT_CSD_BUS_WIDTH_8:
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LOG_E("switch to bus width 8 bit failed!");
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break;
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case EXT_CSD_BUS_WIDTH_4:
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LOG_E("switch to bus width 4 bit failed!");
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break;
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case 2:
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LOG_E("switch to bus width 8 bit failed!");
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case EXT_CSD_BUS_WIDTH_1:
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LOG_E("switch to bus width 1 bit failed!");
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break;
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default:
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break;
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@ -743,7 +743,11 @@ static rt_int32_t sdio_set_highspeed(struct rt_mmcsd_card *card)
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rt_int32_t ret;
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rt_uint8_t speed;
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if (!(card->host->flags & MMCSD_SUP_HIGHSPEED))
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if (!(card->host->flags &
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(MMCSD_SUP_HIGHSPEED |
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MMCSD_SUP_HIGHSPEED_DDR |
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MMCSD_SUP_HIGHSPEED_HS200 |
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MMCSD_SUP_HIGHSPEED_HS400)))
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return 0;
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if (!card->cccr.high_speed)
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