From 73391c60fb7b26c5c05188b065196eea75d63145 Mon Sep 17 00:00:00 2001 From: thread-liu Date: Thu, 26 Nov 2020 14:29:41 +0800 Subject: [PATCH] [add] crc, rng, hash and cryp driver for smt32mp1. --- bsp/stm32/libraries/HAL_Drivers/Kconfig | 16 +- .../HAL_Drivers/config/mp1/dma_config.h | 112 +++-- bsp/stm32/libraries/HAL_Drivers/drv_crypto.c | 413 +++++++++++++++- bsp/stm32/libraries/STM32MPxx_HAL/SConscript | 27 +- bsp/stm32/stm32mp157a-st-discovery/.config | 58 ++- .../CM4/Inc/stm32mp1xx_hal_conf.h | 8 +- .../CM4/Src/stm32mp1xx_hal_msp.c | 248 +++++++++- .../stm32mp157a-st-discovery/board/SConscript | 3 + .../board/ports/crypto/crypto_sample.c | 449 ++++++++++++++++++ 9 files changed, 1244 insertions(+), 90 deletions(-) create mode 100644 bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c diff --git a/bsp/stm32/libraries/HAL_Drivers/Kconfig b/bsp/stm32/libraries/HAL_Drivers/Kconfig index 45160eee82..41cf5cf08b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/Kconfig +++ b/bsp/stm32/libraries/HAL_Drivers/Kconfig @@ -40,7 +40,21 @@ config BSP_USING_RNG depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \ SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1) default n - + +config BSP_USING_HASH + bool "Enable HASH (Hash House Harriers)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_HASH + depends on (SOC_SERIES_STM32MP1) + default n + +config BSP_USING_CRYP + bool "Enable CRYP (Encrypt And Decrypt Data)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRYP + depends on (SOC_SERIES_STM32MP1) + default n + config BSP_USING_UDID bool "Enable UDID (Unique Device Identifier)" select RT_USING_HWCRYPTO diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h index b56973ec98..8a2fc3a5fe 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h @@ -1,13 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-01-02 zylx first version - * 2019-01-08 SummerGift clean up the code - * 2020-06-20 thread-liu add stm32mp1 + * 2020-06-20 thread-liu first version */ #ifndef __DMA_CONFIG_H__ @@ -19,6 +17,22 @@ extern "C" { #endif +/* DMA1 stream0 */ + +/* DMA1 stream1 */ + +/* DMA1 stream2 */ + +/* DMA1 stream3 */ + +/* DMA1 stream4 */ + +/* DMA1 stream5 */ + +/* DMA1 stream6 */ + +/* DMA1 stream7 */ + /* DMA2 stream0 */ #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) #define UART3_RX_DMA_IRQHandler DMA2_Stream0_IRQHandler @@ -26,18 +40,12 @@ extern "C" { #define UART3_RX_DMA_INSTANCE DMA2_Stream0 #define UART3_RX_DMA_CHANNEL DMA_REQUEST_USART3_RX #define UART3_RX_DMA_IRQ DMA2_Stream0_IRQn -#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 -#define SPI4_RX_DMA_CHANNEL DMA_REQUEST_SPI4_RX -#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn -#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) -#define UART5_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define UART5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART5_RX_DMA_INSTANCE DMA2_Stream0 -#define UART5_RX_DMA_CHANNEL DMA_REQUEST_UART5_RX -#define UART5_RX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX +#define SPI5_RX_DMA_IRQ DMA2_Stream0_IRQn #endif /* DMA2 stream1 */ @@ -47,12 +55,12 @@ extern "C" { #define UART3_TX_DMA_INSTANCE DMA2_Stream1 #define UART3_TX_DMA_CHANNEL DMA_REQUEST_USART3_TX #define UART3_TX_DMA_IRQ DMA2_Stream1_IRQn -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler -#define SPI4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 -#define SPI4_TX_DMA_CHANNEL DMA_REQUEST_SPI4_TX -#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI5_TX_DMA_CHANNEL DMA_REQUEST_SPI5_TX +#define SPI5_TX_DMA_IRQ DMA2_Stream1_IRQn #endif /* DMA2 stream2 */ @@ -65,48 +73,48 @@ extern "C" { #endif /* DMA2 stream3 */ -#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) -#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 -#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX -#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define UART4_RX_DMA_INSTANCE DMA2_Stream3 +#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX +#define UART4_RX_DMA_IRQ DMA2_Stream3_IRQn #endif /* DMA2 stream4 */ -#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) -#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI5_TX_DMA_CHANNEL DMA_REQUEST_SPI5_TX -#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) +#define UART4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define UART4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define UART4_TX_DMA_INSTANCE DMA2_Stream4 +#define UART4_TX_DMA_CHANNEL DMA_REQUEST_UART4_TX +#define UART4_TX_DMA_IRQ DMA2_Stream4_IRQn #endif /* DMA2 stream5 */ -#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART4_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler -#define UART4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART4_TX_DMA_INSTANCE DMA2_Stream5 -#define UART4_TX_DMA_CHANNEL DMA_REQUEST_UART4_TX -#define UART4_TX_DMA_IRQ DMA2_Stream5_IRQn +#if defined(BSP_USING_CRYP) && !defined(CRYP2_OUT_DMA_INSTANCE) +#define CRYP2_DMA_OUT_IRQHandler DMA2_Stream5_IRQHandler +#define CRYP2_OUT_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define CRYP2_OUT_DMA_INSTANCE DMA2_Stream5 +#define CRYP2_OUT_DMA_CHANNEL DMA_REQUEST_CRYP2_OUT +#define CRYP2_OUT_DMA_IRQ DMA2_Stream5_IRQn #endif /* DMA2 stream6 */ -#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler -#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART4_RX_DMA_INSTANCE DMA2_Stream6 -#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX -#define UART4_RX_DMA_IRQ DMA2_Stream6_IRQn +#if defined(BSP_USING_CRYP) && !defined(CRYP2_IN_DMA_INSTANCE) +#define CRYP2_DMA_IN_IRQHandler DMA2_Stream6_IRQHandler +#define CRYP2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define CRYP2_IN_DMA_INSTANCE DMA2_Stream6 +#define CRYP2_IN_DMA_CHANNEL DMA_REQUEST_CRYP2_IN +#define CRYP2_IN_DMA_IRQ DMA2_Stream6_IRQn #endif /* DMA2 stream7 */ -#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART5_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler -#define UART5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN -#define UART5_TX_DMA_INSTANCE DMA2_Stream7 -#define UART5_TX_DMA_CHANNEL DMA_REQUEST_UART5_TX -#define UART5_TX_DMA_IRQ DMA2_Stream7_IRQn +#if defined(BSP_USING_HASH) && !defined(HASH2_IN_DMA_INSTANCE) +#define HASH2_DMA_IN_IRQHandler DMA2_Stream7_IRQHandler +#define HASH2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN +#define HASH2_IN_DMA_INSTANCE DMA2_Stream7 +#define HASH2_IN_DMA_CHANNEL DMA_REQUEST_HASH2_IN +#define HASH2_IN_DMA_IRQ DMA2_Stream7_IRQn #endif #ifdef __cplusplus diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c b/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c index e82446c4a6..c196c615c5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c @@ -7,6 +7,8 @@ * Date Author Notes * 2019-07-10 Ernest 1st version * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-11-26 thread-liu add hash + * 2020-11-26 thread-liu add cryp */ #include @@ -15,7 +17,8 @@ #include #include "drv_crypto.h" #include "board.h" - +#include "drv_config.h" + struct stm32_hwcrypto_device { struct rt_hwcrypto_device dev; @@ -24,12 +27,7 @@ struct stm32_hwcrypto_device #if defined(BSP_USING_CRC) -struct hash_ctx_des -{ - CRC_HandleTypeDef contex; -}; - -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) static struct hwcrypto_crc_cfg crc_backup_cfg; static int reverse_bit(rt_uint32_t n) @@ -49,12 +47,12 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r rt_uint32_t result = 0; struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; -#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex); #endif rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0) { if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE) @@ -113,7 +111,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length); -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) if (HW_TypeDef->Init.OutputDataInversionMode) { ctx ->crc_cfg.last_val = reverse_bit(result); @@ -159,10 +157,213 @@ static const struct hwcrypto_rng_ops rng_ops = }; #endif /* BSP_USING_RNG */ +#if defined(BSP_USING_HASH) +static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt_size_t length) +{ + rt_uint32_t tickstart = 0; + rt_uint32_t result = RT_EOK; + struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; + rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); + +#if defined(SOC_SERIES_STM32MP1) + HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex); + /* Start HASH computation using DMA transfer */ + switch (ctx->parent.type) + { + case HWCRYPTO_TYPE_SHA224: + result = HAL_HASHEx_SHA224_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + case HWCRYPTO_TYPE_SHA256: + result = HAL_HASHEx_SHA256_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + case HWCRYPTO_TYPE_MD5: + result = HAL_HASH_MD5_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + case HWCRYPTO_TYPE_SHA1: + result = HAL_HASH_SHA1_Start_DMA(HW_TypeDef, (uint8_t *)in, length); + break; + default : + rt_kprintf("not support hash type: %x", ctx->parent.type); + break; + } + if (result != HAL_OK) + { + goto _exit; + } + /* Wait for DMA transfer to complete */ + tickstart = rt_tick_get(); + while (HAL_HASH_GetState(HW_TypeDef) == HAL_HASH_STATE_BUSY) + { + if (rt_tick_get() - tickstart > 0xFFFF) + { + result = RT_ETIMEOUT; + goto _exit; + } + } + +#endif +_exit: + rt_mutex_release(&stm32_hw_dev->mutex); + + return result; +} + +static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size_t length) +{ + rt_uint32_t result = RT_EOK; + struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; + rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); +#if defined(SOC_SERIES_STM32MP1) + HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex); + /* Get the computed digest value */ + switch (ctx->parent.type) + { + case HWCRYPTO_TYPE_SHA224: + result = HAL_HASHEx_SHA224_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + case HWCRYPTO_TYPE_SHA256: + result = HAL_HASHEx_SHA256_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + case HWCRYPTO_TYPE_MD5: + result = HAL_HASH_MD5_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + case HWCRYPTO_TYPE_SHA1: + result = HAL_HASH_SHA1_Finish(HW_TypeDef, (uint8_t *)out, length); + break; + + default : + rt_kprintf("not support hash type: %x", ctx->parent.type); + break; + } + if (result != HAL_OK) + { + goto _exit; + } +#endif + +_exit: + rt_mutex_release(&stm32_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_hash_ops hash_ops = +{ + .update = _hash_update, + .finish = _hash_finish +}; + +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) +static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, + struct hwcrypto_symmetric_info *info) +{ + rt_uint32_t result = RT_EOK; + rt_uint32_t tickstart = 0; + + struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; + rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); + +#if defined(SOC_SERIES_STM32MP1) + CRYP_HandleTypeDef *HW_TypeDef = (CRYP_HandleTypeDef *)(ctx->parent.contex); + + switch (ctx->parent.type) + { + case HWCRYPTO_TYPE_AES_ECB: + HW_TypeDef->Init.Algorithm = CRYP_AES_ECB; + break; + + case HWCRYPTO_TYPE_AES_CBC: + HW_TypeDef->Init.Algorithm = CRYP_AES_CBC; + break; + + case HWCRYPTO_TYPE_AES_CTR: + HW_TypeDef->Init.Algorithm = CRYP_AES_CTR; + break; + + case HWCRYPTO_TYPE_DES_ECB: + HW_TypeDef->Init.Algorithm = CRYP_DES_ECB; + break; + + case HWCRYPTO_TYPE_DES_CBC: + HW_TypeDef->Init.Algorithm = CRYP_DES_CBC; + break; + + default : + rt_kprintf("not support cryp type: %x", ctx->parent.type); + break; + } + + HAL_CRYP_DeInit(HW_TypeDef); + + HW_TypeDef->Init.DataType = CRYP_DATATYPE_8B; + HW_TypeDef->Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE; + HW_TypeDef->Init.KeySize = CRYP_KEYSIZE_128B; + HW_TypeDef->Init.pKey = (uint32_t*)ctx->key; + + result = HAL_CRYP_Init(HW_TypeDef); + if (result != HAL_OK) + { + /* Initialization Error */ + goto _exit; + } + if (info->mode == HWCRYPTO_MODE_ENCRYPT) + { + result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out); + } + else if (info->mode == HWCRYPTO_MODE_DECRYPT) + { + result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out); + } + else + { + rt_kprintf("error cryp mode : %02x!\n", info->mode); + result = RT_ERROR; + goto _exit; + } + + if (result != HAL_OK) + { + goto _exit; + } + + tickstart = rt_tick_get(); + while (HAL_CRYP_GetState(HW_TypeDef) != HAL_CRYP_STATE_READY) + { + if (rt_tick_get() - tickstart > 0xFFFF) + { + result = RT_ETIMEOUT; + goto _exit; + } + } + +#endif + + if (result != HAL_OK) + { + goto _exit; + } + +_exit: + rt_mutex_release(&stm32_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_symmetric_ops cryp_ops = +{ + .crypt = _cryp_crypt +}; +#endif + static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) { rt_err_t res = RT_EOK; - + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) { #if defined(BSP_USING_RNG) @@ -174,8 +375,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) res = -RT_ERROR; break; } - +#if defined(SOC_SERIES_STM32MP1) + hrng->Instance = RNG2; +#else hrng->Instance = RNG; +#endif HAL_RNG_Init(hrng); ctx->contex = hrng; ((struct hwcrypto_rng *)ctx)->ops = &rng_ops; @@ -193,9 +397,12 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) res = -RT_ERROR; break; } - +#if defined(SOC_SERIES_STM32MP1) + hcrc->Instance = CRC2; +#else hcrc->Instance = CRC; -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#endif +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1) hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE; hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE; @@ -209,9 +416,77 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) #endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */ ctx->contex = hcrc; ((struct hwcrypto_crc *)ctx)->ops = &crc_ops; + break; } #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + { + HASH_HandleTypeDef *hash = rt_calloc(1, sizeof(HASH_HandleTypeDef)); + if (RT_NULL == hash) + { + res = -RT_ERROR; + break; + } +#if defined(SOC_SERIES_STM32MP1) + /* enable dma for hash */ + __HAL_RCC_DMA2_CLK_ENABLE(); + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + + hash->Init.DataType = HASH_DATATYPE_8B; + if (HAL_HASH_Init(hash) != HAL_OK) + { + res = -RT_ERROR; + } +#endif + ctx->contex = hash; + ((struct hwcrypto_hash *)ctx)->ops = &hash_ops; + + break; + } +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + { + CRYP_HandleTypeDef *cryp = rt_calloc(1, sizeof(CRYP_HandleTypeDef)); + if (RT_NULL == cryp) + { + res = -RT_ERROR; + break; + } +#if defined(SOC_SERIES_STM32MP1) + cryp->Instance = CRYP2; + /* enable dma for cryp */ + __HAL_RCC_DMA2_CLK_ENABLE(); + + HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); + + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + + if (HAL_CRYP_Init(cryp) != HAL_OK) + { + res = -RT_ERROR; + } +#endif + ctx->contex = cryp; + ((struct hwcrypto_symmetric *)ctx)->ops = &cryp_ops; + + break; + } +#endif /* BSP_USING_CRYP */ + default: res = -RT_ERROR; break; @@ -234,6 +509,26 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex)); break; #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex)); + HAL_HASH_DeInit((HASH_HandleTypeDef *)(ctx->contex)); + break; +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + HAL_CRYP_DeInit((CRYP_HandleTypeDef *)(ctx->contex)); + break; +#endif /* BSP_USING_CRYP */ + default: break; } @@ -251,7 +546,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry case HWCRYPTO_TYPE_RNG: if (des->contex && src->contex) { - rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des)); + rt_memcpy(des->contex, src->contex, sizeof(RNG_HandleTypeDef)); } break; #endif /* BSP_USING_RNG */ @@ -260,10 +555,35 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry case HWCRYPTO_TYPE_CRC: if (des->contex && src->contex) { - rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des)); + rt_memcpy(des->contex, src->contex, sizeof(CRC_HandleTypeDef)); } break; #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(HASH_HandleTypeDef)); + } + break; +#endif /* BSP_USING_HASH */ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(CRYP_HandleTypeDef)); + } + break; +#endif /* BSP_USING_CRYP */ + default: res = -RT_ERROR; break; @@ -285,11 +605,68 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx) __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex); break; #endif /* BSP_USING_CRC */ + +#if defined(BSP_USING_HASH) + case HWCRYPTO_TYPE_MD5: + case HWCRYPTO_TYPE_SHA1: + case HWCRYPTO_TYPE_SHA2: + __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex)); + break; +#endif /* BSP_USING_HASH*/ + +#if defined(BSP_USING_CRYP) + case HWCRYPTO_TYPE_AES: + case HWCRYPTO_TYPE_DES: + case HWCRYPTO_TYPE_3DES: + case HWCRYPTO_TYPE_RC4: + case HWCRYPTO_TYPE_GCM: + break; +#endif /* BSP_USING_CRYP */ + default: break; } } +void HASH2_DMA_IN_IRQHandler(void) +{ + extern DMA_HandleTypeDef hdma_hash_in; + + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_hash_in); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void CRYP2_DMA_IN_IRQHandler(void) +{ + extern DMA_HandleTypeDef hdma_cryp_in; + + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_cryp_in); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void CRYP2_DMA_OUT_IRQHandler(void) +{ + extern DMA_HandleTypeDef hdma_cryp_out; + + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&hdma_cryp_out); + + /* leave interrupt */ + rt_interrupt_leave(); +} + static const struct rt_hwcrypto_ops _ops = { .create = _crypto_create, @@ -306,10 +683,10 @@ int stm32_hw_crypto_device_init(void) _crypto_dev.dev.ops = &_ops; #if defined(BSP_USING_UDID) -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) cpuid[0] = HAL_GetUIDw0(); cpuid[1] = HAL_GetUIDw1(); -#elif defined(SOC_SERIES_STM32H7) +#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) cpuid[0] = HAL_GetREVID(); cpuid[1] = HAL_GetDEVID(); #endif diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript index dc63174324..7dc020bf65 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript @@ -35,10 +35,6 @@ if GetDepend(['RT_USING_SERIAL']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c'] -#if GetDepend(['RT_USING_SPI']): -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c'] -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c'] - if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pccard.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pcd.c'] @@ -49,14 +45,6 @@ if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): if GetDepend(['RT_USING_CAN']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_can.c'] -#if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']): -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c'] -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c'] -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c'] - -# if GetDepend(['BSP_USING_ETH']): -# src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c'] - if GetDepend(['BSP_USING_WWDG']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c'] @@ -104,6 +92,21 @@ if GetDepend(['BSP_USING_SDMMC']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c'] +if GetDepend(['BSP_USING_HASH']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hash.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hash_ex.c'] + +if GetDepend(['BSP_USING_CRC']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_crc_ex.c'] + +if GetDepend(['BSP_USING_RNG']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rng.c'] + +if GetDepend(['BSP_USING_CRYP']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp_ex.c'] + path = [cwd + '/STM32MP1xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32MP1xx/Include', cwd + '/CMSIS/Core/Include', diff --git a/bsp/stm32/stm32mp157a-st-discovery/.config b/bsp/stm32/stm32mp157a-st-discovery/.config index 01ca2120fa..5715750c67 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/.config +++ b/bsp/stm32/stm32mp157a-st-discovery/.config @@ -123,6 +123,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -199,12 +200,15 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -231,6 +235,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -243,7 +248,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -265,6 +270,11 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # # security packages @@ -273,6 +283,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -289,6 +300,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set # # tools packages @@ -307,6 +320,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -318,6 +334,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -330,6 +347,19 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -367,6 +397,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -374,6 +405,17 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set # # miscellaneous packages @@ -403,13 +445,20 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32MP1=y @@ -427,6 +476,10 @@ CONFIG_BSP_USING_STLINK_TO_USART=y # CONFIG_BSP_USING_PWR is not set # CONFIG_BSP_USING_RCC is not set # CONFIG_BSP_USING_OPENAMP is not set +# CONFIG_BSP_USING_RS485 is not set +# CONFIG_BSP_USING_GBE is not set +# CONFIG_BSP_USING_SDMMC is not set +# CONFIG_BSP_USING_AUDIO is not set # # On-chip Peripheral Drivers @@ -435,7 +488,6 @@ CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_WWDG is not set CONFIG_BSP_USING_UART=y # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_UART3_RX_USING_DMA is not set CONFIG_BSP_USING_UART4=y # CONFIG_BSP_UART4_RX_USING_DMA is not set # CONFIG_BSP_UART4_TX_USING_DMA is not set @@ -448,6 +500,8 @@ CONFIG_BSP_USING_UART4=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_HASH is not set +# CONFIG_BSP_USING_CRYP is not set # CONFIG_BSP_USING_UDID is not set # diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h index 47a5e04456..3ba077b0b5 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h @@ -34,8 +34,8 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED #define HAL_DAC_MODULE_ENABLED /*#define HAL_DCMI_MODULE_ENABLED */ /*#define HAL_DSI_MODULE_ENABLED */ @@ -43,7 +43,7 @@ /*#define HAL_DTS_MODULE_ENABLED */ /*#define HAL_ETH_MODULE_ENABLED */ /*#define HAL_FDCAN_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ +#define HAL_HASH_MODULE_ENABLED /*#define HAL_HCD_MODULE_ENABLED */ #define HAL_HSEM_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED @@ -56,7 +56,7 @@ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED /*#define HAL_MMC_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index 1c87703a03..2ddf367caa 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -26,7 +26,9 @@ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ - +DMA_HandleTypeDef hdma_hash_in = {0}; +DMA_HandleTypeDef hdma_cryp_in = {0}; +DMA_HandleTypeDef hdma_cryp_out = {0}; /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ @@ -1066,6 +1068,250 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) } } +/** +* @brief CRC MSP Initialization +* This function configures the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC2) + { + /* USER CODE BEGIN CRC2_MspInit 0 */ + + /* USER CODE END CRC2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CRC2_CLK_ENABLE(); + /* USER CODE BEGIN CRC2_MspInit 1 */ + + /* USER CODE END CRC2_MspInit 1 */ + } + +} + +/** +* @brief CRC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC2) + { + /* USER CODE BEGIN CRC2_MspDeInit 0 */ + + /* USER CODE END CRC2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC2_CLK_DISABLE(); + /* USER CODE BEGIN CRC2_MspDeInit 1 */ + + /* USER CODE END CRC2_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hrng->Instance==RNG2) + { + /* USER CODE BEGIN RNG2_MspInit 0 */ + + /* USER CODE END RNG2_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG2; + PeriphClkInit.Rng2ClockSelection = RCC_RNG2CLKSOURCE_CSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG2_CLK_ENABLE(); + /* USER CODE BEGIN RNG2_MspInit 1 */ + + /* USER CODE END RNG2_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG2) + { + /* USER CODE BEGIN RNG2_MspDeInit 0 */ + + /* USER CODE END RNG2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG2_CLK_DISABLE(); + /* USER CODE BEGIN RNG2_MspDeInit 1 */ + + /* USER CODE END RNG2_MspDeInit 1 */ + } + +} + +/** +* @brief HASH MSP Initialization +* This function configures the hardware resources used in this example +* @param hhash: HASH handle pointer +* @retval None +*/ +void HAL_HASH_MspInit(HASH_HandleTypeDef* hhash) +{ + /* USER CODE BEGIN HASH2_MspInit 0 */ + /* USER CODE END HASH2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_HASH2_CLK_ENABLE(); + /* USER CODE BEGIN HASH2_MspInit 1 */ + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_hash_in.Instance = DMA2_Stream7; + hdma_hash_in.Init.Request = DMA_REQUEST_HASH2_IN; + hdma_hash_in.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_hash_in.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_hash_in.Init.MemInc = DMA_MINC_ENABLE; + hdma_hash_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_hash_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_hash_in.Init.Mode = DMA_NORMAL; + hdma_hash_in.Init.Priority = DMA_PRIORITY_HIGH; + hdma_hash_in.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_hash_in.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL; + hdma_hash_in.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_hash_in.Init.PeriphBurst = DMA_PBURST_SINGLE; + + if (HAL_DMA_DeInit(&hdma_hash_in) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_hash_in) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hhash,hdmain,hdma_hash_in); + /* USER CODE END HASH2_MspInit 1 */ + +} + +/** +* @brief HASH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hhash: HASH handle pointer +* @retval None +*/ +void HAL_HASH_MspDeInit(HASH_HandleTypeDef* hhash) +{ + /* USER CODE BEGIN HASH2_MspDeInit 0 */ + + /* USER CODE END HASH2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_HASH2_CLK_DISABLE(); + /* USER CODE BEGIN HASH2_MspDeInit 1 */ + + /* USER CODE END HASH2_MspDeInit 1 */ + +} + +#if defined (CRYP1) || defined (CRYP2) +void HAL_CRYP_MspInit(CRYP_HandleTypeDef* hcryp) +{ + if(hcryp->Instance==CRYP2) + { + /* Peripheral clock enable */ + __HAL_RCC_CRYP2_CLK_ENABLE(); + __HAL_RCC_DMAMUX_CLK_ENABLE(); + + /* Peripheral DMA init*/ + hdma_cryp_in.Instance = DMA2_Stream6; + hdma_cryp_in.Init.Request = DMA_REQUEST_CRYP2_IN; + hdma_cryp_in.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_cryp_in.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_cryp_in.Init.MemInc = DMA_MINC_ENABLE; + hdma_cryp_in.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_cryp_in.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_cryp_in.Init.Mode = DMA_NORMAL; + hdma_cryp_in.Init.Priority = DMA_PRIORITY_HIGH; + hdma_cryp_in.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_DeInit(&hdma_cryp_in) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_cryp_in) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hcryp,hdmain,hdma_cryp_in); + + hdma_cryp_out.Instance = DMA2_Stream5; + hdma_cryp_out.Init.Request = DMA_REQUEST_CRYP2_OUT; + hdma_cryp_out.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_cryp_out.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_cryp_out.Init.MemInc = DMA_MINC_ENABLE; + hdma_cryp_out.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_cryp_out.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_cryp_out.Init.Mode = DMA_NORMAL; + hdma_cryp_out.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_cryp_out.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_DeInit(&hdma_cryp_out) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA_Init(&hdma_cryp_out) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hcryp,hdmaout,hdma_cryp_out); + + /* USER CODE BEGIN CRYP_MspInit 1 */ + + /* USER CODE END CRYP_MspInit 1 */ + } +} + +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* hcryp) +{ + + if(hcryp->Instance==CRYP2) + { + /* USER CODE BEGIN CRYP_MspDeInit 0 */ + + /* USER CODE END CRYP_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRYP2_CLK_DISABLE(); + + /* Peripheral DMA DeInit*/ + HAL_DMA_DeInit(hcryp->hdmain); + HAL_DMA_DeInit(hcryp->hdmaout); + } + /* USER CODE BEGIN CRYP_MspDeInit 1 */ + + /* USER CODE END CRYP_MspDeInit 1 */ + +} +#endif /** * @brief This function is executed in case of error occurrence. * @retval None diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/SConscript b/bsp/stm32/stm32mp157a-st-discovery/board/SConscript index 781aae3189..f1de10714b 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/SConscript +++ b/bsp/stm32/stm32mp157a-st-discovery/board/SConscript @@ -54,6 +54,9 @@ if GetDepend(['BSP_USING_AUDIO']): if GetDepend(['BSP_USING_AUDIO_RECORD']): src += Glob('ports/audio/drv_mic.c') +if GetDepend(['(BSP_USING_RNG)']) or GetDepend(['(BSP_USING_HASH)']) or GetDepend(['(BSP_USING_CRC)']) or GetDepend(['BSP_USING_CRYP']): + src += Glob('ports/crypto/crypto_sample.c') + if GetDepend(['BSP_USING_OPENAMP']): src += Glob('CubeMX_Config/CM4/Src/ipcc.c') src += Glob('CubeMX_Config/CM4/Src/openamp.c') diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c new file mode 100644 index 0000000000..e3eb609559 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-27 thread-liu first version + */ + +#include + +#include "drv_crypto.h" +#include +#include +#include + +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%02X ", buf[i + j]); + } + else + { + rt_kprintf(" "); + } + } + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + { + if (i + j < buflen) + { + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + rt_kprintf("\n"); + } +} + +#if defined(BSP_USING_RNG) +static rt_err_t hw_rng_sample(int random_num) +{ + rt_err_t result = RT_EOK; + int i = 0, num0 = 0, num1 = 0; + + if (random_num == 0) + { + return RT_ERROR; + } + + for (i = 0; i< random_num; i++) + { + result = rt_hwcrypto_rng_update(); + rt_kprintf("%d ", result); + result%2 ? num1++ : num0++; + } + rt_kprintf("\neven numbers : %d, odd numbers: %d\n",num1, num0); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_CRC) +static void hw_crc_sample(uint8_t *temp, int size) +{ + struct rt_hwcrypto_ctx *ctx; + rt_uint32_t result = 0; + + struct hwcrypto_crc_cfg cfg = + { + .last_val = 0xFFFFFFFF, + .poly = 0x04C11DB7, + .width = 32, + .xorout = 0x00000000, + .flags = 0, + }; + + ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32); + rt_hwcrypto_crc_cfg(ctx, &cfg); + + result = rt_hwcrypto_crc_update(ctx, temp, size); + + rt_kprintf("crc result: %x \n", result); + + rt_hwcrypto_crc_destroy(ctx); +} +#endif + +#if defined(BSP_USING_HASH) +static void hw_hash_sample() +{ + struct rt_hwcrypto_ctx *ctx = RT_NULL; + const uint8_t hash_input[] = "RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS)."; + + static uint8_t sha1_output[20]; + static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, + 0x02, 0x1b, 0xa8, 0xbc, 0xa2, 0x2e, 0xa5, + 0xb0, 0x62, 0x1b, 0xdf, 0x7f, 0xec}; + + static uint8_t md5_output[16]; + static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, + 0x4c, 0xd6, 0x7d, 0x28, 0xfc, 0xf6, 0xc3, + 0xac, 0x8b}; + + static uint8_t sha224_output[28]; + static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, + 0x9f, 0x82, 0x78, 0x7a, 0x46, 0x91, + 0xb0, 0xe9, 0x64, 0x89, 0xe6, 0xc3, + 0x6b, 0x7e, 0xcf, 0xca, 0x11, 0x42, + 0xc8, 0x77, 0x13, 0x79}; + static uint8_t sha256_output[32]; + static uint8_t sha256_except[32] = {0x74, 0x19, 0xb9, 0x0e, 0xd1, 0x46, + 0x37, 0x0a, 0x55, 0x18, 0x26, 0x6c, + 0x50, 0xd8, 0x71, 0x34, 0xfa, 0x1f, + 0x5f, 0x5f, 0xe4, 0x9a, 0xe9, 0x40, + 0x0a, 0x7d, 0xa0, 0x26, 0x1b, 0x86, + 0x67, 0x45}; + rt_kprintf("======================== Hash Test start ========================\n"); + rt_kprintf("Hash Test string: \n"); + dump_hex(hash_input, sizeof(hash_input)); + + /* sh1 test*/ + rt_kprintf("\n============ SHA1 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA1); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA1); + return ; + } + rt_kprintf("Create sha1 type success!\n"); + rt_kprintf("Except sha1 result:\n"); + dump_hex(sha1_except, sizeof(sha1_except)); + + /* start sha1 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha1 result */ + rt_hwcrypto_hash_finish(ctx, sha1_output, rt_strlen((char const *)sha1_output)); + + rt_kprintf("Actual sha1 result:\n"); + dump_hex(sha1_output, sizeof(sha1_output)); + + if(rt_memcmp(sha1_output, sha1_except, sizeof(sha1_except)/sizeof(sha1_except[0])) != 0) + { + rt_kprintf("Hash type sha1 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha1 Test success, The actual result is equal to the except result\n"); + } + /* deinit hash*/ + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ SHA1 Test Over ============\n"); + + /* md5 test*/ + rt_kprintf("\n============ MD5 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_MD5); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_MD5); + return ; + } + rt_kprintf("Create md5 type success!\n"); + rt_kprintf("Except md5 result:\n"); + dump_hex(md5_except, sizeof(md5_except)); + + /* start md5 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get md5 result */ + rt_hwcrypto_hash_finish(ctx, md5_output, rt_strlen((char const *)md5_output)); + + rt_kprintf("Actual md5 result:\n"); + dump_hex(md5_output, sizeof(md5_output)); + + if(rt_memcmp(md5_output, md5_except, sizeof(md5_except)/sizeof(md5_except[0])) != 0) + { + rt_kprintf("Hash type md5 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type md5 Test success, The actual result is equal to the except result\n"); + } + /* deinit hash*/ + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ MD5 Test Over ============\n"); + + /* sha224 test */ + rt_kprintf("\n============ SHA224 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA224); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA224); + return ; + } + rt_kprintf("Create sha224 type success!\n"); + rt_kprintf("Except sha224 result:\n"); + dump_hex(sha224_except, sizeof(sha224_except)); + + /* start sha224 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha224 result */ + rt_hwcrypto_hash_finish(ctx, sha224_output, rt_strlen((char const *)sha224_output)); + + rt_kprintf("Actual sha224 result:\n"); + dump_hex(sha224_output, sizeof(sha224_output)); + + if(rt_memcmp(sha224_output, sha224_except, sizeof(sha224_except)/sizeof(sha224_except[0])) != 0) + { + rt_kprintf("Hash type sha224 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha224 Test success, The actual result is equal to the except result\n"); + } + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ SHA224 Test Over ============\n"); + + /* sha256 test*/ + rt_kprintf("\n============ SHA256 Test Start ============\n"); + ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA256); + if (ctx == RT_NULL) + { + rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA256); + return ; + } + + rt_kprintf("Create sha256 type success!\n"); + rt_kprintf("Except sha256 result:\n"); + dump_hex(sha256_except, sizeof(sha256_except)); + + /* start sha256 */ + rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); + /* get sha256 result */ + rt_hwcrypto_hash_finish(ctx, sha256_output, rt_strlen((char const *)sha256_output)); + + rt_kprintf("Actual sha256 result\n"); + dump_hex(sha256_output, sizeof(sha256_output)); + + if(rt_memcmp(sha256_output, sha256_except, sizeof(sha256_except)/sizeof(sha256_except[0])) != 0) + { + rt_kprintf("Hash type sha256 Test error, The actual result is not equal to the except result\n"); + } + else + { + rt_kprintf("Hash type sha256 Test success, The actual result is equal to the except result\n"); + } + /* destory */ + rt_hwcrypto_hash_destroy(ctx); + rt_kprintf("============ SHA256 Test Over ============\n"); + rt_kprintf("======================== Hash Test over! ========================\n"); +} +#endif + +#if defined(BSP_USING_CRYP) +/* key*/ +static const rt_uint8_t cryp_key[16] = {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF}; + +static void hw_aes_cbc(const rt_uint8_t in[32], rt_uint8_t out[32], hwcrypto_mode mode) +{ + struct rt_hwcrypto_ctx *ctx; + + ctx = rt_hwcrypto_symmetric_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_AES_CBC); + if (ctx == RT_NULL) + { + rt_kprintf("create AES-CBC context err!"); + return; + } + rt_hwcrypto_symmetric_setkey(ctx, cryp_key, 128); + rt_hwcrypto_symmetric_crypt(ctx, mode, 32, in, out); + rt_hwcrypto_symmetric_destroy(ctx); +} + +static void hw_cryp_sample() +{ + rt_uint8_t buf_in[32]; + rt_uint8_t buf_out[32]; + int i; + + /* Populating test data */ + for (i = 0; i < sizeof(buf_in); i++) + { + buf_in[i] = i; + } + + /* dump primitive data */ + rt_kprintf("key : \n"); + dump_hex(cryp_key, sizeof(cryp_key)); + rt_kprintf("primitive data : \n"); + dump_hex(buf_in, sizeof(buf_in)); + + rt_memset(buf_out, 0, sizeof(buf_out)); + + /* encrypt */ + hw_aes_cbc(buf_in, buf_out, HWCRYPTO_MODE_ENCRYPT); + /* dump encrypt data */ + rt_kprintf("AES-enc : \n"); + dump_hex(buf_out, sizeof(buf_out)); + + rt_memset(buf_in, 0, sizeof(buf_in)); + + /* decrypt */ + hw_aes_cbc(buf_out, buf_in, HWCRYPTO_MODE_DECRYPT); + + /* dump decrypt data */ + rt_kprintf("AES-dec : \n"); + dump_hex(buf_in, sizeof(buf_in)); +} +#endif + +static int crypto(int argc, char **argv) +{ + int result = RT_EOK; + static rt_device_t device = RT_NULL; + char *result_str; + + if (argc > 1) + { + if (!strcmp(argv[1], "probe")) + { + if (argc == 3) + { + char *dev_name = argv[2]; + device = rt_device_find(dev_name); + result_str = (device == RT_NULL) ? "failure" : "success"; + rt_kprintf("probe %s %s \n", argv[2], result_str); + } + else + { + rt_kprintf("crypto probe - probe crypto by name\n"); + } + } + else + { + if (device == RT_NULL) + { + rt_kprintf("Please using 'crypto probe ' first\n"); + return -RT_ERROR; + } + if (!strcmp(argv[1], "rng")) + { +#if defined (BSP_USING_RNG) + if (argc == 3) + { + result = hw_rng_sample(atoi(argv[2])); + if(result != RT_EOK) + { + rt_kprintf("please input a legal number, not <%d>\n", atoi(argv[2])); + } + } + else + { + rt_kprintf("rng - generate digital\n"); + } + +#else + rt_kprintf("please enable RNG first!\n"); +#endif + } + else if (!strcmp(argv[1], "crc")) + { +#if defined (BSP_USING_CRC) + int size = 0, i = 0; + if (argc > 3) + { + size = argc - 2; + uint8_t *data = rt_malloc(size); + if (data) + { + for (i = 0; i < size; i++) + { + data[i] = strtol(argv[2 + i], NULL, 0); + } + hw_crc_sample(data, size); + rt_free(data); + } + else + { + rt_kprintf("Low memory!\n"); + } + } + else + { + rt_kprintf("crypto crc data1 ... dataN - calculate data1 ... dataN crc\n"); + } +#else + rt_kprintf("please enable CRC first!\n"); +#endif + } + else if (!strcmp(argv[1], "hash")) + { +#if defined (BSP_USING_HASH) + if (argc == 3) + { + hw_hash_sample(); + } + else + { + rt_kprintf("crypto hash sample - hash use sample\n"); + } +#else + rt_kprintf("please enable CRC first!\n"); +#endif + } + else if (!strcmp(argv[1], "cryp")) + { +#if defined (BSP_USING_CRYP) + if (argc == 3) + { + hw_cryp_sample(); + } + else + { + rt_kprintf("crypto cryp sample - encrypt and decrypt data sample\n"); + } +#else + rt_kprintf("please enable CRYP first!\n"); +#endif + } + else + { + rt_kprintf("Unknown command. Please enter 'crypto' for help\n"); + } + } + } + else + { + rt_kprintf("Usage: \n"); + rt_kprintf("crypto probe - probe crypto by name\n"); + rt_kprintf("crypto rng number - generate numbers digital\n"); + rt_kprintf("crypto crc data1 ... dataN - calculate data1 ... dataN crc\n"); + rt_kprintf("crypto hash sample - hash use sample\n"); + rt_kprintf("crypto cryp sample - encrypt and decrypt data\n"); + result = -RT_ERROR; + } + + return result; +} +MSH_CMD_EXPORT(crypto, crypto function);