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[stm32/gpio]Optimized the pin-index algorithm

This commit is contained in:
xieyangrun 2020-09-18 18:33:13 +08:00
parent 8afb8b1e29
commit 7305712ef2
2 changed files with 206 additions and 412 deletions
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409
bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
View File

@ -9,6 +9,7 @@
* 2019-04-23 WillianChan Fix GPIO serial number disorder
* 2020-06-16 thread-liu add STM32MP1
* 2020-09-01 thread-liu add GPIOZ
* 2020-09-18 geniusgogo optimization design pin-index algorithm
*/
#include <board.h>
@ -16,225 +17,43 @@
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
{
#if defined(GPIOA)
__STM32_PIN(0 , A, 0 ),
__STM32_PIN(1 , A, 1 ),
__STM32_PIN(2 , A, 2 ),
__STM32_PIN(3 , A, 3 ),
__STM32_PIN(4 , A, 4 ),
__STM32_PIN(5 , A, 5 ),
__STM32_PIN(6 , A, 6 ),
__STM32_PIN(7 , A, 7 ),
__STM32_PIN(8 , A, 8 ),
__STM32_PIN(9 , A, 9 ),
__STM32_PIN(10, A, 10),
__STM32_PIN(11, A, 11),
__STM32_PIN(12, A, 12),
__STM32_PIN(13, A, 13),
__STM32_PIN(14, A, 14),
__STM32_PIN(15, A, 15),
#if defined(GPIOB)
__STM32_PIN(16, B, 0),
__STM32_PIN(17, B, 1),
__STM32_PIN(18, B, 2),
__STM32_PIN(19, B, 3),
__STM32_PIN(20, B, 4),
__STM32_PIN(21, B, 5),
__STM32_PIN(22, B, 6),
__STM32_PIN(23, B, 7),
__STM32_PIN(24, B, 8),
__STM32_PIN(25, B, 9),
__STM32_PIN(26, B, 10),
__STM32_PIN(27, B, 11),
__STM32_PIN(28, B, 12),
__STM32_PIN(29, B, 13),
__STM32_PIN(30, B, 14),
__STM32_PIN(31, B, 15),
#if defined(GPIOC)
__STM32_PIN(32, C, 0),
__STM32_PIN(33, C, 1),
__STM32_PIN(34, C, 2),
__STM32_PIN(35, C, 3),
__STM32_PIN(36, C, 4),
__STM32_PIN(37, C, 5),
__STM32_PIN(38, C, 6),
__STM32_PIN(39, C, 7),
__STM32_PIN(40, C, 8),
__STM32_PIN(41, C, 9),
__STM32_PIN(42, C, 10),
__STM32_PIN(43, C, 11),
__STM32_PIN(44, C, 12),
__STM32_PIN(45, C, 13),
__STM32_PIN(46, C, 14),
__STM32_PIN(47, C, 15),
#if defined(GPIOD)
__STM32_PIN(48, D, 0),
__STM32_PIN(49, D, 1),
__STM32_PIN(50, D, 2),
__STM32_PIN(51, D, 3),
__STM32_PIN(52, D, 4),
__STM32_PIN(53, D, 5),
__STM32_PIN(54, D, 6),
__STM32_PIN(55, D, 7),
__STM32_PIN(56, D, 8),
__STM32_PIN(57, D, 9),
__STM32_PIN(58, D, 10),
__STM32_PIN(59, D, 11),
__STM32_PIN(60, D, 12),
__STM32_PIN(61, D, 13),
__STM32_PIN(62, D, 14),
__STM32_PIN(63, D, 15),
#if defined(GPIOE)
__STM32_PIN(64, E, 0),
__STM32_PIN(65, E, 1),
__STM32_PIN(66, E, 2),
__STM32_PIN(67, E, 3),
__STM32_PIN(68, E, 4),
__STM32_PIN(69, E, 5),
__STM32_PIN(70, E, 6),
__STM32_PIN(71, E, 7),
__STM32_PIN(72, E, 8),
__STM32_PIN(73, E, 9),
__STM32_PIN(74, E, 10),
__STM32_PIN(75, E, 11),
__STM32_PIN(76, E, 12),
__STM32_PIN(77, E, 13),
__STM32_PIN(78, E, 14),
__STM32_PIN(79, E, 15),
#if defined(GPIOF)
__STM32_PIN(80, F, 0),
__STM32_PIN(81, F, 1),
__STM32_PIN(82, F, 2),
__STM32_PIN(83, F, 3),
__STM32_PIN(84, F, 4),
__STM32_PIN(85, F, 5),
__STM32_PIN(86, F, 6),
__STM32_PIN(87, F, 7),
__STM32_PIN(88, F, 8),
__STM32_PIN(89, F, 9),
__STM32_PIN(90, F, 10),
__STM32_PIN(91, F, 11),
__STM32_PIN(92, F, 12),
__STM32_PIN(93, F, 13),
__STM32_PIN(94, F, 14),
__STM32_PIN(95, F, 15),
#if defined(GPIOG)
__STM32_PIN(96, G, 0),
__STM32_PIN(97, G, 1),
__STM32_PIN(98, G, 2),
__STM32_PIN(99, G, 3),
__STM32_PIN(100, G, 4),
__STM32_PIN(101, G, 5),
__STM32_PIN(102, G, 6),
__STM32_PIN(103, G, 7),
__STM32_PIN(104, G, 8),
__STM32_PIN(105, G, 9),
__STM32_PIN(106, G, 10),
__STM32_PIN(107, G, 11),
__STM32_PIN(108, G, 12),
__STM32_PIN(109, G, 13),
__STM32_PIN(110, G, 14),
__STM32_PIN(111, G, 15),
#if defined(GPIOH)
__STM32_PIN(112, H, 0),
__STM32_PIN(113, H, 1),
__STM32_PIN(114, H, 2),
__STM32_PIN(115, H, 3),
__STM32_PIN(116, H, 4),
__STM32_PIN(117, H, 5),
__STM32_PIN(118, H, 6),
__STM32_PIN(119, H, 7),
__STM32_PIN(120, H, 8),
__STM32_PIN(121, H, 9),
__STM32_PIN(122, H, 10),
__STM32_PIN(123, H, 11),
__STM32_PIN(124, H, 12),
__STM32_PIN(125, H, 13),
__STM32_PIN(126, H, 14),
__STM32_PIN(127, H, 15),
#if defined(GPIOI)
__STM32_PIN(128, I, 0),
__STM32_PIN(129, I, 1),
__STM32_PIN(130, I, 2),
__STM32_PIN(131, I, 3),
__STM32_PIN(132, I, 4),
__STM32_PIN(133, I, 5),
__STM32_PIN(134, I, 6),
__STM32_PIN(135, I, 7),
__STM32_PIN(136, I, 8),
__STM32_PIN(137, I, 9),
__STM32_PIN(138, I, 10),
__STM32_PIN(139, I, 11),
__STM32_PIN(140, I, 12),
__STM32_PIN(141, I, 13),
__STM32_PIN(142, I, 14),
__STM32_PIN(143, I, 15),
#if defined(GPIOJ)
__STM32_PIN(144, J, 0),
__STM32_PIN(145, J, 1),
__STM32_PIN(146, J, 2),
__STM32_PIN(147, J, 3),
__STM32_PIN(148, J, 4),
__STM32_PIN(149, J, 5),
__STM32_PIN(150, J, 6),
__STM32_PIN(151, J, 7),
__STM32_PIN(152, J, 8),
__STM32_PIN(153, J, 9),
__STM32_PIN(154, J, 10),
__STM32_PIN(155, J, 11),
__STM32_PIN(156, J, 12),
__STM32_PIN(157, J, 13),
__STM32_PIN(158, J, 14),
__STM32_PIN(159, J, 15),
#if defined(GPIOK)
__STM32_PIN(160, K, 0),
__STM32_PIN(161, K, 1),
__STM32_PIN(162, K, 2),
__STM32_PIN(163, K, 3),
__STM32_PIN(164, K, 4),
__STM32_PIN(165, K, 5),
__STM32_PIN(166, K, 6),
__STM32_PIN(167, K, 7),
__STM32_PIN(168, K, 8),
__STM32_PIN(169, K, 9),
__STM32_PIN(170, K, 10),
__STM32_PIN(171, K, 11),
__STM32_PIN(172, K, 12),
__STM32_PIN(173, K, 13),
__STM32_PIN(174, K, 14),
__STM32_PIN(175, K, 15),
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
#if defined(GPIOZ)
__STM32_PIN(176, Z, 0),
__STM32_PIN(177, Z, 1),
__STM32_PIN(178, Z, 2),
__STM32_PIN(179, Z, 3),
__STM32_PIN(180, Z, 4),
__STM32_PIN(181, Z, 5),
__STM32_PIN(182, Z, 6),
__STM32_PIN(183, Z, 7),
__STM32_PIN(184, Z, 8),
__STM32_PIN(185, Z, 9),
__STM32_PIN(186, Z, 10),
__STM32_PIN(187, Z, 11),
__STM32_PIN(188, Z, 12),
__STM32_PIN(189, Z, 13),
__STM32_PIN(190, Z, 14),
__STM32_PIN(191, Z, 15),
#endif /* defined(GPIOZ) */
#endif /* defined(GPIOK) */
#endif /* defined(GPIOJ) */
#endif /* defined(GPIOI) */
#endif /* defined(GPIOH) */
#endif /* defined(GPIOG) */
#endif /* defined(GPIOF) */
#endif /* defined(GPIOE) */
#endif /* defined(GPIOD) */
#endif /* defined(GPIOC) */
#endif /* defined(GPIOB) */
#endif /* defined(GPIOA) */
};
#define __STM32_PORT_MAX 12u
#elif defined(GPIOK)
#define __STM32_PORT_MAX 11u
#elif defined(GPIOJ)
#define __STM32_PORT_MAX 10u
#elif defined(GPIOI)
#define __STM32_PORT_MAX 9u
#elif defined(GPIOH)
#define __STM32_PORT_MAX 8u
#elif defined(GPIOG)
#define __STM32_PORT_MAX 7u
#elif defined(GPIOF)
#define __STM32_PORT_MAX 6u
#elif defined(GPIOE)
#define __STM32_PORT_MAX 5u
#elif defined(GPIOD)
#define __STM32_PORT_MAX 4u
#elif defined(GPIOC)
#define __STM32_PORT_MAX 3u
#elif defined(GPIOB)
#define __STM32_PORT_MAX 2u
#elif defined(GPIOA)
#define __STM32_PORT_MAX 1u
#else
#define __STM32_PORT_MAX 0u
#error Unsupported STM32 GPIO peripheral.
#endif
#define PIN_STPORT_MAX __STM32_PORT_MAX
static const struct pin_irq_map pin_irq_map[] =
{
@ -314,30 +133,12 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
static uint32_t pin_irq_enable_mask = 0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
static rt_base_t stm32_pin_get(const char *name)
{
rt_base_t pin = 0;
int hw_port_num, hw_pin_num = 0;
int i, name_len = 1;
int mul = 1;
int i, name_len;
name_len = rt_strlen(name);
@ -359,68 +160,58 @@ static rt_base_t stm32_pin_get(const char *name)
return -RT_EINVAL;
}
for (i = name_len - 1; i > 2; i--)
for (i = 3; i < name_len; i++)
{
hw_pin_num += ((int)(name[i] - '0') * mul);
mul = mul * 10;
hw_pin_num *= 10;
hw_pin_num += name[i] - '0';
}
pin = 16 * hw_port_num + hw_pin_num;
pin = PIN_NUM(hw_port_num, hw_pin_num);
if (pin < ITEM_NUM(pins))
{
return pin;
}
else
{
return -RT_EINVAL;
}
}
static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
return;
}
gpio_port = PIN_STPORT(pin);
gpio_pin = PIN_STPIN(pin);
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
HAL_GPIO_WritePin(gpio_port, gpio_pin, (GPIO_PinState)value);
}
}
static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
int value = PIN_LOW;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
return value;
gpio_port = PIN_STPORT(pin);
gpio_pin = PIN_STPIN(pin);
value = HAL_GPIO_ReadPin(gpio_port, gpio_pin);
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
return value;
}
static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return;
}
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pin = PIN_STPIN(pin);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@ -456,7 +247,7 @@ static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
@ -485,16 +276,15 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return RT_ENOSYS;
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
@ -525,16 +315,15 @@ static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return RT_ENOSYS;
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
@ -558,21 +347,19 @@ static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return RT_ENOSYS;
return -RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
@ -589,7 +376,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
irqmap = &pin_irq_map[irqindex];
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pin = PIN_STPIN(pin);
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
switch (pin_irq_hdr_tab[irqindex].mode)
{
@ -606,7 +393,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
break;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
HAL_NVIC_EnableIRQ(irqmap->irqno);
@ -616,7 +403,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
irqmap = get_pin_irq_map(PIN_STPIN(pin));
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
@ -624,7 +411,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
level = rt_hw_interrupt_disable();
HAL_GPIO_DeInit(index->gpio, index->pin);
HAL_GPIO_DeInit(PIN_STPORT(pin), PIN_STPIN(pin));
pin_irq_enable_mask &= ~irqmap->pinbit;
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
@ -754,97 +541,113 @@ void EXTI4_15_IRQHandler(void)
}
#elif defined(SOC_STM32MP157A)
void EXTI0_IRQHandler(void) {
void EXTI0_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void) {
void EXTI1_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void) {
void EXTI2_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void) {
void EXTI3_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void) {
void EXTI4_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
rt_interrupt_leave();
}
void EXTI5_IRQHandler(void) {
void EXTI5_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
rt_interrupt_leave();
}
void EXTI6_IRQHandler(void) {
void EXTI6_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
rt_interrupt_leave();
}
void EXTI7_IRQHandler(void) {
void EXTI7_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
rt_interrupt_leave();
}
void EXTI8_IRQHandler(void) {
void EXTI8_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
rt_interrupt_leave();
}
void EXTI9_IRQHandler(void) {
void EXTI9_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
rt_interrupt_leave();
}
void EXTI10_IRQHandler(void) {
void EXTI10_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
rt_interrupt_leave();
}
void EXTI11_IRQHandler(void) {
void EXTI11_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
rt_interrupt_leave();
}
void EXTI12_IRQHandler(void) {
void EXTI12_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
rt_interrupt_leave();
}
void EXTI13_IRQHandler(void) {
void EXTI13_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
rt_interrupt_leave();
}
void EXTI14_IRQHandler(void) {
void EXTI14_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
rt_interrupt_leave();
}
void EXTI15_IRQHandler(void) {
void EXTI15_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
rt_interrupt_leave();

27
bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
View File

@ -8,6 +8,7 @@
* 2018-11-06 balanceTWK first version
* 2020-06-16 thread-liu add stm32mp1
* 2020-09-01 thread-liu add GPIOZ
* 2020-09-18 geniusgogo optimization design pin-index algorithm
*/
#ifndef __DRV_GPIO_H__
@ -16,6 +17,10 @@
#include <drv_common.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __STM32_PORT(port) GPIO##port##_BASE
#if defined(SOC_SERIES_STM32MP1)
@ -24,24 +29,6 @@
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
#endif
#define __STM32_PIN(index, gpio, gpio_index) \
{ \
index, GPIO##gpio, GPIO_PIN_##gpio_index \
}
#define __STM32_PIN_RESERVE \
{ \
-1, 0, 0 \
}
/* STM32 GPIO driver */
struct pin_index
{
int index;
GPIO_TypeDef *gpio;
uint32_t pin;
};
struct pin_irq_map
{
rt_uint16_t pinbit;
@ -50,5 +37,9 @@ struct pin_irq_map
int rt_hw_pin_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */