增加龙芯1c硬浮点的支持（可以使用硬浮点了）
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fa127c6531
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7129d77bee
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@ -51,6 +51,31 @@ void rt_hw_timer_init(void)
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write_c0_count(0);
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write_c0_count(0);
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}
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}
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/**
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* init hardware FPU
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*/
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void rt_hw_fpu_init(void)
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{
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rt_uint32_t c0_status = 0;
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rt_uint32_t c1_status = 0;
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// ʹÄÜд¦ÀíÆ÷1--FPU
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c0_status = read_c0_status();
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c0_status |= (ST0_CU1 | ST0_FR);
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write_c0_status(c0_status);
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// ÅäÖÃFPU
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c1_status = read_c1_status();
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c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); // set FS, FO, FN
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c1_status &= ~(FPU_CSR_ALL_E); // disable exception
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c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; // set RN
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write_c1_status(c1_status);
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return ;
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}
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/**
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/**
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* This function will initial sam7s64 board.
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* This function will initial sam7s64 board.
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*/
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*/
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@ -69,6 +94,9 @@ void rt_hw_board_init(void)
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/* init operating system timer */
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/* init operating system timer */
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rt_hw_timer_init();
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rt_hw_timer_init();
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/* init hardware fpu */
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rt_hw_fpu_init();
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rt_kprintf("current sr: 0x%08x\n", read_c0_status());
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rt_kprintf("current sr: 0x%08x\n", read_c0_status());
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}
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}
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@ -116,6 +116,70 @@
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#define CP1_REVISION $0
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#define CP1_REVISION $0
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#define CP1_STATUS $31
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#define CP1_STATUS $31
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/*
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* FPU Status Register Values
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*/
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/*
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* Status Register Values
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*/
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#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
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#define FPU_CSR_COND 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
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#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
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#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
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#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
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#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
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#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
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#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
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/* FS/FO/FN */
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#define FPU_CSR_FS 0x01000000
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#define FPU_CSR_FO 0x00400000
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#define FPU_CSR_FN 0x00200000
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/*
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* Bits 18 - 20 of the FPU Status Register will be read as 0,
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* and should be written as zero.
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*/
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#define FPU_CSR_RSVD 0x001c0000
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/*
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* X the exception cause indicator
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* E the exception enable
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* S the sticky/flag bit
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*/
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#define FPU_CSR_ALL_X 0x0003f000
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#define FPU_CSR_UNI_X 0x00020000
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#define FPU_CSR_INV_X 0x00010000
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#define FPU_CSR_DIV_X 0x00008000
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#define FPU_CSR_OVF_X 0x00004000
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#define FPU_CSR_UDF_X 0x00002000
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#define FPU_CSR_INE_X 0x00001000
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#define FPU_CSR_ALL_E 0x00000f80
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#define FPU_CSR_INV_E 0x00000800
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#define FPU_CSR_DIV_E 0x00000400
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#define FPU_CSR_OVF_E 0x00000200
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#define FPU_CSR_UDF_E 0x00000100
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#define FPU_CSR_INE_E 0x00000080
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#define FPU_CSR_ALL_S 0x0000007c
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#define FPU_CSR_INV_S 0x00000040
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#define FPU_CSR_DIV_S 0x00000020
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#define FPU_CSR_OVF_S 0x00000010
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#define FPU_CSR_UDF_S 0x00000008
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#define FPU_CSR_INE_S 0x00000004
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/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
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#define FPU_CSR_RM 0x00000003
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#define FPU_CSR_RN 0x0 /* nearest */
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#define FPU_CSR_RZ 0x1 /* towards zero */
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#define FPU_CSR_RU 0x2 /* towards +Infinity */
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#define FPU_CSR_RD 0x3 /* towards -Infinity */
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/*
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/*
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* R4x00 interrupt enable / cause bits
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* R4x00 interrupt enable / cause bits
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@ -610,6 +674,32 @@ do { \
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#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
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#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
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/*
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* Macros to access the floating point coprocessor control registers
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*/
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#define read_32bit_cp1_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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/* gas fails to assemble cfc1 for some archs (octeon).*/ \
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".set\tmips1\n\t" \
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"cfc1\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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#define write_32bit_cp1_register(register, value) \
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do { \
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__asm__ __volatile__( \
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"ctc1\t%z0, "STR(register)"\n\t" \
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: : "Jr" ((unsigned int)(value))); \
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} while (0)
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#define read_c1_status() read_32bit_cp1_register(CP1_STATUS)
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#define read_c1_revision() read_32bit_cp1_register(CP1_REVISION);
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#define write_c1_status(val) write_32bit_cp1_register(CP1_STATUS, val)
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#endif /* end of __ASSEMBLY__ */
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#endif /* end of __ASSEMBLY__ */
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#endif /* end of __MIPSREGS_H__ */
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#endif /* end of __MIPSREGS_H__ */
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@ -16,6 +16,7 @@
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#include "../common/mips.inc"
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#include "../common/mips.inc"
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#include "../common/stackframe.h"
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#include "../common/stackframe.h"
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#include "stackframe_fpu.h"
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.section ".text", "ax"
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.section ".text", "ax"
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.set noreorder
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.set noreorder
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@ -56,10 +57,12 @@ rt_hw_interrupt_enable:
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rt_hw_context_switch:
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rt_hw_context_switch:
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mtc0 ra, CP0_EPC
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mtc0 ra, CP0_EPC
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SAVE_ALL
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SAVE_ALL
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SAVE_FPU
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sw sp, 0(a0) /* store sp in preempted tasks TCB */
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sw sp, 0(a0) /* store sp in preempted tasks TCB */
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lw sp, 0(a1) /* get new task stack pointer */
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lw sp, 0(a1) /* get new task stack pointer */
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RESTORE_FPU
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RESTORE_ALL_AND_RET
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RESTORE_ALL_AND_RET
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/*
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/*
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@ -70,6 +73,7 @@ rt_hw_context_switch:
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rt_hw_context_switch_to:
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rt_hw_context_switch_to:
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lw sp, 0(a0) /* get new task stack pointer */
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lw sp, 0(a0) /* get new task stack pointer */
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RESTORE_FPU
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RESTORE_ALL_AND_RET
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RESTORE_ALL_AND_RET
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/*
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/*
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@ -103,6 +107,7 @@ _reswitch:
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.globl mips_irq_handle
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.globl mips_irq_handle
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mips_irq_handle:
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mips_irq_handle:
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SAVE_ALL
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SAVE_ALL
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SAVE_FPU
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mfc0 t0, CP0_CAUSE
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mfc0 t0, CP0_CAUSE
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and t1, t0, 0xff
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and t1, t0, 0xff
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@ -151,6 +156,7 @@ mips_irq_handle:
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nop
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nop
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spurious_interrupt:
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spurious_interrupt:
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RESTORE_FPU
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RESTORE_ALL_AND_RET
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RESTORE_ALL_AND_RET
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.set reorder
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.set reorder
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@ -0,0 +1,94 @@
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/*
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* ls1c FPU's stackframe
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* 最开始本想，将代码加入到stackframe.h中的SAVE_ALL, RESTORE_ALL和RESTORE_ALL_AND_RET中，
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* 但考虑到源文件"stackframe.h"位于目录"libcpu\mips\common"内，怕影响到其它mips cpu
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* 所以，另外新建本源文件
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*/
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#ifndef __OPENLOONGSON_STACKFRAME_FPU_H
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#define __OPENLOONGSON_STACKFRAME_FPU_H
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#include "../common/asm.h"
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#include "../common/mipsregs.h"
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#include "../common/stackframe.h"
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#define PT_FPU_R0 (0)
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#define PT_FPU_R2 ((PT_FPU_R0) + 2*LONGSIZE)
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#define PT_FPU_R4 ((PT_FPU_R2) + 2*LONGSIZE)
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#define PT_FPU_R6 ((PT_FPU_R4) + 2*LONGSIZE)
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#define PT_FPU_R8 ((PT_FPU_R6) + 2*LONGSIZE)
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#define PT_FPU_R10 ((PT_FPU_R8) + 2*LONGSIZE)
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#define PT_FPU_R12 ((PT_FPU_R10) + 2*LONGSIZE)
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#define PT_FPU_R14 ((PT_FPU_R12) + 2*LONGSIZE)
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#define PT_FPU_R16 ((PT_FPU_R14) + 2*LONGSIZE)
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#define PT_FPU_R18 ((PT_FPU_R16) + 2*LONGSIZE)
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#define PT_FPU_R20 ((PT_FPU_R18) + 2*LONGSIZE)
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#define PT_FPU_R22 ((PT_FPU_R20) + 2*LONGSIZE)
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#define PT_FPU_R24 ((PT_FPU_R22) + 2*LONGSIZE)
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#define PT_FPU_R26 ((PT_FPU_R24) + 2*LONGSIZE)
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#define PT_FPU_R28 ((PT_FPU_R26) + 2*LONGSIZE)
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#define PT_FPU_R30 ((PT_FPU_R28) + 2*LONGSIZE)
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#define PT_FPU_SIZE ((((PT_FPU_R30) + 2*LONGSIZE) + (2*PTRSIZE-1)) & ~(2*PTRSIZE-1))
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.macro SAVE_FPU
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.set push
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.set noreorder
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move k1, sp /* 保存现场 */
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and k0, k1, 0xFFFFFFF8 /* 8字节对齐 */
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PTR_SUBU sp, k0, PT_FPU_SIZE /* 计算栈底 */
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s.d $f0, PT_FPU_R0(sp)
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s.d $f2, PT_FPU_R2(sp)
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s.d $f4, PT_FPU_R4(sp)
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s.d $f6, PT_FPU_R6(sp)
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s.d $f8, PT_FPU_R8(sp)
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s.d $f10, PT_FPU_R10(sp)
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s.d $f12, PT_FPU_R12(sp)
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s.d $f14, PT_FPU_R14(sp)
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s.d $f16, PT_FPU_R16(sp)
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s.d $f18, PT_FPU_R18(sp)
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s.d $f20, PT_FPU_R20(sp)
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s.d $f22, PT_FPU_R22(sp)
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s.d $f24, PT_FPU_R24(sp)
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s.d $f26, PT_FPU_R26(sp)
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s.d $f28, PT_FPU_R28(sp)
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s.d $f30, PT_FPU_R30(sp)
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move sp, k1 /* 恢复现场 */
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.set reorder
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.set pop
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.endm
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.macro RESTORE_FPU
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.set push
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.set noreorder
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move k1, sp /* 保存现场 */
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and k0, k1, 0xFFFFFFF8 /* 8字节对齐 */
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PTR_SUBU sp, k0, PT_FPU_SIZE /* 计算栈底*/
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l.d $f0, PT_FPU_R0(sp)
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l.d $f2, PT_FPU_R2(sp)
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l.d $f4, PT_FPU_R4(sp)
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l.d $f6, PT_FPU_R6(sp)
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l.d $f8, PT_FPU_R8(sp)
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l.d $f10, PT_FPU_R10(sp)
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l.d $f12, PT_FPU_R12(sp)
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l.d $f14, PT_FPU_R14(sp)
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l.d $f16, PT_FPU_R16(sp)
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l.d $f18, PT_FPU_R18(sp)
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l.d $f20, PT_FPU_R20(sp)
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l.d $f22, PT_FPU_R22(sp)
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l.d $f24, PT_FPU_R24(sp)
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l.d $f26, PT_FPU_R26(sp)
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l.d $f28, PT_FPU_R28(sp)
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l.d $f30, PT_FPU_R30(sp)
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move sp, k1 /* 恢复现场 */
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.set reorder
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.set pop
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.endm
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#endif
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