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[bsp] add new driver & iar support.

This commit is contained in:
wangyq2018 2020-02-26 13:38:07 +08:00
parent 0908df39e7
commit 6bd76cc554
28 changed files with 11002 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
bsp/essemi/es32f369x/.config
View File

@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -114,12 +114,10 @@ CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_USING_CAN=y
# CONFIG_RT_CAN_USING_HDR is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_USING_I2C_BITOPS is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
@ -194,11 +192,15 @@ CONFIG_RT_USING_PIN=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@ -225,6 +227,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@ -237,9 +240,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@ -256,6 +260,11 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
#
# security packages
@ -263,6 +272,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@ -297,6 +308,9 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
#
# system packages
@ -307,6 +321,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@ -317,6 +332,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
#
# peripheral libraries and drivers
@ -333,6 +354,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@ -350,6 +375,21 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
#
# miscellaneous packages
@ -386,6 +426,9 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
CONFIG_SOC_ES32F3696LT=y
#
@ -425,6 +468,28 @@ CONFIG_BSP_USING_UART0=y
#
# CONFIG_BSP_USING_CAN is not set
#
# ADC Drivers
#
# CONFIG_BSP_USING_ADC is not set
#
# RTC Drivers
#
# CONFIG_BSP_USING_RTC is not set
#
# HWtimer Drivers
#
# CONFIG_BSP_USING_HWTIMER0 is not set
# CONFIG_BSP_USING_HWTIMER1 is not set
#
# PWM Drivers
#
# CONFIG_BSP_USING_PWM0 is not set
# CONFIG_BSP_USING_PWM1 is not set
#
# Onboard Peripheral Drivers
#

28
bsp/essemi/es32f369x/README.md
View File

@ -13,9 +13,9 @@ ES-PDS-ES32F369x 是东软载波微电子官方推出的一款基于 ARM Cortex-
开发板外观如下图所示：
ES-PDS-ES32F369x-V1.2
ES-PDS-ES32F369x-V1.3
![ES32F0654](figures/ES-PDS-ES32F369x-V1.2.jpg)
![ES32F0654](figures/ES-PDS-ES32F369x-V1.3.jpg)
该开发板常用 **板载资源** 如下：
@ -32,15 +32,19 @@ ES-PDS-ES32F369x-V1.2
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :--------------- |
| SPI FLASH | 支持 | SPI0 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | 50 GPIOs |
| UART | 支持 | UART0/1/2/3/4/5 |
| SPI | 支持 | SPI0/1/2 |
| I2C | 支持 | I2C0/1 |
| CAN | 支持 | CAN0 |
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :-------------- |
| SPI FLASH | 支持 | SPI0 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | 50 GPIOs |
| UART | 支持 | UART0/1/2/3/4/5 |
| SPI | 支持 | SPI0/1/2 |
| I2C | 支持 | I2C0/1 |
| CAN | 支持 | CAN0 |
| PWM | 支持 | PWM0/1 |
| TIMER | 支持 | TIMER0/1 |
| RTC | 支持 | RTC |
| ADC | 支持 | ADC0 |
### 1.2 注意事项
@ -56,7 +60,7 @@ ES-PDS-ES32F369x-V1.2
使用ESlinkⅡ(mini)连接开发板如下图所示：
ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.2
ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.3
![ESLinkII](figures/ESLinkII-mini.jpg)

53
bsp/essemi/es32f369x/drivers/Kconfig
View File

@ -21,25 +21,25 @@ menu "Hardware Drivers Config"
bool "Enable UART2 PC12/PD02(T/R)"
select RT_USING_SERIAL
default y
depends on !BSP_USING_HWTIMER1
config BSP_USING_UART3
bool "Enable UART3 PC04/PC05(T/R)"
select RT_USING_SERIAL
default n
depends on !BSP_USING_HWTIMER2
depends on !BSP_USING_SPI2
config BSP_USING_UART4
bool "Enable UART4 PB06/PB07(T/R)"
select RT_USING_SERIAL
default n
depends on !BSP_USING_I2C0
depends on !BSP_USING_PWM0
config BSP_USING_UART5
bool "Enable UART5 PB09/PB08(T/R)"
select RT_USING_SERIAL
default n
depends on !BSP_USING_PWM0
endmenu
menu "SPI Drivers"
@ -60,16 +60,18 @@ menu "Hardware Drivers Config"
select RT_USING_SPI
select RT_USING_PIN
default n
depends on !BSP_USING_UART3
endmenu
menu "I2C Drivers"
config BSP_USING_I2C0
bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)"
bool "Enable I2C0 BUS PB06/PB07(SCL/SDA)"
select RT_USING_I2C
default n
depends on !BSP_USING_PWM0
config BSP_USING_I2C1
bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)"
bool "Enable I2C1 BUS PA05/PA06(SCL/SDA)"
select RT_USING_I2C
default n
endmenu
@ -80,6 +82,47 @@ menu "Hardware Drivers Config"
select RT_USING_CAN
default n
endmenu
menu "ADC Drivers"
config BSP_USING_ADC
bool "Using ADC"
select RT_USING_ADC
default n
endmenu
menu "RTC Drivers"
config BSP_USING_RTC
bool "Using RTC"
select RT_USING_RTC
default n
endmenu
menu "HWtimer Drivers"
config BSP_USING_HWTIMER0
bool "Using timer0"
select RT_USING_HWTIMER
default n
config BSP_USING_HWTIMER1
bool "Using timer1"
select RT_USING_HWTIMER
default n
endmenu
menu "PWM Drivers"
config BSP_USING_PWM0
bool "Using PWM0 PB06/PB07/PB08/PB09"
select RT_USING_PWM
default n
depends on !BSP_USING_CAN
depends on !BSP_USING_I2C0
config BSP_USING_PWM1
bool "Using PWM1 PA00/PA01/PA02/PA03"
select RT_USING_PWM
default n
endmenu
endmenu
menu "Onboard Peripheral Drivers"

16
bsp/essemi/es32f369x/drivers/SConscript
View File

@ -28,6 +28,22 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
if GetDepend('BSP_USING_CAN'):
src += ['drv_can.c']
# add adc driver code
if GetDepend(['BSP_USING_ADC']):
src += ['drv_adc.c']
# add rtc driver code
if GetDepend(['BSP_USING_RTC']):
src += ['drv_rtc.c']
# add hwtimer driver code
if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1'):
src += ['drv_hwtimer.c']
# add pwm driver code
if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1'):
src += ['drv_pwm.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)

2
bsp/essemi/es32f369x/drivers/board.h
View File

@ -14,7 +14,7 @@
#include <es32f36xx.h>
#define ES32F3_SRAM_SIZE 0x80000
#define ES32F3_SRAM_SIZE 0x18000
#define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE)
#if defined(__CC_ARM) || defined(__CLANG_ARM)

194
bsp/essemi/es32f369x/drivers/drv_adc.c Normal file
View File

@ -0,0 +1,194 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-03 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_adc.h"
#include <ald_gpio.h>
#include <ald_adc.h>
#ifdef RT_USING_ADC
/* define adc instance */
static struct rt_adc_device _device_adc0;
/* enable or disable adc */
static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
RT_ASSERT(device != RT_NULL);
if (enabled)
{
ADC_ENABLE(_hadc); ;
}
else
{
ADC_DISABLE(_hadc);
}
return RT_EOK;
}
static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel)
{
adc_channel_t es32f3_channel;
gpio_init_t gpio_initstruct;
/* Initialize ADC pin */
gpio_initstruct.mode = GPIO_MODE_INPUT;
gpio_initstruct.pupd = GPIO_FLOATING;
gpio_initstruct.podrv = GPIO_OUT_DRIVE_1;
gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1;
gpio_initstruct.flt = GPIO_FILTER_DISABLE;
gpio_initstruct.type = GPIO_TYPE_CMOS;
gpio_initstruct.func = GPIO_FUNC_0;
/* select gpio pin as adc function */
switch (channel)
{
case 0:
es32f3_channel = ADC_CHANNEL_0;
ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
break;
case 1:
es32f3_channel = ADC_CHANNEL_1;
ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
break;
case 2:
es32f3_channel = ADC_CHANNEL_2;
ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
break;
case 3:
es32f3_channel = ADC_CHANNEL_3;
ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
break;
case 4:
es32f3_channel = ADC_CHANNEL_4;
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
break;
case 5:
es32f3_channel = ADC_CHANNEL_5;
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
break;
case 6:
es32f3_channel = ADC_CHANNEL_6;
ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
break;
case 7:
es32f3_channel = ADC_CHANNEL_7;
ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
break;
case 8:
es32f3_channel = ADC_CHANNEL_8;
ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
break;
case 9:
es32f3_channel = ADC_CHANNEL_9;
ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
break;
case 10:
es32f3_channel = ADC_CHANNEL_10;
ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
break;
case 11:
es32f3_channel = ADC_CHANNEL_11;
ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
break;
case 12:
es32f3_channel = ADC_CHANNEL_12;
ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
break;
case 13:
es32f3_channel = ADC_CHANNEL_13;
ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
break;
case 14:
es32f3_channel = ADC_CHANNEL_14;
ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
break;
case 15:
es32f3_channel = ADC_CHANNEL_15;
ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
break;
case 16:
es32f3_channel = ADC_CHANNEL_16;
break;
case 17:
es32f3_channel = ADC_CHANNEL_17;
break;
case 18:
es32f3_channel = ADC_CHANNEL_18;
break;
default:
break;
}
return es32f3_channel;
}
static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
adc_nch_conf_t nm_config;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
/* config adc channel */
nm_config.channel = es32f3_adc_get_channel(channel);
nm_config.rank = ADC_NCH_RANK_1;
nm_config.samp_time = ADC_SAMPLETIME_4;
ald_adc_normal_channel_config(_hadc, &nm_config);
ald_adc_normal_start(_hadc);
if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK)
*value = ald_adc_normal_get_value(_hadc);
return RT_EOK;
}
static const struct rt_adc_ops es32f3_adc_ops =
{
es32f3_adc_enabled,
es32f3_get_adc_value,
};
int rt_hw_adc_init(void)
{
int result = RT_EOK;
static adc_handle_t _h_adc0;
/* adc function initialization */
_h_adc0.perh = ADC0;
_h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan_mode = DISABLE;
_h_adc0.init.cont_mode = DISABLE;
_h_adc0.init.disc_mode = ADC_ALL_DISABLE;
_h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
_h_adc0.init.conv_res = ADC_CONV_RES_10;
_h_adc0.init.clk_div = ADC_CKDIV_128;
_h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
_h_adc0.init.pos_ref = ADC_POS_REF_VDD;
ald_adc_init(&_h_adc0);
rt_hw_adc_register(&_device_adc0, "adc0", &es32f3_adc_ops, &_h_adc0);
return result;
}
INIT_BOARD_EXPORT(rt_hw_adc_init);
#endif

16
bsp/essemi/es32f369x/drivers/drv_adc.h Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-03 wangyq the first version
*/
#ifndef DRV_ADC_H__
#define DRV_ADC_H__
int rt_hw_adc_init(void);
#endif

136
bsp/essemi/es32f369x/drivers/drv_gpio.c
View File

@ -17,10 +17,10 @@
#ifdef RT_USING_PIN
#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
#define __ES32F3_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
#define __ES32F3_PIN_DEFAULT {-1, 0, 0}
/* ES32F0 GPIO driver */
/* ES32F3 GPIO driver */
struct pin_index
{
int index;
@ -30,71 +30,71 @@ struct pin_index
static const struct pin_index pins[] =
{
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(2, C, 13),
__ES32F0_PIN(3, C, 14),
__ES32F0_PIN(4, C, 15),
__ES32F0_PIN(5, H, 0),
__ES32F0_PIN(6, H, 1),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(8, C, 0),
__ES32F0_PIN(9, C, 1),
__ES32F0_PIN(10, C, 2),
__ES32F0_PIN(11, C, 3),
__ES32F0_PIN(12, H, 3),
__ES32F0_PIN(13, H, 4),
__ES32F0_PIN(14, A, 0),
__ES32F0_PIN(15, A, 1),
__ES32F0_PIN(16, A, 2),
__ES32F0_PIN(17, A, 3),
__ES32F0_PIN(18, F, 0),
__ES32F0_PIN(19, F, 1),
__ES32F0_PIN(20, A, 4),
__ES32F0_PIN(21, A, 5),
__ES32F0_PIN(22, A, 6),
__ES32F0_PIN(23, A, 7),
__ES32F0_PIN(24, C, 4),
__ES32F0_PIN(25, C, 5),
__ES32F0_PIN(26, B, 0),
__ES32F0_PIN(27, B, 1),
__ES32F0_PIN(28, B, 2),
__ES32F0_PIN(29, B, 10),
__ES32F0_PIN(30, B, 11),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(33, B, 12),
__ES32F0_PIN(34, B, 13),
__ES32F0_PIN(35, B, 14),
__ES32F0_PIN(36, B, 15),
__ES32F0_PIN(37, C, 6),
__ES32F0_PIN(38, C, 7),
__ES32F0_PIN(39, C, 8),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(46, A, 13),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(49, A, 14),
__ES32F0_PIN(50, A, 15),
__ES32F0_PIN(51, C, 10),
__ES32F0_PIN(52, C, 11),
__ES32F0_PIN(53, C, 12),
__ES32F0_PIN(54, D, 2),
__ES32F0_PIN(55, B, 3),
__ES32F0_PIN(56, B, 4),
__ES32F0_PIN(57, B, 5),
__ES32F0_PIN(58, B, 6),
__ES32F0_PIN(59, B, 7),
__ES32F0_PIN(60, H, 2),
__ES32F0_PIN(61, B, 8),
__ES32F0_PIN(62, B, 9),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(2, C, 13),
__ES32F3_PIN(3, C, 14),
__ES32F3_PIN(4, C, 15),
__ES32F3_PIN(5, H, 0),
__ES32F3_PIN(6, H, 1),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(8, C, 0),
__ES32F3_PIN(9, C, 1),
__ES32F3_PIN(10, C, 2),
__ES32F3_PIN(11, C, 3),
__ES32F3_PIN(12, H, 3),
__ES32F3_PIN(13, H, 4),
__ES32F3_PIN(14, A, 0),
__ES32F3_PIN(15, A, 1),
__ES32F3_PIN(16, A, 2),
__ES32F3_PIN(17, A, 3),
__ES32F3_PIN(18, F, 0),
__ES32F3_PIN(19, F, 1),
__ES32F3_PIN(20, A, 4),
__ES32F3_PIN(21, A, 5),
__ES32F3_PIN(22, A, 6),
__ES32F3_PIN(23, A, 7),
__ES32F3_PIN(24, C, 4),
__ES32F3_PIN(25, C, 5),
__ES32F3_PIN(26, B, 0),
__ES32F3_PIN(27, B, 1),
__ES32F3_PIN(28, B, 2),
__ES32F3_PIN(29, B, 10),
__ES32F3_PIN(30, B, 11),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(33, B, 12),
__ES32F3_PIN(34, B, 13),
__ES32F3_PIN(35, B, 14),
__ES32F3_PIN(36, B, 15),
__ES32F3_PIN(37, C, 6),
__ES32F3_PIN(38, C, 7),
__ES32F3_PIN(39, C, 8),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(46, A, 13),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(49, A, 14),
__ES32F3_PIN(50, A, 15),
__ES32F3_PIN(51, C, 10),
__ES32F3_PIN(52, C, 11),
__ES32F3_PIN(53, C, 12),
__ES32F3_PIN(54, D, 2),
__ES32F3_PIN(55, B, 3),
__ES32F3_PIN(56, B, 4),
__ES32F3_PIN(57, B, 5),
__ES32F3_PIN(58, B, 6),
__ES32F3_PIN(59, B, 7),
__ES32F3_PIN(60, H, 2),
__ES32F3_PIN(61, B, 8),
__ES32F3_PIN(62, B, 9),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
};
struct pin_irq_map

193
bsp/essemi/es32f369x/drivers/drv_hwtimer.c Normal file
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@ -0,0 +1,193 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-3-19 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <drv_hwtimer.h>
#include <board.h>
#include <ald_cmu.h>
#include <ald_timer.h>
#ifdef RT_USING_HWTIMER
struct es32f3_hwtimer_dev
{
rt_hwtimer_t parent;
timer_handle_t *hwtimer_periph;
IRQn_Type IRQn;
};
#ifdef BSP_USING_HWTIMER0
static struct es32f3_hwtimer_dev hwtimer0;
void BS16T0_Handler(void)
{
ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer0.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode)
{
ald_timer_base_stop(hwtimer0.hwtimer_periph);
}
}
#endif
#ifdef BSP_USING_HWTIMER1
static struct es32f3_hwtimer_dev hwtimer1;
/* can not use when UART2 Handler is enabled */
void BS16T1_Handler(void)
{
/* if BS16T1 it */
if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
{
ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer1.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
{
ald_timer_base_stop(hwtimer1.hwtimer_periph);
}
}
}
#endif
static struct rt_hwtimer_info es32f3_hwtimer_info =
{
96000000, /* maximum count frequency */
1, /* minimum count frequency */
65535, /* counter maximum value */
HWTIMER_CNTMODE_UP
};
static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
if (1 == state)
{
ald_timer_base_init(hwtimer->hwtimer_periph);
ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
NVIC_EnableIRQ(hwtimer->IRQn);
}
hwtimer->parent.freq = ald_cmu_get_pclk1_clock();
es32f3_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock();
es32f3_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock();
}
static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer,
rt_uint32_t cnt,
rt_hwtimer_mode_t mode)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
ald_timer_base_start(hwtimer->hwtimer_periph);
return RT_EOK;
}
static void es32f3_hwtimer_stop(rt_hwtimer_t *timer)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
ald_timer_base_stop(hwtimer->hwtimer_periph);
}
static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
uint32_t hwtimer_count = 0;
RT_ASSERT(hwtimer != RT_NULL);
hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT);
return hwtimer_count;
}
static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer,
rt_uint32_t cmd,
void *args)
{
rt_err_t ret = RT_EOK;
rt_uint32_t freq = 0;
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
freq = *(rt_uint32_t *)args;
if (freq != ald_cmu_get_pclk1_clock())
{
ret = -RT_ERROR;
}
break;
case HWTIMER_CTRL_STOP:
ald_timer_base_stop(hwtimer->hwtimer_periph);
break;
default:
ret = RT_EINVAL;
break;
}
return ret;
}
static struct rt_hwtimer_ops es32f3_hwtimer_ops =
{
es32f3_hwtimer_init,
es32f3_hwtimer_start,
es32f3_hwtimer_stop,
es32f3_hwtimer_count_get,
es32f3_hwtimer_control
};
int rt_hw_hwtimer_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_HWTIMER0
static timer_handle_t _hwtimer_periph0;
_hwtimer_periph0.perh = BS16T0;
hwtimer0.IRQn = BS16T0_IRQn;
hwtimer0.hwtimer_periph = &_hwtimer_periph0;
hwtimer0.parent.info = &es32f3_hwtimer_info;
hwtimer0.parent.ops = &es32f3_hwtimer_ops;
ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0);
#endif
#ifdef BSP_USING_HWTIMER1
static timer_handle_t _hwtimer_periph1;
_hwtimer_periph1.perh = BS16T1;
hwtimer1.IRQn = BS16T1_IRQn;
hwtimer1.hwtimer_periph = &_hwtimer_periph1;
hwtimer1.parent.info = &es32f3_hwtimer_info;
hwtimer1.parent.ops = &es32f3_hwtimer_ops;
ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
#endif
return ret;
}
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
#endif

16
bsp/essemi/es32f369x/drivers/drv_hwtimer.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-3-19 wangyq the first version
*/
#ifndef DRV_HWTIMER_H__
#define DRV_HWTIMER_H__
int rt_hw_hwtimer_init(void);
#endif

11
bsp/essemi/es32f369x/drivers/drv_i2c.c
View File

@ -16,6 +16,7 @@
#include "drv_i2c.h"
#include <ald_i2c.h>
#include <ald_gpio.h>
#include <rtdbg.h>
#ifdef RT_USING_I2C
@ -55,8 +56,8 @@ static void _i2c_init(void)
ald_i2c_reset(&_h_i2c0);
ald_i2c_init(&_h_i2c0);
/* PB8->I2C0_SCL, PB9->I2C0_SDA */
ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
/* PB06->I2C0_SCL, PB07->I2C0_SDA */
ald_gpio_init(GPIOB, GPIO_PIN_6 | GPIO_PIN_7, &gpio_instruct);
#endif
#ifdef BSP_USING_I2C1
@ -90,7 +91,7 @@ static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
{
if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
{
i2c_dbg("i2c bus write failed,i2c bus stop!\n");
LOG_E("i2c bus write failed,i2c bus stop!\n");
goto out;
}
}
@ -98,7 +99,7 @@ static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
{
if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
{
i2c_dbg("i2c bus write failed,i2c bus stop!\n");
LOG_E("i2c bus write failed,i2c bus stop!\n");
goto out;
}
}
@ -107,7 +108,7 @@ static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
ret = i;
out:
i2c_dbg("send stop condition\n");
LOG_E("send stop condition\n");
return ret;
}

171
bsp/essemi/es32f369x/drivers/drv_pwm.c Normal file
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@ -0,0 +1,171 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-11 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include <ald_cmu.h>
#include <ald_timer.h>
#include <ald_gpio.h>
static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
{
uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
(timer_initstruct->init.prescaler + 1);
WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
timer_initstruct->init.period = (uint32_t)_arr;
}
static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns)
{
uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
(timer_initstruct->init.prescaler + 1);
if (ch == TIMER_CHANNEL_1)
WRITE_REG(timer_initstruct->perh->CCVAL1, (uint32_t)tmp);
else if (ch == TIMER_CHANNEL_2)
WRITE_REG(timer_initstruct->perh->CCVAL2, (uint32_t)tmp);
else if (ch == TIMER_CHANNEL_3)
WRITE_REG(timer_initstruct->perh->CCVAL3, (uint32_t)tmp);
else if (ch == TIMER_CHANNEL_4)
WRITE_REG(timer_initstruct->perh->CCVAL4, (uint32_t)tmp);
}
static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
rt_err_t ret = RT_EOK;
uint32_t _ccep;
timer_channel_t pwm_channel;
timer_oc_init_t tim_ocinit;
timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data;
struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
RT_ASSERT(timer_initstruct != RT_NULL);
tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1;
tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH;
tim_ocinit.oc_fast_en = DISABLE;
tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH;
tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET;
tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET;
/* select pwm output channel */
if (1 == cfg->channel)
pwm_channel = TIMER_CHANNEL_1;
else if (2 == cfg->channel)
pwm_channel = TIMER_CHANNEL_2;
else if (3 == cfg->channel)
pwm_channel = TIMER_CHANNEL_3;
else if (4 == cfg->channel)
pwm_channel = TIMER_CHANNEL_4;
else
return RT_EINVAL;
switch (cmd)
{
case PWM_CMD_ENABLE:
ald_timer_pwm_start(timer_initstruct, pwm_channel);
break;
case PWM_CMD_DISABLE:
ald_timer_pwm_stop(timer_initstruct, pwm_channel);
break;
case PWM_CMD_SET:
_ccep = timer_initstruct->perh->CCEP;
/* count registers max 0xFFFF, auto adjust prescaler */
do
{
pwm_set_freq(timer_initstruct, cfg->period);
timer_initstruct->init.prescaler ++;
}
while (timer_initstruct->init.period > 0xFFFF);
/* update prescaler */
WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler);
ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse);
timer_initstruct->perh->CCEP = _ccep;
break;
case PWM_CMD_GET:
cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
READ_REG(timer_initstruct->perh->AR);
break;
default:
break;
}
return ret;
}
const static struct rt_pwm_ops es32f3_pwm_ops =
{
es32f3_pwm_control
};
int rt_hw_pwm_init(void)
{
rt_err_t ret = RT_EOK;
gpio_init_t gpio_initstructure;
gpio_initstructure.mode = GPIO_MODE_OUTPUT;
gpio_initstructure.odos = GPIO_PUSH_PULL;
gpio_initstructure.pupd = GPIO_PUSH_UP;
gpio_initstructure.podrv = GPIO_OUT_DRIVE_6;
gpio_initstructure.nodrv = GPIO_OUT_DRIVE_6;
gpio_initstructure.flt = GPIO_FILTER_DISABLE;
gpio_initstructure.type = GPIO_TYPE_TTL;
#ifdef BSP_USING_PWM0 /* 4 channels */
static struct rt_device_pwm pwm_dev0;
static timer_handle_t timer_initstruct0;
timer_initstruct0.perh = GP16C4T0;
ald_timer_pwm_init(&timer_initstruct0);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_2;
ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f3_pwm_ops,
&timer_initstruct0);
#endif
#ifdef BSP_USING_PWM1 /* 4 channels */
static struct rt_device_pwm pwm_dev1;
static timer_handle_t timer_initstruct1;
timer_initstruct1.perh = GP16C4T1;
ald_timer_pwm_init(&timer_initstruct1);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_5;
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f3_pwm_ops,
&timer_initstruct1);
#endif
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_pwm_init);

16
bsp/essemi/es32f369x/drivers/drv_pwm.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-11 wangyq the first version
*/
#ifndef DRV_PWM_H__
#define DRV_PWM_H__
int rt_hw_pwm_init(void);
#endif

158
bsp/essemi/es32f369x/drivers/drv_rtc.c Normal file
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@ -0,0 +1,158 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-22 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <string.h>
#include "board.h"
#include "drv_rtc.h"
#include <ald_cmu.h>
#include <ald_rtc.h>
#ifdef RT_USING_RTC
static void __rtc_init(rtc_init_t *init)
{
assert_param(IS_RTC_HOUR_FORMAT(init->hour_format));
assert_param(IS_RTC_OUTPUT_SEL(init->output));
assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
ald_rtc_reset();
RTC_UNLOCK();
MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS);
MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS);
MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS);
MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS);
RTC_LOCK();
return;
}
static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
struct tm time_temp;
struct tm *pNow;
rtc_date_t date;
rtc_time_t time;
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC);
time_temp.tm_sec = time.second;
time_temp.tm_min = time.minute;
time_temp.tm_hour = time.hour;
time_temp.tm_mday = date.day;
time_temp.tm_mon = date.month - 1;
time_temp.tm_year = date.year - 1900 + 2000;
*((time_t *)args) = mktime(&time_temp);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
rt_enter_critical();
/* converts calendar time time into local time. */
pNow = localtime((const time_t *)args);
/* copy the statically located variable */
memcpy(&time_temp, pNow, sizeof(struct tm));
/* unlock scheduler. */
rt_exit_critical();
time.hour = time_temp.tm_hour;
time.minute = time_temp.tm_min;
time.second = time_temp.tm_sec;
date.year = time_temp.tm_year + 1900 - 2000;
date.month = time_temp.tm_mon + 1;
date.day = time_temp.tm_mday;
ald_rtc_set_time(&time, RTC_FORMAT_DEC);
ald_rtc_set_date(&date, RTC_FORMAT_DEC);
/* start RTC */
RTC_UNLOCK();
SET_BIT(RTC->CON, RTC_CON_GO_MSK);
RTC_LOCK();
break;
case RT_DEVICE_CTRL_RTC_GET_ALARM:
break;
case RT_DEVICE_CTRL_RTC_SET_ALARM:
break;
default:
break;
}
return result;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops es32f0_rtc_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
es32f0_rtc_control
};
#endif
int rt_hw_rtc_init(void)
{
rt_err_t ret = RT_EOK;
static struct rt_device rtc_dev;
rtc_init_t rtc_initstruct;
/* enable external 32.768kHz */
CMU_LOSC_ENABLE();
ald_cmu_losc_safe_config(ENABLE);
/* set default time */
RTC_UNLOCK();
WRITE_REG(RTC->TIME, 0x134251);
WRITE_REG(RTC->DATE, 0x1190401);
RTC_LOCK();
/* RTC function initialization */
rtc_initstruct.hour_format = RTC_HOUR_FORMAT_24;
rtc_initstruct.asynch_pre_div = 0;
rtc_initstruct.synch_pre_div = 32767;
rtc_initstruct.output = RTC_OUTPUT_DISABLE;
__rtc_init(&rtc_initstruct);
rtc_dev.type = RT_Device_Class_RTC;
rtc_dev.rx_indicate = RT_NULL;
rtc_dev.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
rtc_dev.ops = &es32f0_rtc_ops;
#else
rtc_dev.init = RT_NULL;
rtc_dev.open = RT_NULL;
rtc_dev.close = RT_NULL;
rtc_dev.read = RT_NULL;
rtc_dev.write = RT_NULL;
rtc_dev.control = es32f0_rtc_control;
#endif
rtc_dev.user_data = RTC;
ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif

16
bsp/essemi/es32f369x/drivers/drv_rtc.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-22 wangyq the first version
*/
#ifndef DRV_RTC_H__
#define DRV_RTC_H__
int rt_hw_rtc_init(void);
#endif

2
bsp/essemi/es32f369x/drivers/drv_uart.c
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@ -39,7 +39,7 @@ static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial
gpio_initstructure.odos = GPIO_PUSH_PULL;
gpio_initstructure.pupd = GPIO_PUSH_UP;
gpio_initstructure.podrv = GPIO_OUT_DRIVE_1;
gpio_initstructure.nodrv = GPIO_OUT_DRIVE_0_1;
gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1;
gpio_initstructure.flt = GPIO_FILTER_DISABLE;
gpio_initstructure.type = GPIO_TYPE_TTL;

34
bsp/essemi/es32f369x/drivers/linker_scripts/link.icf Normal file
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@ -0,0 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, last block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

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bsp/essemi/es32f369x/project.ewd Normal file
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bsp/essemi/es32f369x/project.ewp Normal file
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bsp/essemi/es32f369x/project.eww Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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bsp/essemi/es32f369x/project.uvprojx
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@ -331,7 +331,7 @@
<MiscControls />
<Define>ES32F36xx</Define>
<Undefine />
<IncludePath>.;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common</IncludePath>
<IncludePath>.;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -795,27 +795,6 @@
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>can.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\can\can.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>i2c_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\i2c\i2c_core.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>i2c_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\i2c\i2c_dev.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pin.c</FileName>

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bsp/essemi/es32f369x/rtconfig.h
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@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
@ -76,8 +76,6 @@
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_USING_I2C
#define RT_USING_PIN
/* Using USB */
@ -166,6 +164,18 @@
/* CAN Drivers */
/* ADC Drivers */
/* RTC Drivers */
/* HWtimer Drivers */
/* PWM Drivers */
/* Onboard Peripheral Drivers */
/* Offboard Peripheral Drivers */

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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>