From 6a30ec26256c7bb82a764e9ac59d486031df0bd3 Mon Sep 17 00:00:00 2001 From: sheltonyu <59359365+sheltonyu@users.noreply.github.com> Date: Tue, 3 Sep 2024 00:51:06 +0800 Subject: [PATCH] [bsp/at32] ethernet support phy lan8720 and yt8512 --- bsp/at32/at32f407-start/board/Kconfig | 6 +++ bsp/at32/at32f437-start/board/Kconfig | 6 +++ bsp/at32/libraries/rt_drivers/drv_emac.c | 39 ++++++++++++++++---- bsp/at32/libraries/rt_drivers/drv_emac.h | 47 +++++++++++++++++++++++- 4 files changed, 88 insertions(+), 10 deletions(-) diff --git a/bsp/at32/at32f407-start/board/Kconfig b/bsp/at32/at32f407-start/board/Kconfig index 1032819de2..b672271c64 100644 --- a/bsp/at32/at32f407-start/board/Kconfig +++ b/bsp/at32/at32f407-start/board/Kconfig @@ -42,6 +42,12 @@ menu "On-chip Peripheral Drivers" config PHY_USING_DP83848 bool "PHY USING DP83848" + + config PHY_USING_LAN8720 + bool "PHY USING LAN8720" + + config PHY_USING_YT8512 + bool "PHY USING YT8512" endchoice endif diff --git a/bsp/at32/at32f437-start/board/Kconfig b/bsp/at32/at32f437-start/board/Kconfig index 8dc22159dd..07a9e6f778 100644 --- a/bsp/at32/at32f437-start/board/Kconfig +++ b/bsp/at32/at32f437-start/board/Kconfig @@ -81,6 +81,12 @@ menu "On-chip Peripheral Drivers" config PHY_USING_DP83848 bool "PHY USING DP83848" + + config PHY_USING_LAN8720 + bool "PHY USING LAN8720" + + config PHY_USING_YT8512 + bool "PHY USING YT8512" endchoice endif diff --git a/bsp/at32/libraries/rt_drivers/drv_emac.c b/bsp/at32/libraries/rt_drivers/drv_emac.c index 50fe56184b..23b4fcdd55 100644 --- a/bsp/at32/libraries/rt_drivers/drv_emac.c +++ b/bsp/at32/libraries/rt_drivers/drv_emac.c @@ -10,6 +10,7 @@ * performance * 2022-10-15 shelton optimize code * 2023-10-18 shelton optimize code + * 2024-09-02 shelton add support phy lan8720 and yt8512 */ #include "drv_emac.h" @@ -161,7 +162,8 @@ static void phy_clock_config(void) /* 83848 clkout output 50 mhz */ #if defined (SOC_SERIES_AT32F407) crm_clock_out_set(CRM_CLKOUT_SCLK); -#if defined (PHY_USING_DM9162) +#if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) || \ + defined (PHY_USING_YT8512) crm_clkout_div_set(CRM_CLKOUT_DIV_8); #elif defined (PHY_USING_DP83848) crm_clkout_div_set(CRM_CLKOUT_DIV_4); @@ -170,7 +172,8 @@ static void phy_clock_config(void) #if defined (SOC_SERIES_AT32F437) crm_clock_out1_set(CRM_CLKOUT1_PLL); -#if defined (PHY_USING_DM9162) +#if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) || \ + defined (PHY_USING_YT8512) crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_2); #elif defined (PHY_USING_DP83848) crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_1); @@ -260,7 +263,7 @@ static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_dupl { return ERROR; } -#ifdef PHY_USING_DM9162 +#if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) if(data & PHY_FULL_DUPLEX_100MBPS_BIT) { emac_fast_speed_set(EMAC_SPEED_100MBPS); @@ -282,7 +285,7 @@ static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_dupl emac_duplex_mode_set(EMAC_HALF_DUPLEX); } #endif -#ifdef PHY_USING_DP83848 +#if defined (PHY_USING_DP83848) if(data & PHY_DUPLEX_MODE) { emac_duplex_mode_set(EMAC_FULL_DUPLEX); @@ -299,6 +302,24 @@ static error_status emac_speed_config(emac_auto_negotiation_type nego, emac_dupl { emac_fast_speed_set(EMAC_SPEED_100MBPS); } +#endif +#if defined (PHY_USING_YT8512) + if(data & PHY_DUPLEX_MODE) + { + emac_duplex_mode_set(EMAC_FULL_DUPLEX); + } + else + { + emac_duplex_mode_set(EMAC_HALF_DUPLEX); + } + if(data & PHY_SPEED_MODE) + { + emac_fast_speed_set(EMAC_SPEED_100MBPS); + } + else + { + emac_fast_speed_set(EMAC_SPEED_10MBPS); + } #endif } else @@ -475,12 +496,12 @@ rt_err_t emac_txpkt_chainmode(rt_uint32_t frame_length) if((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != (u32)RESET) { /* return error: own bit set */ - return RT_ERROR; + return -RT_ERROR; } if(frame_length == 0) { - return RT_ERROR; + return -RT_ERROR; } if(frame_length > EMAC_MAX_PACKET_LENGTH) @@ -629,7 +650,7 @@ rt_err_t emac_rxpkt_chainmode(void) if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_OWN) != (u32)RESET) { /* return error: own bit set */ - return RT_ERROR; + return -RT_ERROR; } if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (u32)RESET) { @@ -660,7 +681,7 @@ rt_err_t emac_rxpkt_chainmode(void) dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr); } - return RT_ERROR; + return -RT_ERROR; } /** @@ -809,7 +830,9 @@ static void phy_linkchange() if (SR & (PHY_SPEED_MODE)) { +#if defined (PHY_USING_DP83848) phy_speed_new |= PHY_10M; +#endif } if (SR & (PHY_DUPLEX_MODE)) diff --git a/bsp/at32/libraries/rt_drivers/drv_emac.h b/bsp/at32/libraries/rt_drivers/drv_emac.h index 71f57c3e0f..d9a1e50829 100644 --- a/bsp/at32/libraries/rt_drivers/drv_emac.h +++ b/bsp/at32/libraries/rt_drivers/drv_emac.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-05-16 shelton first version + * 2024-09-02 shelton add support phy lan8720 and yt8512 */ #ifndef __DRV_EMAC_H__ @@ -57,8 +58,6 @@ #define PHY_INTERRUPT_FLAG_REG 0x15U /* the phy interrupt mask register. */ #define PHY_INTERRUPT_MASK_REG 0x15U - #define PHY_LINK_CHANGE_FLAG (1<<2) - #define PHY_LINK_CHANGE_MASK (1<<9) #define PHY_INT_MASK 0 #elif defined (PHY_USING_DP83848) #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ @@ -84,6 +83,50 @@ /* the phy interrupt mask register. */ #define PHY_INTERRUPT_MASK_REG 0x12U #define PHY_INT_MASK (1<<5) +#elif defined (PHY_USING_LAN8720) + #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ + #define PHY_STATUS_REG (0x01) /*!< basic mode status register */ + #define PHY_SPECIFIED_CS_REG (0x1F) /*!< specified configuration and status register */ + /* phy control register */ + #define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */ + #define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */ + #define PHY_RESET_BIT (0x8000) /*!< reset phy */ + /* phy status register */ + #define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */ + #define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */ + /* phy specified control/status register */ + #define PHY_FULL_DUPLEX_100MBPS_BIT (0x0018) /*!< full duplex 100 mbps */ + #define PHY_HALF_DUPLEX_100MBPS_BIT (0x0008) /*!< half duplex 100 mbps */ + #define PHY_FULL_DUPLEX_10MBPS_BIT (0x0014) /*!< full duplex 10 mbps */ + #define PHY_HALF_DUPLEX_10MBPS_BIT (0x0004) /*!< half duplex 10 mbps */ + #define PHY_DUPLEX_MODE (0x0100) /*!< full duplex mode */ + #define PHY_SPEED_MODE (0x2000) /*!< 100 mbps */ + /* the phy interrupt source flag register. */ + #define PHY_INTERRUPT_FLAG_REG 0x1DU + /* the phy interrupt mask register. */ + #define PHY_INTERRUPT_MASK_REG 0x1EU + #define PHY_INT_MASK (1<<4) +#elif defined (PHY_USING_YT8512) + #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ + #define PHY_STATUS_REG (0x01) /*!< basic mode status register */ + #define PHY_SPECIFIED_CS_REG (0x11) /*!< phy status register */ + /* phy control register */ + #define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */ + #define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */ + #define PHY_RESET_BIT (0x8000) /*!< reset phy */ + /* phy status register */ + #define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */ + #define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */ + + #define PHY_DUPLEX_MODE (0x2000) /*!< full duplex mode */ + #define PHY_SPEED_MODE (0x4000) /*!< 100 mbps */ + + /* the phy interrupt source flag register. */ + #define PHY_INTERRUPT_FLAG_REG 0x13U + #define PHY_LINK_CHANGE_FLAG (3<<10) + /* the phy interrupt mask register. */ + #define PHY_INTERRUPT_MASK_REG 0x12U + #define PHY_INT_MASK (3<<10) #endif #endif /* __DRV_EMAC_H__ */