add dm9000a driver; remove the polling timer of enc29j60 and fix the tx interrupt issue;
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@197 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
parent
7ae254abf8
commit
680b77cd89
@ -15,7 +15,7 @@ env = Environment(tools = ['mingw'],
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
env.AppendUnique(CPPPATH = bsp_path)
|
||||
env.AppendUnique(CCFLAGS = ' -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD')
|
||||
env.AppendUnique(CCFLAGS = ' -DUSE_STDPERIPH_DRIVER -D' + device_type)
|
||||
|
||||
Export('env')
|
||||
Export('RTT_ROOT')
|
||||
|
@ -17,13 +17,12 @@
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_DFS
|
||||
/* dfs init */
|
||||
#include <dfs_init.h>
|
||||
/* dfs filesystem:FAT filesystem init */
|
||||
#include <dfs_fat.h>
|
||||
/* dfs filesystem:EFS filesystem init */
|
||||
#include <dfs_efs.h>
|
||||
/* dfs Filesystem APIs */
|
||||
@ -33,6 +32,7 @@
|
||||
#ifdef RT_USING_LWIP
|
||||
#include <lwip/sys.h>
|
||||
#include <lwip/api.h>
|
||||
#include <netif/ethernetif.h>
|
||||
#endif
|
||||
|
||||
void rt_init_thread_entry(void* parameter)
|
||||
@ -73,6 +73,18 @@ void rt_init_thread_entry(void* parameter)
|
||||
#ifdef RT_USING_LWIP
|
||||
{
|
||||
extern void lwip_sys_init(void);
|
||||
#ifdef RT_USING_LWIP
|
||||
eth_system_device_init();
|
||||
|
||||
/* register ethernetif device */
|
||||
#if STM32_ETH_IF == 0
|
||||
rt_hw_enc28j60_init();
|
||||
#elif STM32_ETH_IF == 1
|
||||
rt_hw_dm9000_init();
|
||||
#endif
|
||||
/* re-init device driver */
|
||||
rt_device_init_all();
|
||||
#endif
|
||||
|
||||
/* init lwip system */
|
||||
lwip_sys_init();
|
||||
|
@ -42,14 +42,24 @@
|
||||
// <i>Default: 1
|
||||
#define STM32_CONSOLE_USART 1
|
||||
|
||||
// <o> Ethernet Interface: <0=> Microchip ENC28J60 <1=> Davicom DM9000A
|
||||
// <i>Default: 0
|
||||
#define STM32_ETH_IF 0
|
||||
|
||||
void rt_hw_board_led_on(int n);
|
||||
void rt_hw_board_led_off(int n);
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
void rt_hw_usart_init(void);
|
||||
|
||||
/* SD Card init function */
|
||||
void rt_hw_sdcard_init(void);
|
||||
void rt_hw_msd_init(void);
|
||||
|
||||
/* ETH interface init function */
|
||||
void rt_hw_enc28j60_init(void);
|
||||
void rt_hw_dm9000_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
@ -1,9 +1,10 @@
|
||||
#include <rtthread.h>
|
||||
#include "dm9000.h"
|
||||
#include "dm9000a.h"
|
||||
|
||||
#include <netif/ethernetif.h>
|
||||
#include "lwipopts.h"
|
||||
#include "stm32f10x.h"
|
||||
#include "stm32f10x_fsmc.h"
|
||||
|
||||
// #define DM9000_DEBUG 1
|
||||
#if DM9000_DEBUG
|
||||
@ -13,11 +14,13 @@
|
||||
#endif
|
||||
|
||||
/*
|
||||
* DM9000 interrupt line is connected to PA1
|
||||
* 16bit mode
|
||||
* DM9000 interrupt line is connected to PF7
|
||||
*/
|
||||
//--------------------------------------------------------
|
||||
|
||||
#define DM9000_PHY 0x40 /* PHY address 0x01 */
|
||||
#define RST_1() GPIO_SetBits(GPIOF,GPIO_Pin_6)
|
||||
#define RST_0() GPIO_ResetBits(GPIOF,GPIO_Pin_6)
|
||||
|
||||
#define MAX_ADDR_LEN 6
|
||||
enum DM9000_PHY_mode
|
||||
@ -173,12 +176,11 @@ void rt_dm9000_isr()
|
||||
/* Received the coming packet */
|
||||
if (int_status & ISR_PRS)
|
||||
{
|
||||
rt_err_t result;
|
||||
/* disable receive interrupt */
|
||||
dm9000_device.imr_all = IMR_PAR | IMR_PTM;
|
||||
|
||||
/* a frame has been received */
|
||||
result = eth_device_ready(&(dm9000_device.parent));
|
||||
if (result != RT_EOK) rt_kprintf("eth notification failed\n");
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
eth_device_ready(&(dm9000_device.parent));
|
||||
}
|
||||
|
||||
/* Transmit Interrupt check */
|
||||
@ -274,7 +276,7 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
|
||||
while (!(phy_read(1) & 0x20))
|
||||
{
|
||||
/* autonegation complete bit */
|
||||
delay_ms(10);
|
||||
rt_thread_delay(10);
|
||||
i++;
|
||||
if (i == 10000)
|
||||
{
|
||||
@ -361,15 +363,6 @@ static rt_err_t rt_dm9000_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
/* transmit packet. */
|
||||
rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
|
||||
{
|
||||
struct pbuf* q;
|
||||
rt_int32_t len;
|
||||
rt_uint16_t* ptr;
|
||||
|
||||
#if DM9000_DEBUG
|
||||
rt_uint8_t* dump_ptr;
|
||||
rt_uint32_t cnt = 0;
|
||||
#endif
|
||||
|
||||
DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
|
||||
|
||||
/* lock DM9000 device */
|
||||
@ -381,29 +374,40 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
|
||||
/* Move data to DM9000 TX RAM */
|
||||
DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
|
||||
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
len = q->len;
|
||||
ptr = q->payload;
|
||||
/* q traverses through linked list of pbuf's
|
||||
* This list MUST consist of a single packet ONLY */
|
||||
struct pbuf *q;
|
||||
rt_uint16_t pbuf_index = 0;
|
||||
rt_uint8_t word[2], word_index = 0;
|
||||
|
||||
#if DM9000_DEBUG
|
||||
dump_ptr = q->payload;
|
||||
#endif
|
||||
|
||||
/* use 16bit mode to write data to DM9000 RAM */
|
||||
while (len > 0)
|
||||
q = p;
|
||||
/* Write data into dm9000a, two bytes at a time
|
||||
* Handling pbuf's with odd number of bytes correctly
|
||||
* No attempt to optimize for speed has been made */
|
||||
while (q)
|
||||
{
|
||||
DM9000_outw(DM9000_DATA_BASE, *ptr);
|
||||
ptr ++;
|
||||
len -= 2;
|
||||
|
||||
#ifdef DM9000_DEBUG
|
||||
DM9000_TRACE("%02x ", *dump_ptr++);
|
||||
if (++cnt % 16 == 0) DM9000_TRACE("\n");
|
||||
#endif
|
||||
if (pbuf_index < q->len)
|
||||
{
|
||||
word[word_index++] = ((u8_t*)q->payload)[pbuf_index++];
|
||||
if (word_index == 2)
|
||||
{
|
||||
DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
|
||||
word_index = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
q = q->next;
|
||||
pbuf_index = 0;
|
||||
}
|
||||
}
|
||||
/* One byte could still be unsent */
|
||||
if (word_index == 1)
|
||||
{
|
||||
DM9000_outw(DM9000_DATA_BASE, word[0]);
|
||||
}
|
||||
}
|
||||
DM9000_TRACE("\n");
|
||||
|
||||
if (dm9000_device.packet_cnt == 0)
|
||||
{
|
||||
@ -445,11 +449,6 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
|
||||
struct pbuf* p;
|
||||
rt_uint32_t rxbyte;
|
||||
|
||||
#if DM9000_DEBUG
|
||||
rt_uint8_t* dump_ptr;
|
||||
rt_uint32_t cnt = 0;
|
||||
#endif
|
||||
|
||||
/* init p pointer */
|
||||
p = RT_NULL;
|
||||
|
||||
@ -492,20 +491,11 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
|
||||
data = (rt_uint16_t*)q->payload;
|
||||
len = q->len;
|
||||
|
||||
#if DM9000_DEBUG
|
||||
dump_ptr = q->payload;
|
||||
#endif
|
||||
|
||||
while (len > 0)
|
||||
{
|
||||
*data = DM9000_inw(DM9000_DATA_BASE);
|
||||
data ++;
|
||||
len -= 2;
|
||||
|
||||
#if DM9000_DEBUG
|
||||
DM9000_TRACE("%02x ", *dump_ptr++);
|
||||
if (++cnt % 16 == 0) DM9000_TRACE("\n");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
DM9000_TRACE("\n");
|
||||
@ -556,6 +546,12 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
|
||||
p = RT_NULL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* restore receive interrupt */
|
||||
dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
|
||||
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
|
||||
}
|
||||
|
||||
/* unlock DM9000 device */
|
||||
rt_sem_release(&sem_lock);
|
||||
@ -563,11 +559,12 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
|
||||
return p;
|
||||
}
|
||||
|
||||
|
||||
static void RCC_Configuration(void)
|
||||
{
|
||||
/* enable gpiob port clock */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF | RCC_APB2Periph_AFIO, ENABLE);
|
||||
/* enable FSMC clock */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
|
||||
}
|
||||
|
||||
static void NVIC_Configuration(void)
|
||||
@ -578,7 +575,7 @@ static void NVIC_Configuration(void)
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
|
||||
|
||||
/* Enable the EXTI0 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
@ -590,24 +587,109 @@ static void GPIO_Configuration()
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
EXTI_InitTypeDef EXTI_InitStructure;
|
||||
|
||||
/* configure PA1 as external interrupt */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
|
||||
/* configure PF6 as eth RST */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOF,&GPIO_InitStructure);
|
||||
GPIO_ResetBits(GPIOF,GPIO_Pin_6);
|
||||
RST_1();
|
||||
|
||||
/* configure PF7 as external interrupt */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_Init(GPIOF, &GPIO_InitStructure);
|
||||
|
||||
/* Connect DM9000 EXTI Line to GPIOA Pin 1 */
|
||||
GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource1);
|
||||
/* Connect DM9000 EXTI Line to GPIOF Pin 7 */
|
||||
GPIO_EXTILineConfig(GPIO_PortSourceGPIOF, GPIO_PinSource7);
|
||||
|
||||
/* Configure DM9000 EXTI Line to generate an interrupt on falling edge */
|
||||
EXTI_InitStructure.EXTI_Line = EXTI_Line1;
|
||||
EXTI_InitStructure.EXTI_Line = EXTI_Line7;
|
||||
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
|
||||
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||||
EXTI_Init(&EXTI_InitStructure);
|
||||
|
||||
/* Clear the Key Button EXTI line pending bit */
|
||||
EXTI_ClearITPendingBit(EXTI_Line1);
|
||||
EXTI_ClearITPendingBit(EXTI_Line7);
|
||||
}
|
||||
|
||||
static void FSMC_Configuration()
|
||||
{
|
||||
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
|
||||
FSMC_NORSRAMTimingInitTypeDef p;
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
|
||||
RCC_APB2Periph_GPIOF, ENABLE);
|
||||
|
||||
/*-- GPIO Configuration ------------------------------------------------------*/
|
||||
/* SRAM Data lines configuration */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
|
||||
GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
|
||||
GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
|
||||
GPIO_Pin_15;
|
||||
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||
|
||||
/* SRAM Address lines configuration */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
|
||||
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
|
||||
GPIO_Pin_14 | GPIO_Pin_15;
|
||||
GPIO_Init(GPIOF, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
|
||||
GPIO_Pin_4 | GPIO_Pin_5;
|
||||
GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
/* NOE and NWE configuration */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
/* NE3 NE4 configuration */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12;
|
||||
GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||||
|
||||
/* NBL0, NBL1 configuration */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
|
||||
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
p.FSMC_AddressSetupTime = 0;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 2;
|
||||
p.FSMC_BusTurnAroundDuration = 0;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
|
||||
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
|
||||
|
||||
/* Enable FSMC Bank1_SRAM Bank4 */
|
||||
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
|
||||
}
|
||||
|
||||
void rt_hw_dm9000_init()
|
||||
@ -615,6 +697,7 @@ void rt_hw_dm9000_init()
|
||||
RCC_Configuration();
|
||||
NVIC_Configuration();
|
||||
GPIO_Configuration();
|
||||
FSMC_Configuration();
|
||||
|
||||
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
||||
@ -651,8 +734,6 @@ void rt_hw_dm9000_init()
|
||||
eth_device_init(&(dm9000_device.parent), "e0");
|
||||
}
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
void dm9000(void)
|
||||
{
|
||||
rt_kprintf("\n");
|
||||
@ -671,36 +752,8 @@ void dm9000(void)
|
||||
rt_kprintf("IMR (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
|
||||
rt_kprintf("\n");
|
||||
}
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT(dm9000, dm9000 register dump);
|
||||
|
||||
void rx(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
dm9000_io_write(DM9000_ISR, ISR_PRS); /* Clear rx status */
|
||||
|
||||
/* a frame has been received */
|
||||
result = eth_device_ready(&(dm9000_device.parent));
|
||||
if (result != RT_EOK) rt_kprintf("eth notification failed\n");
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT(rx, notify packet rx);
|
||||
|
||||
#endif
|
||||
|
||||
void EXTI1_IRQHandler(void)
|
||||
{
|
||||
extern void rt_dm9000_isr(void);
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_dm9000_isr();
|
||||
|
||||
/* Clear the Key Button EXTI line pending bit */
|
||||
EXTI_ClearITPendingBit(EXTI_Line1);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
rt_hw_interrupt_thread_switch();
|
||||
}
|
||||
|
@ -1,17 +1,20 @@
|
||||
#ifndef __DM9000_H__
|
||||
#define __DM9000_H__
|
||||
|
||||
#define DM9000_IO_BASE 0x6C100000
|
||||
#define DM9000_DATA_BASE 0x6C100008
|
||||
#define DM9000_IO_BASE 0x6C000000
|
||||
#define DM9000_DATA_BASE 0x6C000008
|
||||
|
||||
#define DM9000_IO (*((volatile rt_uint16_t *) DM9000_IO_BASE)) // CMD = 0
|
||||
#define DM9000_DATA (*((volatile rt_uint16_t *) DM9000_DATA_BASE)) // CMD = 1
|
||||
#define DM9000_IO (*((volatile rt_uint16_t *) 0x6C000000)) // CMD = 0
|
||||
#define DM9000_DATA (*((volatile rt_uint16_t *) 0x6C000008)) // CMD = 1
|
||||
|
||||
#define DM9000_inb(r) (*(volatile rt_uint8_t *)r)
|
||||
#define DM9000_outb(r, d) (*(volatile rt_uint8_t *)r = d)
|
||||
#define DM9000_inw(r) (*(volatile rt_uint16_t *)r)
|
||||
#define DM9000_outw(r, d) (*(volatile rt_uint16_t *)r = d)
|
||||
|
||||
#define RST_1() GPIO_SetBits(GPIOF,GPIO_Pin_6)
|
||||
#define RST_0() GPIO_ResetBits(GPIOF,GPIO_Pin_6)
|
||||
|
||||
#define DM9000_ID 0x90000A46 /* DM9000 ID */
|
||||
#define DM9000_PKT_MAX 1536 /* Received packet max size */
|
||||
#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
|
||||
|
@ -6,8 +6,6 @@
|
||||
|
||||
#define MAX_ADDR_LEN 6
|
||||
|
||||
// #define CSACTIVE GPIO_ResetBits(GPIOB, GPIO_Pin_12);
|
||||
// #define CSPASSIVE GPIO_SetBits(GPIOB, GPIO_Pin_12);
|
||||
#define CSACTIVE GPIOB->BRR = GPIO_Pin_12;
|
||||
#define CSPASSIVE GPIOB->BSRR = GPIO_Pin_12;
|
||||
|
||||
@ -24,7 +22,7 @@ static struct net_device enc28j60_dev_entry;
|
||||
static struct net_device *enc28j60_dev =&enc28j60_dev_entry;
|
||||
static rt_uint8_t Enc28j60Bank;
|
||||
static rt_uint16_t NextPacketPtr;
|
||||
static struct rt_semaphore tx_sem;
|
||||
static struct rt_semaphore lock_sem;
|
||||
|
||||
void _delay_us(rt_uint32_t us)
|
||||
{
|
||||
@ -172,6 +170,28 @@ void enc28j60_clkout(rt_uint8_t clk)
|
||||
spi_write(ECOCON, clk & 0x7);
|
||||
}
|
||||
|
||||
rt_inline rt_uint32_t enc28j60_interrupt_disable()
|
||||
{
|
||||
rt_uint32_t level;
|
||||
|
||||
/* switch to bank 0 */
|
||||
enc28j60_set_bank(EIE);
|
||||
|
||||
/* get last interrupt level */
|
||||
level = spi_read(EIE);
|
||||
/* disable interrutps */
|
||||
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIE, level);
|
||||
|
||||
return level;
|
||||
}
|
||||
|
||||
rt_inline void enc28j60_interrupt_enable(rt_uint32_t level)
|
||||
{
|
||||
/* switch to bank 0 */
|
||||
enc28j60_set_bank(EIE);
|
||||
spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, level);
|
||||
}
|
||||
|
||||
/*
|
||||
* Access the PHY to determine link status
|
||||
*/
|
||||
@ -195,8 +215,6 @@ static rt_bool_t enc28j60_check_link_status()
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
/*
|
||||
* Debug routine to dump useful register contents
|
||||
*/
|
||||
@ -223,6 +241,8 @@ static void enc28j60(void)
|
||||
(spi_read(ETXNDH) << 8) | spi_read(ETXNDL),
|
||||
spi_read(MACLCON1), spi_read(MACLCON2), spi_read(MAPHSUP));
|
||||
}
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT(enc28j60, dump enc28j60 registers);
|
||||
#endif
|
||||
|
||||
@ -251,10 +271,8 @@ void enc28j60_isr()
|
||||
pk_counter = spi_read(EPKTCNT);
|
||||
if (pk_counter)
|
||||
{
|
||||
rt_err_t result;
|
||||
/* a frame has been received */
|
||||
result = eth_device_ready((struct eth_device*)&(enc28j60_dev->parent));
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
eth_device_ready((struct eth_device*)&(enc28j60_dev->parent));
|
||||
|
||||
// switch to bank 0
|
||||
enc28j60_set_bank(EIE);
|
||||
@ -292,11 +310,9 @@ void enc28j60_isr()
|
||||
|
||||
if (eir & EIR_TXIF)
|
||||
{
|
||||
/* A frame has been transmitted. */
|
||||
enc28j60_set_bank(EIR);
|
||||
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXIF);
|
||||
|
||||
/* A frame has been transmitted. */
|
||||
rt_sem_release(&tx_sem);
|
||||
}
|
||||
|
||||
/* TX Error handler */
|
||||
@ -412,8 +428,6 @@ rt_err_t enc28j60_init(rt_device_t dev)
|
||||
enc28j60_phy_write(PHLCON, 0xD76); //0x476
|
||||
delay_ms(20);
|
||||
|
||||
// rt_kprintf("enc28j60 init ok!\n");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
@ -470,11 +484,14 @@ rt_err_t enc28j60_tx( rt_device_t dev, struct pbuf* p)
|
||||
struct pbuf* q;
|
||||
rt_uint32_t len;
|
||||
rt_uint8_t* ptr;
|
||||
rt_uint32_t level;
|
||||
|
||||
// rt_kprintf("tx pbuf: 0x%08x, total len %d\n", p, p->tot_len);
|
||||
|
||||
/* lock tx operation */
|
||||
rt_sem_take(&tx_sem, RT_WAITING_FOREVER);
|
||||
/* lock enc28j60 */
|
||||
rt_sem_take(&lock_sem, RT_WAITING_FOREVER);
|
||||
/* disable enc28j60 interrupt */
|
||||
level = enc28j60_interrupt_disable();
|
||||
|
||||
// Set the write pointer to start of transmit buffer area
|
||||
spi_write(EWRPTL, TXSTART_INIT&0xFF);
|
||||
@ -515,7 +532,9 @@ rt_err_t enc28j60_tx( rt_device_t dev, struct pbuf* p)
|
||||
spi_write_op(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
|
||||
}
|
||||
|
||||
//rt_kprintf("tx ok\n");
|
||||
/* enable enc28j60 interrupt */
|
||||
enc28j60_interrupt_enable(level);
|
||||
rt_sem_release(&lock_sem);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
@ -526,9 +545,15 @@ struct pbuf *enc28j60_rx(rt_device_t dev)
|
||||
rt_uint32_t len;
|
||||
rt_uint16_t rxstat;
|
||||
rt_uint32_t pk_counter;
|
||||
rt_uint32_t level;
|
||||
|
||||
p = RT_NULL;
|
||||
|
||||
/* lock enc28j60 */
|
||||
rt_sem_take(&lock_sem, RT_WAITING_FOREVER);
|
||||
/* disable enc28j60 interrupt */
|
||||
level = enc28j60_interrupt_disable();
|
||||
|
||||
pk_counter = spi_read(EPKTCNT);
|
||||
if (pk_counter)
|
||||
{
|
||||
@ -604,23 +629,18 @@ struct pbuf *enc28j60_rx(rt_device_t dev)
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_uint32_t level;
|
||||
/* lock enc28j60 */
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
// switch to bank 0
|
||||
enc28j60_set_bank(EIE);
|
||||
// enable interrutps
|
||||
spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE);
|
||||
// switch to bank 0
|
||||
enc28j60_set_bank(ECON1);
|
||||
// enable packet reception
|
||||
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
level |= EIE_PKTIE;
|
||||
}
|
||||
|
||||
/* enable enc28j60 interrupt */
|
||||
enc28j60_interrupt_enable(level);
|
||||
rt_sem_release(&lock_sem);
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
@ -656,7 +676,7 @@ static void GPIO_Configuration()
|
||||
/* configure PB0 as external interrupt */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
/* Configure SPI2 pins: SCK, MISO and MOSI ----------------------------*/
|
||||
@ -699,25 +719,8 @@ static void SetupSPI (void)
|
||||
SPI_Cmd(SPI2, ENABLE);
|
||||
}
|
||||
|
||||
static rt_timer_t enc28j60_timer;
|
||||
void rt_hw_enc28j60_timeout(void* parameter)
|
||||
void rt_hw_enc28j60_init()
|
||||
{
|
||||
// switch to bank 0
|
||||
enc28j60_set_bank(EIE);
|
||||
// enable interrutps
|
||||
spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE);
|
||||
// switch to bank 0
|
||||
enc28j60_set_bank(ECON1);
|
||||
// enable packet reception
|
||||
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
|
||||
|
||||
enc28j60_isr();
|
||||
}
|
||||
|
||||
int rt_hw_enc28j60_init()
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
/* configuration PB5 as INT */
|
||||
RCC_Configuration();
|
||||
NVIC_Configuration();
|
||||
@ -742,16 +745,7 @@ int rt_hw_enc28j60_init()
|
||||
enc28j60_dev_entry.dev_addr[4] = 0x45;
|
||||
enc28j60_dev_entry.dev_addr[5] = 0x5e;
|
||||
|
||||
rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO);
|
||||
rt_sem_init(&lock_sem, "lock", 1, RT_IPC_FLAG_FIFO);
|
||||
|
||||
result = eth_device_init(&(enc28j60_dev->parent), "E0");
|
||||
|
||||
/* workaround for enc28j60 interrupt */
|
||||
enc28j60_timer = rt_timer_create("etimer",
|
||||
rt_hw_enc28j60_timeout, RT_NULL,
|
||||
50, RT_TIMER_FLAG_PERIODIC);
|
||||
if (enc28j60_timer != RT_NULL)
|
||||
rt_timer_start(enc28j60_timer);
|
||||
|
||||
return RT_EOK;
|
||||
eth_device_init(&(enc28j60_dev->parent), "e0");
|
||||
}
|
||||
|
@ -296,6 +296,6 @@
|
||||
// max frame length which the conroller will accept:
|
||||
#define MAX_FRAMELEN 1518
|
||||
|
||||
int rt_hw_enc28j60_init(void);
|
||||
void rt_hw_enc28j60_init(void);
|
||||
|
||||
#endif
|
||||
|
@ -18,12 +18,14 @@ File 1,1,<.\application.c><application.c>
|
||||
File 1,1,<.\startup.c><startup.c>
|
||||
File 1,1,<.\led.c><led.c>
|
||||
File 1,1,<.\usart.c><usart.c>
|
||||
File 1,1,<.\enc28j60.c><enc28j60.c>
|
||||
File 1,1,<.\sdcard.c><sdcard.c>
|
||||
File 1,1,<.\msd.c><msd.c>
|
||||
File 1,1,<.\enc28j60.c><enc28j60.c>
|
||||
File 1,1,<.\dm9000a.c><dm9000a.c>
|
||||
File 1,1,<.\rtc.c><rtc.c>
|
||||
File 1,5,<.\rtconfig.h><rtconfig.h>
|
||||
File 1,5,<.\board.h><board.h>
|
||||
File 1,1,<..\..\net\apps\tcpecho.c><tcpecho.c>
|
||||
File 2,1,<.\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c>
|
||||
File 2,1,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c><stm32f10x_adc.c>
|
||||
File 2,1,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c><stm32f10x_bkp.c>
|
||||
|
@ -1869,6 +1869,9 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\board.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\dm9000a.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\enc28j60.c</name>
|
||||
</file>
|
||||
|
@ -17,13 +17,12 @@
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_DFS
|
||||
/* dfs init */
|
||||
#include <dfs_init.h>
|
||||
/* dfs filesystem:FAT filesystem init */
|
||||
#include <dfs_fat.h>
|
||||
/* dfs filesystem:EFS filesystem init */
|
||||
#include <dfs_efs.h>
|
||||
/* dfs Filesystem APIs */
|
||||
@ -33,6 +32,7 @@
|
||||
#ifdef RT_USING_LWIP
|
||||
#include <lwip/sys.h>
|
||||
#include <lwip/api.h>
|
||||
#include <netif/ethernetif.h>
|
||||
#endif
|
||||
|
||||
void rt_init_thread_entry(void* parameter)
|
||||
@ -42,6 +42,8 @@ void rt_init_thread_entry(void* parameter)
|
||||
{
|
||||
/* init the device filesystem */
|
||||
dfs_init();
|
||||
|
||||
#ifdef RT_USING_DFS_EFSL
|
||||
/* init the efsl filesystam*/
|
||||
efsl_init();
|
||||
|
||||
@ -52,7 +54,18 @@ void rt_init_thread_entry(void* parameter)
|
||||
}
|
||||
else
|
||||
rt_kprintf("File System initialzation failed!\n");
|
||||
#elif defined(RT_USING_DFS_ELMFAT)
|
||||
/* init the elm chan FatFs filesystam*/
|
||||
elm_init();
|
||||
|
||||
/* mount sd card fat partition 1 as root directory */
|
||||
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
|
||||
{
|
||||
rt_kprintf("File System initialized!\n");
|
||||
}
|
||||
else
|
||||
rt_kprintf("File System initialzation failed!\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -60,6 +73,18 @@ void rt_init_thread_entry(void* parameter)
|
||||
#ifdef RT_USING_LWIP
|
||||
{
|
||||
extern void lwip_sys_init(void);
|
||||
#ifdef RT_USING_LWIP
|
||||
eth_system_device_init();
|
||||
|
||||
/* register ethernetif device */
|
||||
#if STM32_ETH_IF == 0
|
||||
rt_hw_enc28j60_init();
|
||||
#elif STM32_ETH_IF == 1
|
||||
rt_hw_dm9000_init();
|
||||
#endif
|
||||
/* re-init device driver */
|
||||
rt_device_init_all();
|
||||
#endif
|
||||
|
||||
/* init lwip system */
|
||||
lwip_sys_init();
|
||||
|
65
bsp/stm3210/project_full/board.h
Normal file
65
bsp/stm3210/project_full/board.h
Normal file
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* File : board.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-09-22 Bernard add board.h to this bsp
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
/* board configuration */
|
||||
// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
|
||||
// <i>Default: 1
|
||||
#define STM32_USE_SDIO 1
|
||||
|
||||
/* whether use board external SRAM memory */
|
||||
// <e>Use external SRAM memory on the board
|
||||
// <i>Enable External SRAM memory
|
||||
#define STM32_EXT_SRAM 0
|
||||
// <o>Begin Address of External SRAM
|
||||
// <i>Default: 0x68000000
|
||||
#define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */
|
||||
// <o>End Address of External SRAM
|
||||
// <i>Default: 0x68080000
|
||||
#define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */
|
||||
// </e>
|
||||
|
||||
// <o> Internal SRAM memory size[Kbytes] <8-64>
|
||||
// <i>Default: 64
|
||||
#define STM32_SRAM_SIZE 64
|
||||
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
|
||||
|
||||
// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
|
||||
// <i>Default: 1
|
||||
#define STM32_CONSOLE_USART 1
|
||||
|
||||
// <o> Ethernet Interface: <0=> Microchip ENC28J60 <1=> Davicom DM9000A
|
||||
// <i>Default: 0
|
||||
#define STM32_ETH_IF 0
|
||||
|
||||
void rt_hw_board_led_on(int n);
|
||||
void rt_hw_board_led_off(int n);
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
void rt_hw_usart_init(void);
|
||||
|
||||
/* SD Card init function */
|
||||
void rt_hw_sdcard_init(void);
|
||||
void rt_hw_msd_init(void);
|
||||
|
||||
/* ETH interface init function */
|
||||
void rt_hw_enc28j60_init(void);
|
||||
void rt_hw_dm9000_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
@ -18,12 +18,14 @@ File 1,1,<.\application.c><application.c>
|
||||
File 1,1,<.\startup.c><startup.c>
|
||||
File 1,1,<.\led.c><led.c>
|
||||
File 1,1,<.\usart.c><usart.c>
|
||||
File 1,1,<.\enc28j60.c><enc28j60.c>
|
||||
File 1,1,<.\sdcard.c><sdcard.c>
|
||||
File 1,1,<.\msd.c><msd.c>
|
||||
File 1,1,<.\enc28j60.c><enc28j60.c>
|
||||
File 1,1,<.\dm9000a.c><dm9000a.c>
|
||||
File 1,1,<.\rtc.c><rtc.c>
|
||||
File 1,5,<.\rtconfig.h><rtconfig.h>
|
||||
File 1,5,<.\board.h><board.h>
|
||||
File 1,1,<..\..\net\apps\tcpecho.c><tcpecho.c>
|
||||
File 2,1,<.\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c>
|
||||
File 2,1,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c><stm32f10x_adc.c>
|
||||
File 2,1,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c><stm32f10x_bkp.c>
|
||||
@ -216,7 +218,7 @@ Options 1,0,0 // Target 'RT-Thread STM32'
|
||||
ADSLDMC (--keep __fsym_* --keep __vsym_*)
|
||||
ADSLDIF ()
|
||||
ADSLDDW ()
|
||||
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE)
|
||||
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F107xCSchedule)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F107xC)
|
||||
OPTDBG 49150,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
|
||||
FLASH1 { 9,0,0,0,1,0,0,0,5,16,0,0,0,0,0,0,0,0,0,0 }
|
||||
FLASH2 (Segger\JL2CM3.dll)
|
||||
|
@ -1869,6 +1869,9 @@
|
||||
<file>
|
||||
<name>$PROJ_DIR$\board.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\dm9000a.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\enc28j60.c</name>
|
||||
</file>
|
||||
|
@ -25,11 +25,6 @@
|
||||
|
||||
/*@{*/
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
#include "enc28j60.h"
|
||||
#include <netif/ethernetif.h>
|
||||
#endif
|
||||
|
||||
extern int rt_application_init(void);
|
||||
#ifdef RT_USING_FINSH
|
||||
extern void finsh_system_init(void);
|
||||
@ -111,13 +106,6 @@ void rtthread_startup(void)
|
||||
rt_hw_msd_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
eth_system_device_init();
|
||||
|
||||
/* register ethernetif device */
|
||||
rt_hw_enc28j60_init();
|
||||
#endif
|
||||
|
||||
rt_hw_rtc_init();
|
||||
|
||||
/* init all device */
|
||||
|
@ -22,6 +22,7 @@
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_it.h"
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
/** @addtogroup Template_Project
|
||||
@ -272,6 +273,8 @@ void SDIO_IRQHandler(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
#if (STM32_ETH_IF == 0)
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTI0_IRQHandler
|
||||
* Description : This function handles External interrupt Line 0 request.
|
||||
@ -281,7 +284,6 @@ void SDIO_IRQHandler(void)
|
||||
*******************************************************************************/
|
||||
void EXTI0_IRQHandler(void)
|
||||
{
|
||||
#ifdef RT_USING_LWIP
|
||||
extern void enc28j60_isr(void);
|
||||
|
||||
/* enter interrupt */
|
||||
@ -294,8 +296,34 @@ void EXTI0_IRQHandler(void)
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (STM32_ETH_IF == 1)
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTI9_5_IRQHandler
|
||||
* Description : This function handles External lines 9 to 5 interrupt request.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void EXTI9_5_IRQHandler(void)
|
||||
{
|
||||
extern void rt_dm9000_isr(void);
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_dm9000_isr();
|
||||
|
||||
/* Clear the Key Button EXTI line pending bit */
|
||||
EXTI_ClearITPendingBit(EXTI_Line7);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#endif /* end of RT_USING_LWIP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -64,7 +64,6 @@
|
||||
/* Using symbol table */
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_DEVICE_NAME "uart1"
|
||||
|
||||
/* SECTION: device filesystem */
|
||||
#define RT_USING_DFS
|
||||
|
@ -2,16 +2,19 @@
|
||||
RT_USING_FINSH = True
|
||||
RT_USING_DFS = True
|
||||
RT_USING_DFS_YAFFS2 = False
|
||||
RT_USING_DFS_EFSL = True
|
||||
RT_USING_DFS_EFSL = False
|
||||
RT_USING_DFS_ELMFAT = True
|
||||
RT_USING_LWIP = True
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='stm32'
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = 'd:/SourceryGCC/bin'
|
||||
#PLATFORM = 'armcc'
|
||||
#EXEC_PATH = 'C:/Keil'
|
||||
#PLATFORM = 'gcc'
|
||||
#EXEC_PATH = 'd:/codesourcery/bin'
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'e:/Keil'
|
||||
#PLATFORM = 'iar'
|
||||
#EXEC_PATH = 'E:/Program Files/IAR Systems/Embedded Workbench 5.4/'
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
@ -21,7 +24,7 @@ if PLATFORM == 'gcc':
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
TARGET_EXT = 'axf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
@ -29,7 +32,7 @@ if PLATFORM == 'gcc':
|
||||
DEVICE = ' -mcpu=cortex-m3 -mthumb'
|
||||
CFLAGS = DEVICE + ' -DRT_USING_MINILIBC'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=main.elf.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
@ -74,11 +77,18 @@ elif PLATFORM == 'armcc':
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
CC = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' --cpu DARMSTM --thumb'
|
||||
|
||||
CFLAGS = ''
|
||||
AFLAGS = ''
|
||||
LFLAGS = ''
|
||||
LFLAGS = ' --config stm32f10x_flash.icf'
|
||||
|
||||
EXEC_PATH += '/arm/bin/'
|
||||
RT_USING_MINILIBC = False
|
||||
POST_ACTION = ''
|
||||
|
@ -23,6 +23,8 @@
|
||||
#include <stm32f10x_dma.h>
|
||||
#include <stm32f10x_sdio.h>
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Examples
|
||||
* @{
|
||||
*/
|
||||
@ -69,6 +71,7 @@
|
||||
#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)
|
||||
#define SD_STD_CAPACITY ((uint32_t)0x00000000)
|
||||
#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)
|
||||
#define SD_VOLTAGE_WINDOW_MMC ((uint32_t)0x80FF8000)
|
||||
|
||||
#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
|
||||
#define SD_ALLZERO ((uint32_t)0x00000000)
|
||||
@ -320,10 +323,42 @@ SD_Error SD_PowerON(void)
|
||||
}
|
||||
|
||||
}/* else MMC Card */
|
||||
else
|
||||
{
|
||||
CardType = SDIO_MULTIMEDIA_CARD;
|
||||
|
||||
/* Send CMD1 SEND_OP_COND with Argument 0x80FF8000 */
|
||||
while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
|
||||
{
|
||||
|
||||
/* SEND CMD55 APP_CMD with RCA as 0 */
|
||||
SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_MMC;
|
||||
SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_OP_COND;
|
||||
SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
|
||||
SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
|
||||
SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
|
||||
SDIO_SendCommand(&SDIO_CmdInitStructure);
|
||||
|
||||
errorstatus = CmdResp3Error();
|
||||
if (errorstatus != SD_OK)
|
||||
{
|
||||
return(errorstatus);
|
||||
}
|
||||
|
||||
response = SDIO_GetResponse(SDIO_RESP1);
|
||||
validvoltage = (bool) (((response >> 31) == 1) ? 1 : 0);
|
||||
count++;
|
||||
}
|
||||
if (count >= SD_MAX_VOLT_TRIAL)
|
||||
{
|
||||
errorstatus = SD_INVALID_VOLTRANGE;
|
||||
return(errorstatus);
|
||||
}
|
||||
}
|
||||
|
||||
return(SD_OK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns the SDIO output signals off.
|
||||
* @param None
|
||||
@ -397,6 +432,24 @@ SD_Error SD_InitializeCards(void)
|
||||
return(errorstatus);
|
||||
}
|
||||
}
|
||||
if (SDIO_MULTIMEDIA_CARD == CardType)
|
||||
{
|
||||
/* Send CMD3 SET_REL_ADDR with argument 0 */
|
||||
/* SD Card publishes its RCA. */
|
||||
SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16);
|
||||
SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_REL_ADDR;
|
||||
SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
|
||||
SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
|
||||
SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
|
||||
SDIO_SendCommand(&SDIO_CmdInitStructure);
|
||||
|
||||
errorstatus = CmdResp2Error();
|
||||
|
||||
if (SD_OK != errorstatus)
|
||||
{
|
||||
return(errorstatus);
|
||||
}
|
||||
}
|
||||
|
||||
if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
|
||||
{
|
||||
@ -905,11 +958,29 @@ SD_Error SD_ReadBlock(uint32_t addr, uint32_t *readbuff, uint16_t BlockSize)
|
||||
}
|
||||
else if (DeviceMode == SD_DMA_MODE)
|
||||
{
|
||||
int cnt = 0;
|
||||
SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
|
||||
SDIO_DMACmd(ENABLE);
|
||||
DMA_RxConfiguration(readbuff, BlockSize);
|
||||
while (DMA_GetFlagStatus(DMA2_FLAG_TC4) == RESET)
|
||||
{}
|
||||
{
|
||||
cnt ++;
|
||||
if (cnt > 10 * 50000)
|
||||
{
|
||||
rt_kprintf("DMA flag 0x%08x\n", DMA_GetFlagStatus(DMA2_FLAG_TC4));
|
||||
/* Clear all DPSM configuration */
|
||||
SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
|
||||
SDIO_DataInitStructure.SDIO_DataLength = 0;
|
||||
SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||
SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||
SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||
SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Disable;
|
||||
SDIO_DataConfig(&SDIO_DataInitStructure);
|
||||
SDIO_DMACmd(DISABLE);
|
||||
errorstatus = SD_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return(errorstatus);
|
||||
}
|
||||
@ -2915,6 +2986,7 @@ static void DMA_RxConfiguration(uint32_t *BufferDST, uint32_t BufferSize)
|
||||
static struct rt_device sdcard_device;
|
||||
static SD_CardInfo SDCardInfo;
|
||||
static struct dfs_partition part;
|
||||
static struct rt_semaphore sd_lock;
|
||||
|
||||
/* RT-Thread Device Driver Interface */
|
||||
static rt_err_t rt_sdcard_init(rt_device_t dev)
|
||||
@ -2927,6 +2999,11 @@ static rt_err_t rt_sdcard_init(rt_device_t dev)
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
|
||||
{
|
||||
rt_kprintf("init sd lock semaphore failed\n");
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
@ -2946,26 +3023,32 @@ static rt_err_t rt_sdcard_close(rt_device_t dev)
|
||||
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
SD_Error status;
|
||||
rt_uint32_t i;
|
||||
rt_uint32_t i, retry;
|
||||
|
||||
// rt_kprintf("read: 0x%x, size %d\n", pos, size);
|
||||
|
||||
rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
|
||||
retry = 3;
|
||||
/* read all sectors */
|
||||
for (i = 0; i < size / SECTOR_SIZE; i ++)
|
||||
{
|
||||
__retry:
|
||||
status = SD_ReadBlock((part.offset + i)* SECTOR_SIZE + pos,
|
||||
(uint32_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE),
|
||||
SECTOR_SIZE);
|
||||
if (status != SD_OK)
|
||||
{
|
||||
rt_kprintf("sd card read failed\n");
|
||||
return 0;
|
||||
-- retry;
|
||||
if (retry != 0) goto __retry;
|
||||
else break;
|
||||
}
|
||||
}
|
||||
|
||||
rt_sem_release(&sd_lock);
|
||||
|
||||
if (status == SD_OK) return size;
|
||||
|
||||
rt_kprintf("read failed: %d\n", status);
|
||||
rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -2976,7 +3059,9 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
|
||||
|
||||
// rt_kprintf("write: 0x%x, size %d\n", pos, size);
|
||||
|
||||
/* read all sectors */
|
||||
rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
|
||||
|
||||
/* write all sectors */
|
||||
for (i = 0; i < size / SECTOR_SIZE; i ++)
|
||||
{
|
||||
status = SD_WriteBlock((part.offset + i)* SECTOR_SIZE + pos,
|
||||
@ -2985,13 +3070,14 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
|
||||
if (status != SD_OK)
|
||||
{
|
||||
rt_kprintf("sd card write failed\n");
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
rt_sem_release(&sd_lock);
|
||||
if (status == SD_OK) return size;
|
||||
|
||||
rt_kprintf("write failed: %d\n", status);
|
||||
rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -3002,18 +3088,19 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
|
||||
void rt_hw_sdcard_init()
|
||||
{
|
||||
if (SD_Init())
|
||||
if ( SD_Init() == SD_OK )
|
||||
{
|
||||
SD_Error status;
|
||||
rt_uint8_t *sector;
|
||||
|
||||
SD_EnableWideBusOperation(SDIO_BusWide_1b);
|
||||
|
||||
status = SD_GetCardInfo(&SDCardInfo);
|
||||
if (status != SD_OK) goto __return;
|
||||
|
||||
status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16));
|
||||
if (status != SD_OK) goto __return;
|
||||
|
||||
SD_EnableWideBusOperation(SDIO_BusWide_4b);
|
||||
SD_SetDeviceMode(SD_DMA_MODE);
|
||||
|
||||
/* get the first sector to read partition table */
|
||||
|
@ -25,22 +25,12 @@
|
||||
|
||||
/*@{*/
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
#ifdef STM32F10X_CL
|
||||
extern void rt_hw_stm32_eth_init(void);
|
||||
#else
|
||||
#include "enc28j60.h"
|
||||
#endif
|
||||
#include <netif/ethernetif.h>
|
||||
#endif
|
||||
|
||||
extern int rt_application_init(void);
|
||||
#ifdef RT_USING_FINSH
|
||||
extern void finsh_system_init(void);
|
||||
extern void finsh_set_device(const char* device);
|
||||
#endif
|
||||
|
||||
/* bss end definitions for heap init */
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#elif __ICCARM__
|
||||
@ -109,25 +99,11 @@ void rtthread_startup(void)
|
||||
|
||||
/* init hardware serial device */
|
||||
rt_hw_usart_init();
|
||||
|
||||
#ifdef RT_USING_DFS
|
||||
/* init sdcard driver */
|
||||
#if STM32_USE_SDIO
|
||||
rt_hw_sdcard_init();
|
||||
#else
|
||||
rt_hw_msd_init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
eth_system_device_init();
|
||||
|
||||
/* register ethernetif device */
|
||||
#ifdef STM32F10X_CL
|
||||
rt_hw_stm32_eth_init();
|
||||
#else
|
||||
rt_hw_enc28j60_init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
rt_hw_rtc_init();
|
||||
@ -141,7 +117,7 @@ void rtthread_startup(void)
|
||||
#ifdef RT_USING_FINSH
|
||||
/* init finsh */
|
||||
finsh_system_init();
|
||||
finsh_set_device(FINSH_DEVICE_NAME);
|
||||
finsh_set_device("uart1");
|
||||
#endif
|
||||
|
||||
/* init idle thread */
|
||||
|
@ -22,8 +22,8 @@
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_it.h"
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
|
||||
/** @addtogroup Template_Project
|
||||
* @{
|
||||
@ -259,7 +259,7 @@ void USART3_IRQHandler(void)
|
||||
*******************************************************************************/
|
||||
void SDIO_IRQHandler(void)
|
||||
{
|
||||
#if defined(RT_USING_DFS) && STM32_USE_SDIO
|
||||
#ifdef RT_USING_DFS
|
||||
extern int SD_ProcessIRQSrc(void);
|
||||
|
||||
/* enter interrupt */
|
||||
@ -273,6 +273,8 @@ void SDIO_IRQHandler(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
#if (STM32_ETH_IF == 0)
|
||||
/*******************************************************************************
|
||||
* Function Name : EXTI0_IRQHandler
|
||||
* Description : This function handles External interrupt Line 0 request.
|
||||
@ -282,7 +284,6 @@ void SDIO_IRQHandler(void)
|
||||
*******************************************************************************/
|
||||
void EXTI0_IRQHandler(void)
|
||||
{
|
||||
#if defined(RT_USING_LWIP) && !defined(STM32F10X_CL)
|
||||
extern void enc28j60_isr(void);
|
||||
|
||||
/* enter interrupt */
|
||||
@ -295,30 +296,34 @@ void EXTI0_IRQHandler(void)
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (STM32_ETH_IF == 1)
|
||||
/*******************************************************************************
|
||||
* Function Name : ETH_IRQHandler
|
||||
* Description : This function handles ETH interrupt request.
|
||||
* Function Name : EXTI9_5_IRQHandler
|
||||
* Description : This function handles External lines 9 to 5 interrupt request.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ETH_IRQHandler(void)
|
||||
void EXTI9_5_IRQHandler(void)
|
||||
{
|
||||
#if defined(RT_USING_LWIP) && defined(STM32F10X_CL)
|
||||
extern void rt_hw_stm32_eth_isr(void);
|
||||
extern void rt_dm9000_isr(void);
|
||||
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_hw_stm32_eth_isr();
|
||||
rt_dm9000_isr();
|
||||
|
||||
/* Clear the Key Button EXTI line pending bit */
|
||||
EXTI_ClearITPendingBit(EXTI_Line7);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#endif /* end of RT_USING_LWIP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -38,7 +38,7 @@ struct stm32_serial_device uart2 =
|
||||
{
|
||||
USART2,
|
||||
&uart2_int_rx,
|
||||
&uart2_dma_rx,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL
|
||||
};
|
||||
@ -180,12 +180,6 @@ static void NVIC_Configuration(void)
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
/* Enable the DMA1 Channel6 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel6_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART3
|
||||
@ -205,7 +199,7 @@ static void NVIC_Configuration(void)
|
||||
|
||||
static void DMA_Configuration(void)
|
||||
{
|
||||
#if defined(RT_USING_UART2) || defined (RT_USING_UART3)
|
||||
#if defined (RT_USING_UART3)
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
|
||||
/* fill init structure */
|
||||
@ -216,21 +210,7 @@ static void DMA_Configuration(void)
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
|
||||
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART2
|
||||
/* DMA1 Channel4 (triggered by USART2 Rx event) Config */
|
||||
DMA_DeInit(UART2_RX_DMA);
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = USART2_DR_Base;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0;
|
||||
DMA_InitStructure.DMA_BufferSize = 0;
|
||||
DMA_Init(UART2_RX_DMA, &DMA_InitStructure);
|
||||
DMA_ITConfig(UART2_RX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE);
|
||||
DMA_ClearFlag(DMA1_FLAG_TC4);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART3
|
||||
/* DMA1 Channel5 (triggered by USART3 Tx event) Config */
|
||||
DMA_DeInit(UART3_TX_DMA);
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = USART3_DR_Base;
|
||||
@ -298,15 +278,13 @@ void rt_hw_usart_init()
|
||||
USART_Init(USART2, &USART_InitStructure);
|
||||
USART_ClockInit(USART2, &USART_ClockInitStructure);
|
||||
|
||||
uart2_dma_rx.dma_channel= UART2_RX_DMA;
|
||||
|
||||
/* register uart2 */
|
||||
rt_hw_serial_register(&uart2_device, "uart2",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_RX,
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
&uart2);
|
||||
|
||||
/* Enable USART2 DMA Rx request */
|
||||
USART_DMACmd(USART2, USART_DMAReq_Rx , ENABLE);
|
||||
USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART3
|
||||
|
Loading…
x
Reference in New Issue
Block a user