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Merge pull request #4294 from Michael0066/ls1b-dev 

bsp:ls1b:rework uart driver and fix some bugs to make it work. tested on ls1b dev board
This commit is contained in:
Bernard Xiong 2021-02-18 10:26:22 +08:00 committed by GitHub
parent 17ee3d2c08 97de1e7407
commit 6420c27791
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
21 changed files with 1989 additions and 396 deletions
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20
bsp/ls1bdev/Kconfig
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@ -16,7 +16,6 @@ config PKGS_DIR
default "packages"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/libcpu/mips/common/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_LS1B
@ -25,16 +24,33 @@ config SOC_LS1B
select RT_USING_USER_MAIN
default y
config RT_MEM_SIZE
int "Memory Size (MByte)"
default 256
config RT_OSC_CLK
int "Oscillator Clock (Hz)"
default 25000000
if RT_USING_SERIAL
config RT_USING_UART0
bool "Using RT_USING_UART0"
default y
default n
config RT_USING_UART1
bool "Using RT_USING_UART1"
default n
config RT_USING_UART2
bool "Using RT_USING_UART2"
default n
config RT_USING_UART3
bool "Using RT_USING_UART3"
default n
config RT_USING_UART4
bool "Using RT_USING_UART4"
default n
config RT_USING_UART5
bool "Using RT_USING_UART5"
default y
config RT_UART_RX_BUFFER_SIZE
int "The rx buffer size"

4
bsp/ls1bdev/drivers/board.c
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@ -19,7 +19,7 @@
#include <mips_fpu.h>
#include "board.h"
#include "uart.h"
#include "drv_uart.h"
#include "ls1b.h"
#ifdef RT_USING_RTGUI
@ -84,6 +84,6 @@ void rt_hw_board_init(void)
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
rt_kprintf("current sr: 0x%08x\n", read_c0_status());
}
/*@}*/

2
bsp/ls1bdev/drivers/board.h
View File

@ -19,7 +19,7 @@
void rt_hw_board_init(void);
/* 64M SDRAM */
#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
#define RT_HW_HEAP_END (0x80000000 + RT_MEM_SIZE * 1024 * 1024)
#define CPU_HZ (125 * 1000000)
#endif

222
bsp/ls1bdev/drivers/drv_uart.c Normal file
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@ -0,0 +1,222 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-08 zhuangwei the first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "drv_uart.h"
#include "ls1b_pin.h"
#include "ls1b_uart.h"
/* STM32 uart driver */
struct rt_uart_ls1b
{
ls1b_uart_t UARTx;
rt_uint32_t IRQ;
};
static rt_err_t ls1b_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct rt_uart_ls1b *uart_dev = RT_NULL;
ls1b_uart_info_t uart_info = {0};
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
// 初始化串口
uart_info.UARTx = uart_dev->UARTx;
uart_info.baudrate = cfg->baud_rate;
uart_info.rx_enable = TRUE;
uart_init(&uart_info);
return RT_EOK;
}
static rt_err_t ls1b_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct rt_uart_ls1b *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */
rt_hw_interrupt_mask(uart_dev->IRQ);
break;
case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */
rt_hw_interrupt_umask(uart_dev->IRQ);
break;
default:
break;
}
return RT_EOK;
}
static int ls1b_uart_putc(struct rt_serial_device *serial, char c)
{
struct rt_uart_ls1b *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
uart_putc(uart_dev->UARTx, c);
return 1;
}
static int ls1b_uart_getc(struct rt_serial_device *serial)
{
struct rt_uart_ls1b *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
void *uart_base = uart_get_base(uart_dev->UARTx);
if (LSR_RXRDY & reg_read_8(uart_base + LS1B_UART_LSR_OFFSET))
{
return reg_read_8(uart_base + LS1B_UART_DAT_OFFSET);
}
return -1;
}
/* UART interrupt handler */
static void uart_irq_handler(int vector, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device *)param;
struct rt_uart_ls1b *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
void *uart_base = uart_get_base(uart_dev->UARTx);
unsigned char iir = reg_read_8(uart_base + LS1B_UART_IIR_OFFSET);
// 判断是否为接收超时或接收到有效数据
if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
{
rt_interrupt_enter();
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
rt_interrupt_leave();
}
}
static const struct rt_uart_ops ls1b_uart_ops =
{
ls1b_uart_configure,
ls1b_uart_control,
ls1b_uart_putc,
ls1b_uart_getc,
};
#if defined(RT_USING_UART1)
struct rt_uart_ls1b uart1 =
{
LS1B_UART1,
LS1B_UART1_IRQ,
};
struct rt_serial_device serial1;
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART2)
struct rt_uart_ls1b uart2 =
{
LS1B_UART2,
LS1B_UART2_IRQ,
};
struct rt_serial_device serial2;
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
struct rt_uart_ls1b uart3 =
{
LS1B_UART3,
LS1B_UART3_IRQ,
};
struct rt_serial_device serial3;
#endif /* RT_USING_UART3 */
#if defined(RT_USING_UART4)
struct rt_uart_ls1b uart4 =
{
LS1B_UART4,
LS1B_UART4_IRQ,
};
struct rt_serial_device serial4;
#endif /* RT_USING_UART4 */
#if defined(RT_USING_UART5)
struct rt_uart_ls1b uart5 =
{
LS1B_UART5,
LS1B_UART5_IRQ,
};
struct rt_serial_device serial5;
#endif /* RT_USING_UART5 */
void rt_hw_uart_init(void)
{
struct rt_uart_ls1b *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART5
uart = &uart5;
serial5.ops = &ls1b_uart_ops;
serial5.config = config;
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5");
/* register UART5 device */
rt_hw_serial_register(&serial5,
"uart5",
//RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART5 */
#ifdef RT_USING_UART2
uart = &uart2;
serial2.ops = &ls1b_uart_ops;
serial2.config = config;
pin_set_purpose(36, PIN_PURPOSE_OTHER);
pin_set_purpose(37, PIN_PURPOSE_OTHER);
pin_set_remap(36, PIN_REMAP_SECOND);
pin_set_remap(37, PIN_REMAP_SECOND);
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial2, "UART2");
/* register UART2 device */
rt_hw_serial_register(&serial2,
"uart2",
//RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART2 */
}

100
bsp/ls1bdev/drivers/drv_uart.h Normal file
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@ -0,0 +1,100 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-08 zhuangwei the first version
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include "ls1b.h"
#include <rthw.h>
#define DEV_CLK 252000000 // 252MHz
#define UART_BAUDRATE 115200
#define UART0_BASE 0xBFE40000
//#define UART0_1_BASE 0xBFE41000
#define UART1_BASE 0xBFE44000
#define UART2_BASE 0xBFE48000
#define UART3_BASE 0xBFE4C000
#define UART4_BASE 0xBFE4C400
#define UART5_BASE 0xBFE4C500
#define UART6_BASE 0xBFE4C600
#define UART7_BASE 0xBFE4C700
#define UART8_BASE 0xBFE4C800
#define UART9_BASE 0xBFE4C900
#define UART10_BASE 0xBFE4Ca00
#define UART11_BASE 0xBFE4Cb00
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT HWREG8(UART0_BASE + 0x00)
#define UART0_IER HWREG8(UART0_BASE + 0x01)
#define UART0_IIR HWREG8(UART0_BASE + 0x02)
#define UART0_FCR HWREG8(UART0_BASE + 0x02)
#define UART0_LCR HWREG8(UART0_BASE + 0x03)
#define UART0_MCR HWREG8(UART0_BASE + 0x04)
#define UART0_LSR HWREG8(UART0_BASE + 0x05)
#define UART0_MSR HWREG8(UART0_BASE + 0x06)
#define UART0_LSB HWREG8(UART0_BASE + 0x00)
#define UART0_MSB HWREG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT HWREG8(UART1_BASE + 0x00)
#define UART1_IER HWREG8(UART1_BASE + 0x01)
#define UART1_IIR HWREG8(UART1_BASE + 0x02)
#define UART1_FCR HWREG8(UART1_BASE + 0x02)
#define UART1_LCR HWREG8(UART1_BASE + 0x03)
#define UART1_MCR HWREG8(UART1_BASE + 0x04)
#define UART1_LSR HWREG8(UART1_BASE + 0x05)
#define UART1_MSR HWREG8(UART1_BASE + 0x06)
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_uart_init(void);
#endif

280
bsp/ls1bdev/drivers/uart.c
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@ -1,280 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "uart.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
#if defined(RT_USING_DEVICE)
struct rt_uart_ls1b
{
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irq;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int irqno, void *param)
{
rt_ubase_t level;
rt_uint8_t isr;
struct rt_uart_ls1b *uart = &uart_device;
/* read interrupt status and clear it */
isr = UART_IIR(uart->hw_base);
isr = (isr >> 1) & 0x3;
/* receive data available */
if (isr & 0x02)
{
/* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if (uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init(rt_device_t dev)
{
rt_uint32_t baud_div;
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL);
#if 0
/* init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
/* enable UART clock */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = 0x3;
/* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE;
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_LSB(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
/* Enable UART unit, enable and clear FIFO */
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
#endif
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= UARTIER_IRXE;
/* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
rt_hw_interrupt_umask(uart->irq);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_uint8_t *ptr;
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t *)buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
char *ptr;
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL);
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size != 0)
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr++;
size--;
}
}
return (rt_size_t)ptr - (rt_size_t)buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_ls1b *uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART0)
uart->hw_base = UART0_BASE;
uart->irq = LS1B_UART0_IRQ;
#elif defined(RT_USING_UART1)
uart->hw_base = UART1_BASE;
uart->irq = LS1B_UART1_IRQ;
#elif defined(RT_USING_UART3)
uart->hw_base = UART3_BASE;
uart->irq = LS1B_UART3_IRQ;
#endif
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent, "uart0",
RT_DEVICE_FLAG_RDWR |
RT_DEVICE_FLAG_STREAM |
RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/

99
bsp/ls1bdev/drivers/uart.h
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@ -1,99 +0,0 @@
/*
* File : uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version for LS1B
*/
#ifndef __UART_H__
#define __UART_H__
#include "ls1b.h"
#include <rthw.h>
#define UART0_BASE 0xBFE40000
#define UART0_1_BASE 0xBFE41000
#define UART0_2_BASE 0xBFE42000
#define UART0_3_BASE 0xBFE43000
#define UART1_BASE 0xBFE44000
#define UART1_1_BASE 0xBFE45000
#define UART1_2_BASE 0xBFE46000
#define UART1_3_BASE 0xBFE47000
#define UART2_BASE 0xBFE48000
#define UART3_BASE 0xBFE4C000
#define UART4_BASE 0xBFE6C000
#define UART5_BASE 0xBFE7C000
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT HWREG8(UART0_BASE + 0x00)
#define UART0_IER HWREG8(UART0_BASE + 0x01)
#define UART0_IIR HWREG8(UART0_BASE + 0x02)
#define UART0_FCR HWREG8(UART0_BASE + 0x02)
#define UART0_LCR HWREG8(UART0_BASE + 0x03)
#define UART0_MCR HWREG8(UART0_BASE + 0x04)
#define UART0_LSR HWREG8(UART0_BASE + 0x05)
#define UART0_MSR HWREG8(UART0_BASE + 0x06)
#define UART0_LSB HWREG8(UART0_BASE + 0x00)
#define UART0_MSB HWREG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT HWREG8(UART1_BASE + 0x00)
#define UART1_IER HWREG8(UART1_BASE + 0x01)
#define UART1_IIR HWREG8(UART1_BASE + 0x02)
#define UART1_FCR HWREG8(UART1_BASE + 0x02)
#define UART1_LCR HWREG8(UART1_BASE + 0x03)
#define UART1_MCR HWREG8(UART1_BASE + 0x04)
#define UART1_LSR HWREG8(UART1_BASE + 0x05)
#define UART1_MSR HWREG8(UART1_BASE + 0x06)
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_uart_init(void);
#endif

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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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bsp/ls1bdev/libraries/ls1b_clock.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
#include "rtconfig.h"
#include "ls1b_regs.h"
#include "ls1b_public.h"
// 晶振的频率
#define AHB_CLK (RT_OSC_CLK)
#define APB_CLK (AHB_CLK)
#define DIV_DC_EN (0x1 << 31)
#define DIV_DC (0x1f << 26)
#define DIV_CPU_EN (0x1 << 25)
#define DIV_CPU (0x1f << 20)
#define DIV_DDR_EN (0x1 << 19)
#define DIV_DDR (0x1f << 14)
#define DIV_DC_SHIFT 26
#define DIV_CPU_SHIFT 20
#define DIV_DDR_SHIFT 14
/*
* 获取PLL频率
* @ret PLL频率
*/
unsigned long clk_get_pll_rate(void)
{
unsigned int ctrl;
unsigned long pll_rate = 0;
ctrl = reg_read_32((volatile unsigned int *)LS1B_START_FREQ);
pll_rate = (12 + (ctrl & 0x3f)) * APB_CLK / 2
+ ((ctrl >> 8) & 0x3ff) * APB_CLK / 1024 / 2;
return pll_rate;
}
/*
* 获取CPU频率
* @ret CPU频率
*/
unsigned long clk_get_cpu_rate(void)
{
unsigned long pll_rate, cpu_rate;
unsigned int ctrl;
pll_rate = clk_get_pll_rate();
ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT);
return cpu_rate;
}
/*
* 获取DDR频率
* @ret DDR频率
*/
unsigned long clk_get_ddr_rate(void)
{
unsigned long pll_rate, ddr_rate;
unsigned int ctrl;
pll_rate = clk_get_pll_rate();
ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
ddr_rate = pll_rate / ((ctrl & DIV_DDR) >> DIV_DDR_SHIFT);
return ddr_rate;
}
/*
* 获取APB频率
* @ret APB频率
*/
unsigned long clk_get_apb_rate(void)
{
return clk_get_ddr_rate() / 2;
}
/*
* 获取DC频率
* @ret DC频率
*/
unsigned long clk_get_dc_rate(void)
{
unsigned long pll_rate, dc_rate;
unsigned int ctrl;
pll_rate = clk_get_pll_rate();
ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
dc_rate = pll_rate ;
return dc_rate;
}

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
#ifndef __LOONGSON_CLOCK_H
#define __LOONGSON_CLOCK_H
/*
* 获取PLL频率
* @ret PLL频率
*/
unsigned long clk_get_pll_rate(void);
/*
* 获取CPU频率
* @ret CPU频率
*/
unsigned long clk_get_cpu_rate(void);
/*
* 获取DDR频率
* @ret DDR频率
*/
unsigned long clk_get_ddr_rate(void);
/*
* 获取APB频率
* @ret APB频率
*/
unsigned long clk_get_apb_rate(void);
/*
* 获取DC频率
* @ret DC频率
*/
unsigned long clk_get_dc_rate(void);
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
#include "ls1b_public.h"
#include "ls1b_regs.h"
#include "ls1b_gpio.h"
#include "ls1b_pin.h"
/*
* 获取指定gpio的CFG寄存器
* @gpio gpio编号
* @ret CFG寄存器
*/
volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio)
{
volatile unsigned int *gpio_cfgx = NULL; // GPIO_CFGx寄存器
unsigned int port = GPIO_GET_PORT(gpio);
switch (port)
{
case 0:
gpio_cfgx = (volatile unsigned int *)LS1B_GPIO_CFG0;
break;
case 1:
gpio_cfgx = (volatile unsigned int *)LS1B_GPIO_CFG1;
break;
default:
gpio_cfgx = NULL;
break;
}
return gpio_cfgx;
}
/*
* 获取指定gpio的EN寄存器
* @gpio gpio编号
* @ret EN寄存器
*/
volatile unsigned int *gpio_get_en_reg(unsigned int gpio)
{
volatile unsigned int *gpio_enx = NULL; // GPIO_ENx寄存器
unsigned int port = GPIO_GET_PORT(gpio);
switch (port)
{
case 0:
gpio_enx = (volatile unsigned int *)LS1B_GPIO_EN0;
break;
case 1:
gpio_enx = (volatile unsigned int *)LS1B_GPIO_EN1;
break;
default:
gpio_enx = NULL;
return gpio_enx;
}
return gpio_enx;
}
/*
* gpio初始化
* @gpio gpio引脚，取值范围[0, 127]
* @mode gpio的工作模式(输入、输出)
*
* 例: 将gpio50初始化为输出
* gpio_init(50, gpio_mode_output);
*/
void gpio_init(unsigned int gpio, gpio_mode_t mode)
{
volatile unsigned int *gpio_enx = NULL; // GPIO_ENx寄存器
unsigned int pin = GPIO_GET_PIN(gpio);
// 将pin设为普通GPIO
pin_set_purpose(gpio, PIN_PURPOSE_GPIO);
// 设置gpio工作模式(输入、输出)
gpio_enx = gpio_get_en_reg(gpio);
if (gpio_mode_output == mode) // 输出
{
reg_clr_one_bit(gpio_enx, pin);
}
else // 输入
{
reg_set_one_bit(gpio_enx, pin);
}
return ;
}
/*
* 在指定gpio输出高电平或低电平
* @gpio gpio引脚，取值范围[0, 127]
* @level 电平值
*
* 例: 在gpio50上输出低电平
* gpio_set(50, gpio_level_low);
*/
void gpio_set(unsigned int gpio, gpio_level_t level)
{
volatile unsigned int *gpio_outx = NULL; // GPIO_OUTx寄存器
unsigned int port = GPIO_GET_PORT(gpio);
unsigned int pin = GPIO_GET_PIN(gpio);
// 获取寄存器地址
switch (port)
{
case 0:
gpio_outx = (volatile unsigned int *)LS1B_GPIO_OUT0;
break;
case 1:
gpio_outx = (volatile unsigned int *)LS1B_GPIO_OUT1;
break;
default: // 正确的程序不应该走到这里，直接返回
return ;
}
// 输出
if (gpio_level_low == level)
{
reg_clr_one_bit(gpio_outx, pin);
}
else
{
reg_set_one_bit(gpio_outx, pin);
}
return ;
}
/*
* 读取指定gpio引脚的值
* @gpio gpio引脚，取值范围[0,127]
*
* 例: 读取gpio50引脚上的值
* gpio_level_t level;
* level = gpio_get(50);
*/
unsigned int gpio_get(unsigned int gpio)
{
volatile unsigned int *gpio_inx = NULL; // GPIO_INx寄存器
unsigned int port = GPIO_GET_PORT(gpio);
unsigned int pin = GPIO_GET_PIN(gpio);
// 获取寄存器地址
switch (port)
{
case 0:
gpio_inx = (volatile unsigned int *)LS1B_GPIO_IN0;
break;
case 1:
gpio_inx = (volatile unsigned int *)LS1B_GPIO_IN1;
break;
default: // 正常的流程不应该走到这里，直接返回
return 0;
}
// 读取
return reg_get_bit(gpio_inx, pin);
}
/**
* 设置中断类型
* @gpio gpio引脚
* @type 触发中断的条件。高电平触发、低电平触发、上升沿触发 or 下降沿触发
*/
void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type)
{
volatile unsigned int *int_pol = NULL; // 中断极性选择寄存器
volatile unsigned int *int_edge = NULL; // 中断边沿选择寄存器
unsigned int port = GPIO_GET_PORT(gpio);
unsigned int pin = GPIO_GET_PIN(gpio);
// 获取寄存器地址
switch (port)
{
case 0: // GPIO[31:0]
int_pol = (volatile unsigned int *)LS1B_INT2_POL;
int_edge = (volatile unsigned int *)LS1B_INT2_EDGE;
break;
case 1: // GPIO[63:32]
int_pol = (volatile unsigned int *)LS1B_INT3_POL;
int_edge = (volatile unsigned int *)LS1B_INT3_EDGE;
break;
}
// 设置中断类型
switch (type)
{
case IRQ_TYPE_EDGE_RISING:
*int_pol |= (1 << pin);
*int_edge |= (1 << pin);
break;
case IRQ_TYPE_EDGE_FALLING:
*int_pol &= ~(1 << pin);
*int_edge |= (1 << pin);
break;
case IRQ_TYPE_LEVEL_HIGH:
*int_pol |= (1 << pin);
*int_edge &= ~(1 << pin);
break;
case IRQ_TYPE_LEVEL_LOW:
*int_pol &= ~(1 << pin);
*int_edge &= ~(1 << pin);
break;
default:
break;
}
return ;
}

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
#ifndef __LOONGSON_GPIO_H
#define __LOONGSON_GPIO_H
// 龙芯1c的gpio是按照0,1,2,3,4...这样的顺序编号的，
// 但在操作寄存器的时候，又是按照每32个一组来分的
// 这里利用这个特性，将每组的32个gpio叫做一个"port"，每个gpio在每组中的索引叫"pin"
// port = gpio / 32
// pin = gpio % 32
// 例如GPIO50，port=1,pin=18
#define GPIO_GET_PORT(gpio) ((gpio) / 32)
#define GPIO_GET_PIN(gpio) ((gpio) % 32)
// gpio的工作模式--输入、输出
typedef enum{
gpio_mode_output = 0, // 输出
gpio_mode_input = 1 // 输入
}gpio_mode_t;
// gpio高低电平值
typedef enum{
gpio_level_low = 0, // 低电平
gpio_level_high = 1 // 高电平
}gpio_level_t;
typedef enum {
// 上升沿触发
IRQ_TYPE_EDGE_RISING = 0x00000001,
// 下降沿触发
IRQ_TYPE_EDGE_FALLING = 0x00000002,
IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
// 高电平触发
IRQ_TYPE_LEVEL_HIGH = 0x00000004,
// 低电平触发
IRQ_TYPE_LEVEL_LOW = 0x00000008,
IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
}gpio_irq_type_t;
/*
* 获取指定gpio的CFG寄存器
* @gpio gpio编号
* @ret CFG寄存器
*/
volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio);
/*
* gpio初始化
* @gpio gpio引脚，取值范围[0, 127]
* @mode gpio的工作模式(输入、输出)
*
* 例: 将gpio50初始化为输出
* gpio_init(50, gpio_mode_output);
*/
void gpio_init(unsigned int gpio, gpio_mode_t mode);
/*
* 在指定gpio输出高电平或低电平
* @gpio gpio引脚，取值范围[0, 127]
* @level 电平值
*
* 例: 在gpio50上输出低电平
* gpio_set(50, gpio_level_low);
*/
void gpio_set(unsigned int gpio, gpio_level_t level);
/*
* 读取指定gpio引脚的值
* @gpio gpio引脚，取值范围[0,127]
*
* 例: 读取gpio50引脚上的值
* gpio_level_t level;
* level = gpio_get(50);
*/
unsigned int gpio_get(unsigned int gpio);
/**
* 设置中断类型
* @gpio gpio引脚
* @type 触发中断的条件。高电平触发、低电平触发、上升沿触发 or 下降沿触发
*/
void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type);
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 引脚功能(普通gpio，pwm，复用等)相关接口
#include "ls1b_public.h"
#include "ls1b_regs.h"
#include "ls1b_gpio.h"
#include "ls1b_pin.h"
/*
* 把指定pin设置为指定用途(普通gpio，非gpio)
* @gpio gpio引脚编号
* @purpose 用途
*/
void pin_set_purpose(unsigned int gpio, pin_purpose_t purpose)
{
volatile unsigned int *gpio_cfgx; // GPIO_CFGx寄存器
unsigned int pin = GPIO_GET_PIN(gpio);
gpio_cfgx = gpio_get_cfg_reg(gpio);
if (PIN_PURPOSE_GPIO == purpose) // 引脚用作普通gpio
{
reg_set_one_bit(gpio_cfgx, pin);
}
else // 引脚用作其它功能(非gpio)
{
reg_clr_one_bit(gpio_cfgx, pin);
}
return ;
}
/*
* 设置指定pin为第n复用
* @gpio gpio编号
* @remap 第n复用
*/
void pin_set_remap(unsigned int gpio, pin_remap_t remap)
{
volatile unsigned int *reg = NULL; // 复用寄存器
unsigned int port = GPIO_GET_PORT(gpio);
unsigned int pin = GPIO_GET_PIN(gpio);
int i;
/*指定全部pin复用为0*/
for (i = 0; i <= 4; i++)
{
reg = (volatile unsigned int *)((LS1B_CBUS_FIRST0) + ((port) * 0x04) + ((i) * 0x10));
// 置0
reg_clr_one_bit(reg, pin);
}
if (remap == PIN_REMAP_DEFAULT) return;
switch (port)
{
case 0:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST0;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND0;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD0;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH0;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH0;
break;
}
break;
case 1:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST1;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND1;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD1;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH1;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH1;
break;
}
break;
case 2:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST2;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND2;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD2;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH2;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH2;
break;
}
break;
case 3:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST3;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND3;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD3;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH3;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH3;
break;
}
break;
default:
return ;
}
// 置1
reg_set_one_bit(reg, pin);
return ;
}

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
// 引脚功能(普通gpio，pwm，复用等)相关接口
#ifndef __LOONGSON_PIN_H
#define __LOONGSON_PIN_H
// 引脚用途
typedef enum
{
PIN_PURPOSE_GPIO = 0, // 引脚用作普通gpio
PIN_PURPOSE_OTHER, // 引脚用作其它功能(非gpio)
}pin_purpose_t;
// 引脚复用
typedef enum
{
PIN_REMAP_FIRST = 0, // 第一复用
PIN_REMAP_SECOND, // 第二复用
PIN_REMAP_THIRD, // 第三复用
PIN_REMAP_FOURTH, // 第四复用
PIN_REMAP_FIFTH, // 第五复用
PIN_REMAP_DEFAULT, //缺省复用
}pin_remap_t;
/*
* 把指定pin设置为指定用途(普通gpio，非gpio)
* @gpio gpio引脚编号
* @purpose 用途
*/
void pin_set_purpose(unsigned int gpio, pin_purpose_t purpose);
/*
* 设置指定pin为第n复用
* @gpio gpio编号
* @remap 第n复用
*/
void pin_set_remap(unsigned int gpio, pin_remap_t remap);
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 一些常用的、共用的接口
/*
* 将指定寄存器的指定位置1
* @reg 寄存器地址
* @bit 需要置1的那一bit
*/
void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit)
{
unsigned int temp, mask;
mask = 1 << bit;
temp = *reg;
temp |= mask;
*reg = temp;
return ;
}
/*
* 将指定寄存器的指定位清零
* @reg 寄存器地址
* @bit 需要清零的那一bit
*/
void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit)
{
unsigned int temp, mask;
mask = 1 << bit;
temp = *reg;
temp &= ~mask;
*reg = temp;
return ;
}
/*
* 获取指定寄存器的指定位的值
* @reg 寄存器地址
* @bit 需要读取值的那一bit
* @ret 指定位的值
*/
unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit)
{
unsigned int temp;
temp = *reg;
temp = (temp >> bit) & 1;
return temp;
}
/*
* 向寄存器中写入8bit(一个字节)数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_8(unsigned char data, volatile unsigned char *addr)
{
*addr = data;
}
/*
* 从寄存器读出8bit(一个字节)数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned char reg_read_8(volatile unsigned char *addr)
{
return (*addr);
}
/*
* 向寄存器中写一个32bit的数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_32(unsigned int data, volatile unsigned int *addr)
{
*addr = data;
}
/*
* 从寄存器读出一个32bit数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned int reg_read_32(volatile unsigned int *addr)
{
return (*addr);
}
/**
* ffs - find first bit set
* @x: the word to search
*
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
int ls1b_ffs(int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
/*
* fls - find last (most-significant) bit set
* @x: the word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
int ls1b_fls(int x)
{
int r = 32;
if (!x)
return 0;
if (!(x & 0xffff0000u))
{
x <<= 16;
r -= 16;
}
if (!(x & 0xff000000u))
{
x <<= 8;
r -= 8;
}
if (!(x & 0xf0000000u))
{
x <<= 4;
r -= 4;
}
if (!(x & 0xc0000000u))
{
x <<= 2;
r -= 2;
}
if (!(x & 0x80000000u))
{
x <<= 1;
r -= 1;
}
return r;
}

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
// 一些常用的、共用的接口
#ifndef __LOONGSON_PUBLIC_H
#define __LOONGSON_PUBLIC_H
#include <stdio.h>
// pmon提供的打印函数，见main()函数
struct callvectors {
int (*open) (char *, int, int);
int (*close) (int);
int (*read) (int, void *, int);
int (*write) (int, void *, int);
long long (*lseek) (int, long long, int);
int (*printf) (const char *, ...);
void (*cacheflush) (void);
char *(*gets) (char *);
};
#define myprintf (*callvec->printf)
#define mygets (*callvec->gets)
extern struct callvectors *callvec;
#define MIN(a, b) ((a) > (b) ? (b) : (a))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
typedef enum
{
FALSE=0,
TRUE=1
}BOOL;
/*
* 将指定寄存器的指定位置1
* @reg 寄存器地址
* @bit 需要置1的那一bit
*/
void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit);
/*
* 将指定寄存器的指定位清零
* @reg 寄存器地址
* @bit 需要清零的那一bit
*/
void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit);
/*
* 获取指定寄存器的指定位的值
* @reg 寄存器地址
* @bit 需要读取值的那一bit
* @ret 指定位的值
*/
unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit);
/*
* 向寄存器中写入8bit(一个字节)数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_8(unsigned char data, volatile unsigned char *addr);
/*
* 从寄存器读出8bit(一个字节)数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned char reg_read_8(volatile unsigned char *addr);
/*
* 向寄存器中写一个32bit的数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_32(unsigned int data, volatile unsigned int *addr);
/*
* 从寄存器读出一个32bit数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned int reg_read_32(volatile unsigned int *addr);
/**
* ffs - find first bit set
* @x: the word to search
*/
int ls1b_ffs(int x);
/*
* fls - find last (most-significant) bit set
* @x: the word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
int ls1b_fls(int x);
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 龙芯1b外设寄存器
#ifndef __LOONGSON_LS1B_REGS_H
#define __LOONGSON_LS1B_REGS_H
// 时钟相关寄存器地址
#define LS1B_START_FREQ (0xbfe78030)
#define LS1B_CLK_DIV_PARAM (0xbfe78034)
// gpio相关寄存器地址
#define LS1B_GPIO_CFG0 (0xbfd010c0)
#define LS1B_GPIO_EN0 (0xbfd010d0)
#define LS1B_GPIO_IN0 (0xbfd010e0)
#define LS1B_GPIO_OUT0 (0xbfd010f0)
#define LS1B_GPIO_CFG1 (0xbfd010c4)
#define LS1B_GPIO_EN1 (0xbfd010d4)
#define LS1B_GPIO_IN1 (0xbfd010e4)
#define LS1B_GPIO_OUT1 (0xbfd010f4)
// 复用相关寄存器
#define LS1B_CBUS_FIRST0 (0xbfd011c0)
#define LS1B_CBUS_SECOND0 (0xbfd011d0)
#define LS1B_CBUS_THIRD0 (0xbfd011e0)
#define LS1B_CBUS_FOURTH0 (0xbfd011f0)
#define LS1B_CBUS_FIFTH0 (0xbfd01200)
#define LS1B_CBUS_FIRST1 (0xbfd011c4)
#define LS1B_CBUS_SECOND1 (0xbfd011d4)
#define LS1B_CBUS_THIRD1 (0xbfd011e4)
#define LS1B_CBUS_FOURTH1 (0xbfd011f4)
#define LS1B_CBUS_FIFTH1 (0xbfd01204)
#define LS1B_CBUS_FIRST2 (0xbfd011c8)
#define LS1B_CBUS_SECOND2 (0xbfd011d8)
#define LS1B_CBUS_THIRD2 (0xbfd011e8)
#define LS1B_CBUS_FOURTH2 (0xbfd011f8)
#define LS1B_CBUS_FIFTH2 (0xbfd01208)
#define LS1B_CBUS_FIRST3 (0xbfd011cc)
#define LS1B_CBUS_SECOND3 (0xbfd011dc)
#define LS1B_CBUS_THIRD3 (0xbfd011ec)
#define LS1B_CBUS_FOURTH3 (0xbfd011fc)
#define LS1B_CBUS_FIFTH3 (0xbfd0120c)
// PWM寄存器偏移
#define LS1B_PWM_CNTR (0x0)
#define LS1B_PWM_HRC (0x4)
#define LS1B_PWM_LRC (0x8)
#define LS1B_PWM_CTRL (0xC)
// PWM基地址
#define LS1B_REG_BASE_PWM0 (0xbfe5c000)
#define LS1B_REG_BASE_PWM1 (0xbfe5c010)
#define LS1B_REG_BASE_PWM2 (0xbfe5c020)
#define LS1B_REG_BASE_PWM3 (0xbfe5c030)
//CAN基地址
#define LS1B_REG_BASE_CAN0 (0xbfe50000)
#define LS1B_REG_BASE_CAN1 (0xbfe54000)
// 中断配置寄存器
#define LS1B_INT0_SR (0xbfd01040)
#define LS1B_INT0_EN (0xbfd01044)
#define LS1B_INT0_SET (0xbfd01048)
#define LS1B_INT0_CLR (0xbfd0104c)
#define LS1B_INT0_POL (0xbfd01050)
#define LS1B_INT0_EDGE (0xbfd01054)
#define LS1B_INT1_SR (0xbfd01058)
#define LS1B_INT1_EN (0xbfd0105c)
#define LS1B_INT1_SET (0xbfd01060)
#define LS1B_INT1_CLR (0xbfd01064)
#define LS1B_INT1_POL (0xbfd01068)
#define LS1B_INT1_EDGE (0xbfd0106c)
#define LS1B_INT2_SR (0xbfd01070)
#define LS1B_INT2_EN (0xbfd01074)
#define LS1B_INT2_SET (0xbfd01078)
#define LS1B_INT2_CLR (0xbfd0107c)
#define LS1B_INT2_POL (0xbfd01080)
#define LS1B_INT2_EDGE (0xbfd01084)
#define LS1B_INT3_SR (0xbfd01088)
#define LS1B_INT3_EN (0xbfd0108c)
#define LS1B_INT3_SET (0xbfd01090)
#define LS1B_INT3_CLR (0xbfd01094)
#define LS1B_INT3_POL (0xbfd01098)
#define LS1B_INT3_EDGE (0xbfd0109c)
#define LS1B_INT4_SR (0xbfd010a0)
#define LS1B_INT4_EN (0xbfd010a4)
#define LS1B_INT4_SET (0xbfd010a8)
#define LS1B_INT4_CLR (0xbfd010ac)
#define LS1B_INT4_POL (0xbfd010b0)
#define LS1B_INT4_EDGE (0xbfd010b4)
// I2C寄存器
#define LS1B_I2C0_BASE (0xbfe58000)
#define LS1B_I2C1_BASE (0xbfe68000)
#define LS1B_I2C2_BASE (0xbfe70000)
// SPI寄存器
#define LS1B_SPI0_BASE (0xbfe80000)
#define LS1B_SPI1_BASE (0xbfec0000)
// 串口寄存器
#define LS1B_UART00_BASE (0xbfe40000)
#define LS1B_UART01_BASE (0xbfe41000)
#define LS1B_UART1_BASE (0xbfe44000)
#define LS1B_UART2_BASE (0xbfe48000)
#define LS1B_UART3_BASE (0xbfe4c000)
#define LS1B_UART4_BASE (0xbfe6c000)
#define LS1B_UART5_BASE (0xbfe7c000)
#define LS1B_UART6_BASE (0xbfe41000)
#define LS1B_UART7_BASE (0xbfe42000)
#define LS1B_UART8_BASE (0xbfe43000)
#define LS1B_UART9_BASE (0xbfe45000)
#define LS1B_UART10_BASE (0xbfe46000)
#define LS1B_UART11_BASE (0xbfe47000)
//RTC寄存器
#define LS1B_RTC_BASE (0xbfe64024)
#endif

251
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@ -0,0 +1,251 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 串口相关源码
#include <stdio.h>
#include <stdarg.h>
#include "ls1b_public.h"
#include "ls1b_regs.h"
#include "ls1b_pin.h"
#include "ls1b_uart.h"
#include "ls1b_clock.h"
#include "ls1b.h"
// 串口线路状态寄存器的位域
#define LS1B_UART_LSR_TE (1 << 6)
#define LS1B_UART_LSR_TFE (1 << 5)
// 打印缓存的大小
#define LS1B_UART_PRINT_BUF_SIZE (256)
// 调试串口信息
ls1b_uart_info_t debug_uart_info = {0};
/*
* 获取指定串口模块的基地址
* @UARTx 串口编号
* @ret 基地址
*/
void *uart_get_base(ls1b_uart_t UARTx)
{
void *base = NULL;
switch (UARTx)
{
case LS1B_UART00:
base = (void *)LS1B_UART00_BASE;
break;
case LS1B_UART01:
base = (void *)LS1B_UART01_BASE;
break;
case LS1B_UART1:
base = (void *)LS1B_UART1_BASE;
break;
case LS1B_UART2:
base = (void *)LS1B_UART2_BASE;
break;
case LS1B_UART3:
base = (void *)LS1B_UART3_BASE;
break;
case LS1B_UART4:
base = (void *)LS1B_UART4_BASE;
break;
case LS1B_UART5:
base = (void *)LS1B_UART5_BASE;
break;
case LS1B_UART6:
base = (void *)LS1B_UART6_BASE;
break;
case LS1B_UART7:
base = (void *)LS1B_UART7_BASE;
break;
case LS1B_UART8:
base = (void *)LS1B_UART8_BASE;
break;
case LS1B_UART9:
base = (void *)LS1B_UART9_BASE;
break;
case LS1B_UART10:
base = (void *)LS1B_UART10_BASE;
break;
case LS1B_UART11:
base = (void *)LS1B_UART11_BASE;
break;
default:
break;
}
return base;
}
/*
* 初始化指定的串口模块
* @uart_info_p 串口模块信息
*/
void uart_init(ls1b_uart_info_t *uart_info_p)
{
void *uart_base = uart_get_base(uart_info_p->UARTx);
unsigned long baudrate_div = 0;
// 禁止所有中断
reg_write_8(0, uart_base + LS1B_UART_IER_OFFSET);
// 接收FIFO的中断申请Trigger为14字节，清空发送和接收FIFO，并复位
reg_write_8(0xc3, uart_base + LS1B_UART_FCR_OFFSET);
// 设置波特率
reg_write_8(0x80, uart_base + LS1B_UART_LCR_OFFSET);
baudrate_div = clk_get_apb_rate() / 16 / uart_info_p->baudrate;
reg_write_8((baudrate_div >> 8) & 0xff, uart_base + LS1B_UART_MSB_OFFSET);
reg_write_8(baudrate_div & 0xff, uart_base + LS1B_UART_LSB_OFFSET);
// 8个数据位，1个停止位，无校验
reg_write_8(0x03, uart_base + LS1B_UART_LCR_OFFSET);
// 使能接收中断
if (TRUE == uart_info_p->rx_enable)
{
reg_write_8(IER_IRxE|IER_ILE , uart_base + LS1B_UART_IER_OFFSET);
}
return ;
}
/*
* 判断FIFO是否为空
* @uartx 串口号
* @ret TRUE or FALSE
*/
BOOL uart_is_transmit_empty(ls1b_uart_t uartx)
{
void *uart_base = uart_get_base(uartx);
unsigned char status = reg_read_8(uart_base + LS1B_UART_LSR_OFFSET);
if (status & (LS1B_UART_LSR_TE | LS1B_UART_LSR_TFE))
{
return TRUE;
}
else
{
return FALSE;
}
}
/*
* 发送一个字节
* @uartx 串口号
* @ch 待发送的字符串
*/
void uart_putc(ls1b_uart_t uartx, unsigned char ch)
{
void *uart_base = uart_get_base(uartx);
// 等待
while (FALSE == uart_is_transmit_empty(uartx))
;
// 发送
reg_write_8(ch, uart_base + LS1B_UART_DAT_OFFSET);
return ;
}
/*
* 打印一个字符串到指定串口
* @uartx 串口号
* @str 待打印的字符串
*/
void uart_print(ls1b_uart_t uartx, const char *str)
{
while ('\0' != *str) // 判断是否为字符串结束符
{
uart_putc(uartx, *str); // 发送一个字符
str++;
}
return ;
}
/*
* 初始化串口2
*/
void uart2_init(void)
{
unsigned int tx_gpio = 37;
unsigned int rx_gpio = 36;
// 设置复用
pin_set_remap(tx_gpio, PIN_REMAP_SECOND);
pin_set_remap(rx_gpio, PIN_REMAP_SECOND);
// 初始化相关寄存器
debug_uart_info.UARTx = LS1B_UART2;
debug_uart_info.baudrate = 115200;
debug_uart_info.rx_enable = FALSE; // 调试串口只需要打印(发送)功能，不需要接收功能
uart_init(&debug_uart_info);
return ;
}
/*
* 在串口2上打印字符串
* @str 待打印的字符串
*/
void uart2_print(const char *str)
{
uart_print(LS1B_UART2, str);
return ;
}
/*
* 在调试串口打印字符串
* @str 待打印的字符串
*/
void uart_debug_print(const char *str)
{
uart_print(debug_uart_info.UARTx, str);
return ;
}
/*
* 在调试串口打印一个字符
* @ch 待打印的字符
*/
void uart_debug_putc(unsigned char ch)
{
uart_putc(debug_uart_info.UARTx, ch);
return ;
}

181
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@ -0,0 +1,181 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 串口相关头文件
#ifndef __LOONGSON_UART_H
#define __LOONGSON_UART_H
#include "ls1b_public.h"
// 串口各寄存器相对基地址的偏移
#define LS1B_UART_DAT_OFFSET (0)
#define LS1B_UART_IER_OFFSET (1)
#define LS1B_UART_IIR_OFFSET (2)
#define LS1B_UART_FCR_OFFSET (2)
#define LS1B_UART_LCR_OFFSET (3)
#define LS1B_UART_MCR_OFFSET (4)
#define LS1B_UART_LSR_OFFSET (5)
#define LS1B_UART_MSR_OFFSET (6)
#define LS1B_UART_LSB_OFFSET (0) // 分频锁存器1
#define LS1B_UART_MSB_OFFSET (1) // 分频锁存器2
/* interrupt enable register */
#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
#define IER_IME 0x8 /* Modem状态中断使能 */
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
// 线路控制寄存器
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
// 串口模块编号
typedef enum
{
LS1B_UART00 = 0, // 全功能串口UART0可以分为两个四线串口UART00和UART01
LS1B_UART01,
LS1B_UART1,
LS1B_UART2,
LS1B_UART3,
LS1B_UART4,
LS1B_UART5,
LS1B_UART6,
LS1B_UART7,
LS1B_UART8,
LS1B_UART9,
LS1B_UART10,
LS1B_UART11
}ls1b_uart_t;
// 串口信息
typedef struct
{
ls1b_uart_t UARTx; // 串口模块编号
unsigned int baudrate; // 波特率
BOOL rx_enable; // 是否需要使用串口接收数据(使能接收中断)，发送默认使能
}ls1b_uart_info_t;
/*
* 获取指定串口模块的基地址
* @UARTx 串口编号
* @ret 基地址
*/
void *uart_get_base(ls1b_uart_t UARTx);
/*
* 初始化指定的串口模块
* @uart_info_p 串口模块信息
*/
void uart_init(ls1b_uart_info_t *uart_info_p);
/*
* 初始化串口2
*/
void uart2_init(void);
/*
* 在串口2上打印字符串
* @str 待打印的字符串
*/
void uart2_print(const char *str);
/*
* 在调试串口打印字符串
* @str 待打印的字符串
*/
void uart_debug_print(const char *str);
/*
* 在调试串口打印一个字符
* @ch 待打印的字符
*/
void uart_debug_putc(unsigned char ch);
/*
* 发送一个字节
* @uartx 串口号
* @ch 待发送的字符串
*/
void uart_putc(ls1b_uart_t uartx, unsigned char ch);
/*
* 打印一个字符串到指定串口
* @uartx 串口号
* @str 待打印的字符串
*/
void uart_print(ls1b_uart_t uartx, const char *str);
#endif

18
bsp/ls1bdev/rtconfig.h
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@ -10,15 +10,12 @@
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_DEBUG
/* Inter-Thread communication */
@ -40,8 +37,8 @@
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40002
#define RT_CONSOLE_DEVICE_NAME "uart5"
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
@ -114,9 +111,6 @@
/* Utilities */
/* RT-Thread MIPS CPU */
/* RT-Thread online packages */
/* IoT - internet of things */
@ -157,7 +151,9 @@
/* samples: kernel and components samples */
#define SOC_LS1B
#define RT_USING_UART0
#define RT_MEM_SIZE 256
#define RT_OSC_CLK 25000000
#define RT_USING_UART5
#define RT_UART_RX_BUFFER_SIZE 64
#endif

2
bsp/ls1bdev/rtconfig.py
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@ -36,7 +36,7 @@ OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -mips32r2'
DEVICE = ' -mips32 -msoft-float -mfp32'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'