修改无意义代码
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@ -213,8 +213,6 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
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{
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{
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#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
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tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
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#else
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tim_clock = HAL_RCC_GetPCLK2Freq();
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#endif
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#endif
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}
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}
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else
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else
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@ -262,8 +260,6 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
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{
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{
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#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
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tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
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#else
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tim_clock = HAL_RCC_GetPCLK2Freq();
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#endif
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#endif
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}
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}
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else
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else
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@ -21,9 +21,9 @@
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struct rt_pwm_configuration
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struct rt_pwm_configuration
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{
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{
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rt_uint32_t channel; /* 0-n */
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rt_uint32_t channel; /* 0-n */
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rt_uint32_t period; /* unit:ns 1ns~4.29s:1Ghz~0.23hz */
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rt_uint32_t period; /* unit:ns 1ns~4.29s:1Ghz~0.23hz */
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rt_uint32_t pulse; /* unit:ns (pulse<=period) */
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rt_uint32_t pulse; /* unit:ns (pulse<=period) */
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/*
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/*
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* RT_TRUE : The channel of pwm is complememtary.
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* RT_TRUE : The channel of pwm is complememtary.
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