From 63239801d9a2abe1b210faf6cd9f3b126924f7e0 Mon Sep 17 00:00:00 2001
From: Trisuborn <553070703@qq.com>
Date: Wed, 20 Jan 2021 11:24:00 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E6=97=A0=E6=84=8F=E4=B9=89?=
 =?UTF-8?q?=E4=BB=A3=E7=A0=81?=
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---
 bsp/stm32/libraries/HAL_Drivers/drv_pwm.c       | 4 ----
 components/drivers/include/drivers/rt_drv_pwm.h | 6 +++---
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
index ab3897c569..38958dddd4 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
@@ -213,8 +213,6 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
     {
 #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
         tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
-#else
-        tim_clock = HAL_RCC_GetPCLK2Freq();
 #endif
     }
     else
@@ -262,8 +260,6 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
     {
 #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
         tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
-#else
-        tim_clock = HAL_RCC_GetPCLK2Freq();
 #endif
     }
     else
diff --git a/components/drivers/include/drivers/rt_drv_pwm.h b/components/drivers/include/drivers/rt_drv_pwm.h
index 4b436758d9..a4d64fbc12 100644
--- a/components/drivers/include/drivers/rt_drv_pwm.h
+++ b/components/drivers/include/drivers/rt_drv_pwm.h
@@ -21,9 +21,9 @@
 
 struct rt_pwm_configuration
 {
-    rt_uint32_t channel;        /* 0-n */
-    rt_uint32_t period;         /* unit:ns 1ns~4.29s:1Ghz~0.23hz */
-    rt_uint32_t pulse;          /* unit:ns (pulse<=period) */
+    rt_uint32_t channel; /* 0-n */
+    rt_uint32_t period;  /* unit:ns 1ns~4.29s:1Ghz~0.23hz */
+    rt_uint32_t pulse;   /* unit:ns (pulse<=period) */
 
     /*
      * RT_TRUE  : The channel of pwm is complememtary.