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Merge pull request #5538 from Blues-Jiang/Blues_dev 

[bsp/n32g45x] Add UART support and menuconfig.
This commit is contained in:
guo 2022-01-20 10:45:37 +08:00 committed by GitHub
parent f2dc981994 d62368cc75
commit 61d5e72248
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 772 additions and 214 deletions
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2
bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c
View File

@ -124,7 +124,7 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
ADC_InitStructure.ChsNumber = 1;
ADC_Init(n32_adc_handler, &ADC_InitStructure);
if (((n32_adc_handler == ADC2) || (n32_adc_handler == ADC2))
if (((n32_adc_handler == ADC1) || (n32_adc_handler == ADC2))
&& ((n32_adc_get_channel(channel) == ADC_CH_16)
|| (n32_adc_get_channel(channel) == ADC_CH_18)))
{

277
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
View File

@ -15,7 +15,9 @@
#ifdef RT_USING_PIN
#define N32G45X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
#ifndef N32G45X_PIN_NUMBERS
#define N32G45X_PIN_NUMBERS 64//[48, 64, 80, 100, 128 ]
#endif
#define __N32_PIN(index, rcc, gpio, gpio_index) \
{ \
@ -88,7 +90,6 @@ static const struct pin_index pins[] =
__N32_PIN(46, APB2, B, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
#endif
#if (N32G45X_PIN_NUMBERS == 64)
__N32_PIN_DEFAULT,
@ -96,8 +97,8 @@ static const struct pin_index pins[] =
__N32_PIN(2, APB2, C, 13),
__N32_PIN(3, APB2, C, 14),
__N32_PIN(4, APB2, C, 15),
__N32_PIN(5, APB2, D, 0),
__N32_PIN(6, APB2, D, 1),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(8, APB2, C, 0),
__N32_PIN(9, APB2, C, 1),
@ -157,6 +158,89 @@ static const struct pin_index pins[] =
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
#endif
#if (N32G45X_PIN_NUMBERS == 80)
__N32_PIN_DEFAULT,
__N32_PIN(1, APB2, E, 2),
__N32_PIN(2, APB2, E, 3),
__N32_PIN_DEFAULT,
__N32_PIN(4, APB2, C, 13),
__N32_PIN(5, APB2, C, 14),
__N32_PIN(6, APB2, C, 15),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(10, APB2, C, 0),
__N32_PIN(11, APB2, C, 1),
__N32_PIN(12, APB2, C, 2),
__N32_PIN(13, APB2, C, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(16, APB2, A, 0),
__N32_PIN(17, APB2, A, 1),
__N32_PIN(18, APB2, A, 2),
__N32_PIN(19, APB2, A, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(22, APB2, A, 4),
__N32_PIN(23, APB2, A, 5),
__N32_PIN(24, APB2, A, 6),
__N32_PIN(25, APB2, A, 7),
__N32_PIN(26, APB2, C, 4),
__N32_PIN(27, APB2, C, 5),
__N32_PIN(28, APB2, B, 0),
__N32_PIN(29, APB2, B, 1),
__N32_PIN(30, APB2, B, 2),
__N32_PIN(31, APB2, E, 7),
__N32_PIN(32, APB2, E, 8),
__N32_PIN(33, APB2, E, 9),
__N32_PIN(34, APB2, E, 10),
__N32_PIN(35, APB2, E, 11),
__N32_PIN(36, APB2, E, 12),
__N32_PIN(37, APB2, E, 13),
__N32_PIN(38, APB2, B, 10),
__N32_PIN(39, APB2, B, 11),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(42, APB2, B, 12),
__N32_PIN(43, APB2, B, 13),
__N32_PIN(44, APB2, B, 14),
__N32_PIN(45, APB2, B, 15),
__N32_PIN(46, APB2, D, 8),
__N32_PIN(47, APB2, D, 9),
__N32_PIN(48, APB2, D, 10),
__N32_PIN(49, APB2, D, 14),
__N32_PIN(50, APB2, D, 15),
__N32_PIN(51, APB2, C, 6),
__N32_PIN(52, APB2, C, 7),
__N32_PIN(53, APB2, C, 8),
__N32_PIN(54, APB2, C, 9),
__N32_PIN(55, APB2, A, 8),
__N32_PIN(56, APB2, A, 9),
__N32_PIN(57, APB2, A, 10),
__N32_PIN(58, APB2, A, 11),
__N32_PIN(59, APB2, A, 12),
__N32_PIN(60, APB2, A, 13),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(63, APB2, A, 14),
__N32_PIN(64, APB2, A, 15),
__N32_PIN(65, APB2, C, 10),
__N32_PIN(66, APB2, C, 11),
__N32_PIN(67, APB2, C, 12),
__N32_PIN(68, APB2, D, 0),
__N32_PIN(69, APB2, D, 1),
__N32_PIN(70, APB2, D, 2),
__N32_PIN(71, APB2, B, 3),
__N32_PIN(72, APB2, B, 4),
__N32_PIN(73, APB2, B, 5),
__N32_PIN(74, APB2, B, 6),
__N32_PIN(75, APB2, B, 7),
__N32_PIN_DEFAULT,
__N32_PIN(77, APB2, B, 8),
__N32_PIN(78, APB2, B, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
#endif
#if (N32G45X_PIN_NUMBERS == 100)
__N32_PIN_DEFAULT,
__N32_PIN(1, APB2, E, 2),
@ -260,7 +344,7 @@ static const struct pin_index pins[] =
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
#endif
#if (N32G45X_PIN_NUMBERS == 144)
#if (N32G45X_PIN_NUMBERS == 128)
__N32_PIN_DEFAULT,
__N32_PIN(1, APB2, E, 2),
__N32_PIN(2, APB2, E, 3),
@ -271,7 +355,6 @@ static const struct pin_index pins[] =
__N32_PIN(7, APB2, C, 13),
__N32_PIN(8, APB2, C, 14),
__N32_PIN(9, APB2, C, 15),
__N32_PIN(10, APB2, F, 0),
__N32_PIN(11, APB2, F, 1),
__N32_PIN(12, APB2, F, 2),
@ -280,131 +363,115 @@ static const struct pin_index pins[] =
__N32_PIN(15, APB2, F, 5),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(18, APB2, F, 6),
__N32_PIN(19, APB2, F, 7),
__N32_PIN(20, APB2, F, 8),
__N32_PIN(21, APB2, F, 9),
__N32_PIN(22, APB2, F, 10),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(26, APB2, C, 0),
__N32_PIN(27, APB2, C, 1),
__N32_PIN(28, APB2, C, 2),
__N32_PIN(29, APB2, C, 3),
__N32_PIN(21, APB2, C, 0),
__N32_PIN(22, APB2, C, 1),
__N32_PIN(23, APB2, C, 2),
__N32_PIN(24, APB2, C, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(34, APB2, A, 0),
__N32_PIN(35, APB2, A, 1),
__N32_PIN(36, APB2, A, 2),
__N32_PIN(37, APB2, A, 3),
__N32_PIN(29, APB2, A, 0),
__N32_PIN(30, APB2, A, 1),
__N32_PIN(31, APB2, A, 2),
__N32_PIN(32, APB2, A, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(40, APB2, A, 4),
__N32_PIN(41, APB2, A, 5),
__N32_PIN(42, APB2, A, 6),
__N32_PIN(43, APB2, A, 7),
__N32_PIN(44, APB2, C, 4),
__N32_PIN(45, APB2, C, 5),
__N32_PIN(46, APB2, B, 0),
__N32_PIN(47, APB2, B, 1),
__N32_PIN(48, APB2, B, 2),
__N32_PIN(49, APB2, F, 11),
__N32_PIN(50, APB2, F, 12),
__N32_PIN(35, APB2, A, 4),
__N32_PIN(36, APB2, A, 5),
__N32_PIN(37, APB2, A, 6),
__N32_PIN(38, APB2, A, 7),
__N32_PIN(39, APB2, C, 4),
__N32_PIN(40, APB2, C, 5),
__N32_PIN(41, APB2, B, 0),
__N32_PIN(42, APB2, B, 1),
__N32_PIN(43, APB2, B, 2),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(53, APB2, F, 13),
__N32_PIN(54, APB2, F, 14),
__N32_PIN(55, APB2, F, 15),
__N32_PIN(56, APB2, G, 0),
__N32_PIN(57, APB2, G, 1),
__N32_PIN(58, APB2, E, 7),
__N32_PIN(59, APB2, E, 8),
__N32_PIN(60, APB2, E, 9),
__N32_PIN(46, APB2, F, 12),
__N32_PIN(47, APB2, F, 13),
__N32_PIN(48, APB2, F, 14),
__N32_PIN(49, APB2, F, 15),
__N32_PIN(50, APB2, E, 7),
__N32_PIN(51, APB2, E, 8),
__N32_PIN(52, APB2, E, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(63, APB2, E, 10),
__N32_PIN(64, APB2, E, 11),
__N32_PIN(65, APB2, E, 12),
__N32_PIN(66, APB2, E, 13),
__N32_PIN(67, APB2, E, 14),
__N32_PIN(68, APB2, E, 15),
__N32_PIN(69, APB2, B, 10),
__N32_PIN(70, APB2, B, 11),
__N32_PIN(55, APB2, E, 10),
__N32_PIN(56, APB2, E, 11),
__N32_PIN(57, APB2, E, 12),
__N32_PIN(58, APB2, E, 13),
__N32_PIN(59, APB2, E, 14),
__N32_PIN(60, APB2, E, 15),
__N32_PIN(61, APB2, B, 10),
__N32_PIN(62, APB2, B, 11),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(73, APB2, B, 12),
__N32_PIN(74, APB2, B, 13),
__N32_PIN(75, APB2, B, 14),
__N32_PIN(76, APB2, B, 15),
__N32_PIN(77, APB2, D, 8),
__N32_PIN(78, APB2, D, 9),
__N32_PIN(79, APB2, D, 10),
__N32_PIN(80, APB2, D, 11),
__N32_PIN(81, APB2, D, 12),
__N32_PIN(82, APB2, D, 13),
__N32_PIN(65, APB2, B, 12),
__N32_PIN(66, APB2, B, 13),
__N32_PIN(67, APB2, B, 14),
__N32_PIN(68, APB2, B, 15),
__N32_PIN(69, APB2, D, 8),
__N32_PIN(70, APB2, D, 9),
__N32_PIN(71, APB2, D, 10),
__N32_PIN(72, APB2, D, 11),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(85, APB2, D, 14),
__N32_PIN(86, APB2, D, 15),
__N32_PIN(87, APB2, G, 2),
__N32_PIN(88, APB2, G, 3),
__N32_PIN(89, APB2, G, 4),
__N32_PIN(90, APB2, G, 5),
__N32_PIN(91, APB2, G, 6),
__N32_PIN(92, APB2, G, 7),
__N32_PIN(93, APB2, G, 8),
__N32_PIN(75, APB2, D, 12),
__N32_PIN(76, APB2, D, 13),
__N32_PIN(77, APB2, D, 14),
__N32_PIN(78, APB2, D, 15),
__N32_PIN(79, APB2, G, 0),
__N32_PIN(80, APB2, G, 1),
__N32_PIN(81, APB2, G, 2),
__N32_PIN(82, APB2, G, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(96, APB2, C, 6),
__N32_PIN(97, APB2, C, 7),
__N32_PIN(98, APB2, C, 8),
__N32_PIN(99, APB2, C, 9),
__N32_PIN(100, APB2, A, 8),
__N32_PIN(101, APB2, A, 9),
__N32_PIN(102, APB2, A, 10),
__N32_PIN(103, APB2, A, 11),
__N32_PIN(104, APB2, A, 12),
__N32_PIN(105, APB2, A, 13),
__N32_PIN(85, APB2, C, 6),
__N32_PIN(86, APB2, C, 7),
__N32_PIN(87, APB2, C, 8),
__N32_PIN(88, APB2, C, 9),
__N32_PIN(89, APB2, A, 8),
__N32_PIN(90, APB2, A, 9),
__N32_PIN(91, APB2, A, 10),
__N32_PIN(92, APB2, A, 11),
__N32_PIN(93, APB2, A, 12),
__N32_PIN(94, APB2, A, 13),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(109, APB2, A, 14),
__N32_PIN(110, APB2, A, 15),
__N32_PIN(111, APB2, C, 10),
__N32_PIN(112, APB2, C, 11),
__N32_PIN(113, APB2, C, 12),
__N32_PIN(114, APB2, D, 0),
__N32_PIN(115, APB2, D, 1),
__N32_PIN(116, APB2, D, 2),
__N32_PIN(117, APB2, D, 3),
__N32_PIN(118, APB2, D, 4),
__N32_PIN(119, APB2, D, 5),
__N32_PIN(97, APB2, A, 14),
__N32_PIN(98, APB2, A, 15),
__N32_PIN(99, APB2, C, 10),
__N32_PIN(100, APB2, C, 11),
__N32_PIN(101, APB2, C, 12),
__N32_PIN(102, APB2, D, 0),
__N32_PIN(103, APB2, D, 1),
__N32_PIN(104, APB2, D, 2),
__N32_PIN(105, APB2, D, 3),
__N32_PIN(106, APB2, D, 4),
__N32_PIN(107, APB2, D, 5),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(122, APB2, D, 6),
__N32_PIN(123, APB2, D, 7),
__N32_PIN(124, APB2, G, 9),
__N32_PIN(125, APB2, G, 10),
__N32_PIN(126, APB2, G, 11),
__N32_PIN(127, APB2, G, 12),
__N32_PIN(128, APB2, G, 13),
__N32_PIN(129, APB2, G, 14),
__N32_PIN(110, APB2, D, 6),
__N32_PIN(111, APB2, D, 7),
__N32_PIN(112, APB2, G, 4),
__N32_PIN(113, APB2, G, 5),
__N32_PIN(114, APB2, G, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(132, APB2, G, 15),
__N32_PIN(133, APB2, B, 3),
__N32_PIN(134, APB2, B, 4),
__N32_PIN(135, APB2, B, 5),
__N32_PIN(136, APB2, B, 6),
__N32_PIN(137, APB2, B, 7),
__N32_PIN(117, APB2, B, 3),
__N32_PIN(118, APB2, B, 4),
__N32_PIN(119, APB2, B, 5),
__N32_PIN(120, APB2, B, 6),
__N32_PIN(121, APB2, B, 7),
__N32_PIN_DEFAULT,
__N32_PIN(139, APB2, B, 8),
__N32_PIN(140, APB2, B, 9),
__N32_PIN(141, APB2, E, 0),
__N32_PIN(142, APB2, E, 1),
__N32_PIN(123, APB2, B, 8),
__N32_PIN(124, APB2, B, 9),
__N32_PIN(125, APB2, E, 0),
__N32_PIN(126, APB2, E, 1),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
#endif

7
bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
View File

@ -212,10 +212,6 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration
rt_uint64_t psc;
rt_uint32_t pulse;
/* Init timer pin and enable clock */
void n32_msp_tim_init(void *Instance);
n32_msp_tim_init(TIMx);
RCC_ClocksType RCC_Clock;
RCC_GetClocksFreqValue(&RCC_Clock);
rt_uint64_t input_clock;
@ -332,6 +328,9 @@ static int rt_hw_pwm_init(void)
if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device,
n32_pwm_obj[i].name, &drv_ops, &(n32_pwm_obj[i])) == RT_EOK)
{
/* Init timer pin and enable clock */
void n32_msp_tim_init(void *Instance);
n32_msp_tim_init(n32_pwm_obj[i].tim_handle);
}
else
{

102
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
View File

@ -477,6 +477,76 @@ void DMA1_Channel8_IRQHandler(void)
}
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
/* UART6 device driver structure */
struct n32_uart uart6 =
{
UART6,
UART6_IRQn,
{
DMA2_CH1,
DMA2,
DMA2_FLAG_GL1,
DMA2_Channel1_IRQn,
0,
},
};
struct rt_serial_device serial6;
void UART6_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial6);
/* leave interrupt */
rt_interrupt_leave();
}
void DMA2_Channel1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
dma_rx_done_isr(&serial6);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
/* UART7 device driver structure */
struct n32_uart uart7 =
{
UART7,
UART7_IRQn,
{
DMA2_CH6,
DMA2,
DMA2_FLAG_GL6,
DMA2_Channel6_IRQn,
0,
},
};
struct rt_serial_device serial7;
void UART7_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial7);
/* leave interrupt */
rt_interrupt_leave();
}
void DMA2_Channel6_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
dma_rx_done_isr(&serial7);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART7 */
static void NVIC_Configuration(struct n32_uart *uart)
{
NVIC_InitType NVIC_InitStructure;
@ -592,7 +662,7 @@ int rt_hw_usart_init(void)
serial4.ops = &n32_uart_ops;
serial4.config = config;
NVIC_Configuration(uart);
/* register UART3 device */
/* register UART4 device */
rt_hw_serial_register(&serial4, "uart4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
@ -605,12 +675,40 @@ int rt_hw_usart_init(void)
serial5.ops = &n32_uart_ops;
serial5.config = config;
NVIC_Configuration(uart);
/* register UART3 device */
/* register UART5 device */
rt_hw_serial_register(&serial5, "uart5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
uart);
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
uart = &uart6;
config.baud_rate = BAUD_RATE_115200;
serial6.ops = &n32_uart_ops;
serial6.config = config;
NVIC_Configuration(uart);
/* register UART6 device */
rt_hw_serial_register(&serial6, "uart6",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
uart);
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
uart = &uart7;
config.baud_rate = BAUD_RATE_115200;
serial7.ops = &n32_uart_ops;
serial7.config = config;
NVIC_Configuration(uart);
/* register UART7 device */
rt_hw_serial_register(&serial7, "uart7",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
uart);
#endif /* BSP_USING_UART7 */
return RT_EOK;
}

83
bsp/n32g452xx/n32g452xx-mini-system/.config
View File

@ -139,16 +139,16 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
@ -292,7 +292,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@ -326,14 +325,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
@ -341,7 +338,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# language packages
#
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
@ -354,15 +350,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
@ -378,13 +367,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
#
# tools packages
@ -427,39 +413,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
@ -469,7 +435,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_RT_USING_ARDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -478,6 +443,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
@ -494,13 +460,14 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_WCWIDTH is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_USB_STACK is not set
#
# peripheral libraries and drivers
@ -574,11 +541,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
#
# AI packages
@ -617,7 +581,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -639,11 +602,14 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_TERMBOX is not set
#
# Hardware Drivers Config
@ -658,14 +624,31 @@ CONFIG_BSP_USING_UART=y
#
# On-chip Peripheral Drivers
#
# CONFIG_N32G45X_PIN_NUMBERS_48 is not set
CONFIG_N32G45X_PIN_NUMBERS_64=y
# CONFIG_N32G45X_PIN_NUMBERS_100 is not set
# CONFIG_N32G45X_PIN_NUMBERS_128 is not set
CONFIG_N32G45X_PIN_NUMBERS=64
CONFIG_BSP_USING_GPIO=y
#
# Remap JTAG Port
#
# CONFIG_BSP_RMP_SW_JTAG_FULL_ENABLE is not set
# CONFIG_BSP_RMP_SW_JTAG_NO_NJTRST is not set
CONFIG_BSP_RMP_SW_JTAG_SW_ENABLE=y
# CONFIG_BSP_RMP_SW_JTAG_DISABLE is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART1_PIN_RMP is not set
CONFIG_BSP_USING_UART1_NO_RMP=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_HWTIMER is not set
# CONFIG_BSP_USING_SPI is not set

151
bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
View File

@ -19,10 +19,49 @@ endmenu
menu "On-chip Peripheral Drivers"
choice
prompt "Package of N32G45NXX chip:"
default N32G45X_PIN_NUMBERS_64
config N32G45X_PIN_NUMBERS_48
bool "LQFP48/TQFP48(QFN48 is not supported.)"
config N32G45X_PIN_NUMBERS_64
bool "LQFP64"
config N32G45X_PIN_NUMBERS_100
bool "LQFP100"
config N32G45X_PIN_NUMBERS_128
bool "LQFP128"
endchoice
config N32G45X_PIN_NUMBERS
int
range 0 128
default 48 if N32G45X_PIN_NUMBERS_48
default 64 if N32G45X_PIN_NUMBERS_64
default 100 if N32G45X_PIN_NUMBERS_100
default 128 if N32G45X_PIN_NUMBERS_128
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
if BSP_USING_GPIO
menu "Remap JTAG Port"
choice
prompt "Remap JTAG Port"
default BSP_RMP_SW_JTAG_SW_ENABLE
config BSP_RMP_SW_JTAG_FULL_ENABLE
bool "Full SWJ Enabled (JTAG-DP+SW-DP). No GPIO available."
config BSP_RMP_SW_JTAG_NO_NJTRST
bool "Full SWJ Enabled (JTAG-DP+SW-DP) without JTRST. PB4 available."
config BSP_RMP_SW_JTAG_SW_ENABLE
bool "JTAG-DP Disabled and SW-DP Enabled. PA15,PB3,PB4 available."
config BSP_RMP_SW_JTAG_DISABLE
bool "Full SWJ Disabled (JTAG-DP+SW-DP). PA13,PA14,PA15,PB3,PB4 available."
endchoice
endmenu
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
@ -39,25 +78,121 @@ menu "On-chip Peripheral Drivers"
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
bool "Enable USART1"
default y
if BSP_USING_UART1
choice
prompt "Select TX/RX Pin of USART1"
default BSP_USING_UART1_NO_RMP
config BSP_USING_UART1_PIN_RMP
bool "USART1(Remap):(TX:PB6,RX:PB7)"
config BSP_USING_UART1_NO_RMP
bool "USART1(Default):(TX:PA9,RX:PA10)"
endchoice
endif
config BSP_USING_UART2
bool "Enable UART2"
bool "Enable USART2"
default n
if BSP_USING_UART2
choice
prompt "Select TX/RX Pin of USART2"
default BSP_USING_UART2_NO_RMP
config BSP_USING_UART2_NO_RMP
bool "USART2(Default):(TX:PA2, RX:PA3)"
config BSP_USING_UART2_PIN_RMP1
bool "USART2:(TX:PD5, RX:PD6)"
config BSP_USING_UART2_PIN_RMP2
bool "USART2:(TX:PC8, RX:PC9)"
config BSP_USING_UART2_PIN_RMP3
bool "USART2:(TX:PB4, RX:PB5)"
endchoice
endif
config BSP_USING_UART3
bool "Enable UART3"
bool "Enable USART3"
default n
if BSP_USING_UART3
choice
prompt "Select TX/RX Pin of USART3"
default BSP_USING_UART3_PIN_NO_RMP
config BSP_USING_UART3_PIN_NO_RMP
bool "USART3:Default (TX:PB10, RX:PB11)"
config BSP_USING_UART3_PIN_PART_RMP
bool "USART3:Partial remap (TX:PC10, RX:PC11)"
config BSP_USING_UART3_PIN_ALL_RMP
bool "USART3:Full remap (TX:PD8, RX:PD9)"
endchoice
endif
config BSP_USING_UART4
bool "Enable UART4"
default n
if BSP_USING_UART4
choice
prompt "Select TX/RX Pin of UART4"
default BSP_USING_UART4_PIN_NORMP
config BSP_USING_UART4_PIN_NORMP
bool "UART4(Default):TX:PC10, RX:PC11"
config BSP_USING_UART4_PIN_RMP1
bool "UART4:TX:PB2, RX:PE7"
config BSP_USING_UART4_PIN_RMP2
bool "UART4:TX:PA13, RX:PA14"
config BSP_USING_UART4_PIN_RMP3
bool "UART4:TX:PD0, RX:PD1"
endchoice
endif
config BSP_USING_UART5
bool "Enable UART5"
default n
if BSP_USING_UART5
choice
prompt "Select TX/RX Pin of UART5"
default BSP_USING_UART5_PIN_NORMP
config BSP_USING_UART5_PIN_NORMP
bool "UART5(Default):TX:PC12, RX:PD2"
config BSP_USING_UART5_PIN_RMP1
bool "UART5:TX:PB13, RX:PB14"
config BSP_USING_UART5_PIN_RMP2
bool "UART5:TX:PE8, RX:PE9"
config BSP_USING_UART5_PIN_RMP3
bool "UART5:TX:PB8, RX:PB9"
endchoice
endif
config BSP_USING_UART6
bool "Enable UART6"
default n
if BSP_USING_UART6
choice
prompt "Select TX/RX Pin of UART6"
default BSP_USING_UART6_PIN_NORMP
config BSP_USING_UART6_PIN_NORMP
bool "UART6(Default):TX:PE2, RX:PE3"
config BSP_USING_UART6_PIN_RMP2
bool "UART6:TX:PC0, RX:PC1"
config BSP_USING_UART6_PIN_RMP3
bool "UART6:TX:PB0, RX:PB1"
endchoice
endif
config BSP_USING_UART7
bool "Enable UART7"
default n
if BSP_USING_UART7
choice
prompt "Select TX/RX Pin of UART7"
default BSP_USING_UART7_PIN_NORMP
config BSP_USING_UART7_PIN_NORMP
bool "UART7(Default):TX:PC4, RX:PC5"
config BSP_USING_UART7_PIN_RMP1
bool "UART7:TX:PC2, RX:PC3"
config BSP_USING_UART7_PIN_RMP3
bool "UART7:TX:PG0, RX:PG1"
endchoice
endif
endif
menuconfig BSP_USING_PWM
@ -213,13 +348,13 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 63
default 22
int "I2C1 scl pin number"
range 1 N32G45X_PIN_NUMBERS
default 29
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 63
default 23
range 1 N32G45X_PIN_NUMBERS
default 30
endif
menuconfig BSP_USING_ADC

1
bsp/n32g452xx/n32g452xx-mini-system/board/board.c
View File

@ -76,6 +76,7 @@ void rt_hw_board_init()
#ifdef RT_USING_PIN
int n32_hw_pin_init(void);
n32_hw_pin_init();
n32_msp_jtag_init(RT_NULL);
#endif
#ifdef RT_USING_SERIAL

2
bsp/n32g452xx/n32g452xx-mini-system/board/board.h
View File

@ -25,7 +25,7 @@ extern "C" {
#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <80>, Default: 80*/
#define N32_SRAM_SIZE (80)
#define N32_SRAM_SIZE (144)
#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
#if defined(__ARMCC_VERSION)

318
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
View File

@ -27,58 +27,283 @@ void n32_msp_usart_init(void *Instance)
if (USART1 == USARTx)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
#ifdef BSP_USING_UART1_PIN_RMP
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP_USART1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_6;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_7;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
}
#endif
}
#endif /* BSP_USING_UART1 */
#ifdef BSP_USING_UART2
if (USART2 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
#ifdef BSP_USING_UART2_PIN_RMP1
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP1_USART2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_6;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
#elif defined (BSP_USING_UART2_PIN_RMP2)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMCP2_USART2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#elif defined (BSP_USING_UART2_PIN_RMP3)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP3_USART2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
}
#endif
}
#endif /* BSP_USING_UART2 */
#ifdef BSP_USING_UART3
if (USART3 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
#if defined(BSP_USING_UART3_PIN_PART_RMP)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_PART_RMP_USART3, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_11;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART3_PIN_ALL_RMP)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_ALL_RMP_USART3, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_11;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
}
#endif
}
#endif /* BSP_USING_UART3 */
#ifdef BSP_USING_UART4
if (UART4 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
#if defined(BSP_USING_UART4_PIN_RMP1)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP1_UART4, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_GPIOE, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_7;
GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART4_PIN_RMP2)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP2_UART4, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_14;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART4_PIN_RMP3)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP3_UART4, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_11;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
}
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#endif
}
#endif /* BSP_USING_UART4 */
#ifdef BSP_USING_UART5
if (UART5 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE);
#if defined(BSP_USING_UART5_PIN_RMP1)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP1_UART5, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_14;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART5_PIN_RMP2)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP2_UART5, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART5_PIN_RMP3)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP3_UART5, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_GPIOD, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_12;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
#endif
}
#endif /* BSP_USING_UART5 */
#ifdef BSP_USING_UART6
if (UART6 == USARTx)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART6, ENABLE);
#if defined(BSP_USING_UART6_PIN_RMP2)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP2_UART6, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART6_PIN_RMP3)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP3_UART6, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
#else /* BSP_USING_UART6_PIN_NORMP */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
#endif
}
#endif /* BSP_USING_UART6 */
#ifdef BSP_USING_UART7
if (UART7 == USARTx)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART7, ENABLE);
#if defined(BSP_USING_UART7_PIN_RMP1)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP1_UART7, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#elif defined(BSP_USING_UART7_PIN_RMP3)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP3_UART7, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
GPIO_InitPeripheral(GPIOG, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
GPIO_InitPeripheral(GPIOG, &GPIO_InitCtlStruct);
#else /* BSP_USING_UART7_PIN_NORMP */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#endif
}
#endif /* BSP_USING_UART7 */
/* Add others */
}
#endif /* BSP_USING_SERIAL */
@ -113,7 +338,6 @@ void n32_msp_spi_init(void *Instance)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_12;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
@ -167,7 +391,7 @@ void n32_msp_tim_init(void *Instance)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_11;
GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11;
GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
@ -244,7 +468,7 @@ void n32_msp_adc_init(void *Instance)
/* Configure ADC Channel as analog input */
GPIO_InitCtlStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitCtlStruct.GPIO_Speed = GPIO_INPUT;
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
}
@ -260,7 +484,7 @@ void n32_msp_adc_init(void *Instance)
/* Configure ADC Channel as analog input */
GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitCtlStruct.GPIO_Speed = GPIO_INPUT;
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
}
@ -341,21 +565,73 @@ void n32_msp_can_init(void *Instance)
if (CAN2 == CANx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
// GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_6;
GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
GPIO_InitCtlStruct.Pin = GPIO_PIN_12;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
}
#endif
}
#endif /* BSP_USING_CAN */
void n32_msp_jtag_init(void *Instance)
{
GPIO_InitType GPIO_InitCtlStruct;
GPIO_InitStruct(&GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
#if defined(BSP_RMP_SW_JTAG_NO_NJTRST)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_NO_NJTRST, ENABLE);
/* Available pin: PB4 */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
#elif defined(BSP_RMP_SW_JTAG_SW_ENABLE)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE);
/* Available pin: PB3, PB4, PA15 */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_OD;
GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitCtlStruct.Pin = GPIO_PIN_15;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
#elif defined(BSP_RMP_SW_JTAG_DISABLE)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_DISABLE, ENABLE);
/* Available pin: PB3, PB4, PA13, PA14, PA15 */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_OD;
GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
GDPIO_InitCtlStruct.Pin = GPIO_PIN_4;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPD;
GPIO_InitCtlStruct.Pin = GPIO_PIN_14;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitCtlStruct.Pin = GPIO_PIN_15;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
#else
return;
#endif
}
#ifdef RT_USING_FINSH
#include <finsh.h>
#if defined(BSP_USING_UART2) || defined(BSP_USING_UART3)
@ -413,7 +689,7 @@ static int adc_vol_sample(int argc, char *argv[])
return RT_ERROR;
}
for (int i = 6; i <= 9; ++i)
for (int i = 1; i <= 18; ++i)
{
ret = rt_adc_enable(adc_dev, i);
value = rt_adc_read(adc_dev, i);

1
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h
View File

@ -18,6 +18,7 @@ void n32_msp_sdio_init(void *Instance);
void n32_msp_adc_init(void *Instance);
void n32_msp_hwtim_init(void *Instance);
void n32_msp_can_init(void *Instance);
void n32_msp_jtag_init(void *Instance);
#endif /* __N32_MSP_H__ */

28
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
View File

@ -76,6 +76,12 @@
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
/* Device Drivers */
@ -85,9 +91,6 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_ADC
#define RT_USING_PWM
#define RT_USING_WDT
/* Using USB */
@ -157,26 +160,14 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* POSIX extension functions */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
@ -204,7 +195,14 @@
/* On-chip Peripheral Drivers */
#define N32G45X_PIN_NUMBERS_64
#define N32G45X_PIN_NUMBERS 64
#define BSP_USING_GPIO
/* Remap JTAG Port */
#define BSP_RMP_SW_JTAG_SW_ENABLE
#define BSP_USING_UART1
#define BSP_USING_UART1_NO_RMP
#endif