From 60c6a878bfe240bf777b34b47221e2408b6eeaec Mon Sep 17 00:00:00 2001 From: FuChao Date: Wed, 8 Sep 2021 13:02:13 +0800 Subject: [PATCH] =?UTF-8?q?=E6=96=B0=E5=A2=9E=E5=AF=B9MDK5=E7=9A=84?= =?UTF-8?q?=E7=BC=96=E8=AF=91=E6=94=AF=E6=8C=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../CMSIS/Vango/V85xx/Source/lib_CodeRAM.c | 35 + .../CMSIS/Vango/V85xx/Source/lib_LoadNVR.c | 648 +++++++++++++ .../CMSIS/Vango/V85xx/Source/lib_cortex.c | 175 ++++ bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h | 894 ++++++++++++++++++ bsp/Vango_V85xx/drivers/board.h | 15 +- 5 files changed, 1765 insertions(+), 2 deletions(-) create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c new file mode 100644 index 0000000000..59af288800 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c @@ -0,0 +1,35 @@ +/** + ****************************************************************************** + * @file lib_CodeRAM.c + * @author Application Team + * @version V4.4.0 + * @date 2019-01-18 + * @brief Codes executed in SRAM. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_CodeRAM.h" + +#ifndef __GNUC__ +/** + * @brief Flash deep standby, enter idle mode. + * @note This function is executed in RAM. + * @param None + * @retval None + */ +__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void) +{ + /* Flash deep standby */ + FLASH->PASS = 0x55AAAA55; + FLASH->DSTB = 0xAA5555AA; + /* Enter Idle mode */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + __WFI(); +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c new file mode 100644 index 0000000000..d75753b048 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c @@ -0,0 +1,648 @@ +/** + ****************************************************************************** + * @file lib_LoadNVR.c + * @author Application Team + * @version V4.7.0 + * @date 2019-12-12 + * @brief Load information from NVR. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_LoadNVR.h" + + +/** + * @breif Load Analog trim data from NVR manually. + * @note Successful Operation: + * - Load [0x40DC0] or [0x40DD0] to ANA registers(B C D E), return 0. + * Operation failed: + * - return 1. + * @param None + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_LoadANADataManual(void) +{ + uint32_t checksum; + uint32_t op_reg; + uint32_t ana_data; + uint32_t key_reg = 0xFFFFFFFF; + + /* Get Analog data1 */ + ana_data = *NVR_ANA_TRIMDATA1; + op_reg = *NVR_ANA_OPREG1; + /* Calculate checksum1 */ + checksum = ~(ana_data + op_reg + key_reg); + /* Compare checksum1 */ + if (checksum == (*NVR_ANA_CHECKSUM1)) + { + ANA->REGB = (uint8_t)(ana_data); + ANA->REGC = (uint8_t)(ana_data >> 8); + ANA->REGD = (uint8_t)(ana_data >> 16); + ANA->REGE = (uint8_t)(ana_data >> 24); + return 0; + } + + /* Get Analog data2 */ + ana_data = *NVR_ANA_TRIMDATA2; + op_reg = *NVR_ANA_OPREG2; + /* Calculate checksum2 */ + checksum = ~(ana_data + op_reg + key_reg); + /* Compare checksum2 */ + if (checksum == (*NVR_ANA_CHECKSUM2)) + { + ANA->REGB = (uint8_t)(ana_data); + ANA->REGC = (uint8_t)(ana_data >> 8); + ANA->REGD = (uint8_t)(ana_data >> 16); + ANA->REGE = (uint8_t)(ana_data >> 24); + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Get the parameters of ADC voltage measuring. + * @note Voltage(unit:V) = aParameter*ADC_DATA + bParameter + * ADC_DATA: ADC channel original data + * aParameter/bParameter: Get from this function + * @param [in]Mode: + * NVR_3V_EXTERNAL_NODIV + * NVR_3V_EXTERNAL_RESDIV + * NVR_3V_EXTERNAL_CAPDIV + * NVR_3V_VDD_RESDIV + * NVR_3V_VDD_CAPDIV + * NVR_3V_BATRTC_RESDIV + * NVR_3V_BATRTC_CAPDIV + * NVR_5V_EXTERNAL_NODIV + * NVR_5V_EXTERNAL_RESDIV + * NVR_5V_EXTERNAL_CAPDIV + * NVR_5V_VDD_RESDIV + * NVR_5V_VDD_CAPDIV + * NVR_5V_BATRTC_RESDIV + * NVR_5V_BATRTC_CAPDIV + * @param [out]Parameter: The parameters get from NVR + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter) +{ + uint32_t checksum; + uint32_t i; + int32_t tmp_int; + + /* Check the parameters */ + assert_parameters(IS_NVR_ADCVOL_MODE(Mode)); + + /*----- Power supply: 5V -----*/ + if (0x100UL & Mode) + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_5VPARA_BASEADDR1+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VPARA_BASEADDR1+i)) /* Checksum1 error */ + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_5VPARA_BASEADDR2+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VPARA_BASEADDR2+i)) /* Checksum2 error */ + { + return 1; + } + else + { + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } + else + { + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } + /*----- Power supply: 3.3V -----*/ + else + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_3VPARA_BASEADDR1+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VPARA_BASEADDR1+i)) /* Checksum1 error */ + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_3VPARA_BASEADDR2+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VPARA_BASEADDR2+i)) /* Checksum2 error */ + { + return 1; + } + else + { + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } + else + { + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } +} + +/** + * @breif Get BAT Measure result. + * @param [out]MEAResult The pointer to struct NVR_BATMEARES. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult) +{ + uint32_t bat_r; + uint32_t bat_c; + uint32_t checksum; + + bat_r = *NVR_BAT_R1; + bat_c = *NVR_BAT_C1; + /* Calculate checksum1 */ + checksum = ~(bat_r + bat_c); + if (checksum == (*NVR_BATMEA_CHECHSUM1)) + { + MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0); + MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0); + return 0; + } + + bat_r = *NVR_BAT_R2; + bat_c = *NVR_BAT_C2; + /* Calculate checksum2 */ + checksum = ~(bat_r + bat_c); + if (checksum == (*NVR_BATMEA_CHECHSUM2)) + { + MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0); + MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0); + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Load RTC ACPx pramameters from NVR to RTC registers. + Get RTC pramameters. + * @param [out]RTCTempData The pointer to struct NVR_RTCINFO. + * @retval 0: Function succeeded. + !0: Function not succeeded, load default value to registers. + bit[0]=1: Temperature Measure delta information checksum error, default value is 0. + bit[1]=1: P paramters checksum error, default value as follows + [P0]-214, [P1]1060, [P2]-19746971, [P5]6444, [P6]1342, [P7]0 + bit[2]=1: P4 checksum error, default value is 0 + bit[3]=1: ACKx checksum error, default value as follows + [K1]20827, [K2]21496, [K3]22020, [K4]24517, [K5]25257 + bit[4]=1: ACTI checksum error, default value is 0x1800(24.0) + bit[5]=1: ACKTEMP checksum error, defalut value is 0x3C2800EC + */ +uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData) +{ + uint32_t real_temp, mea_temp; + uint32_t rtc_data1, rtc_data2, rtc_data3, rtc_data4; + uint32_t rtc_p4; + uint32_t rtc_ack[5]; + uint32_t rtc_acti; + uint32_t rtc_acktemp; + uint32_t checksum; + float pclk_mul; + + int16_t TempDelta; + uint32_t retval = 0; + +/*------------------------ Temperature Measure delta -------------------------*/ + real_temp = *NVR_REALTEMP1; + mea_temp = *NVR_MEATEMP1; + /* Calculate checksum1 */ + checksum = ~(real_temp + mea_temp); + if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true + { + TempDelta = (int16_t)real_temp - (int16_t)mea_temp; + } + else + { + real_temp = *NVR_REALTEMP2; + mea_temp = *NVR_MEATEMP2; + /* Calculate checksum2 */ + checksum = ~(real_temp + mea_temp); + if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true + { + TempDelta = (int16_t)real_temp - (int16_t)mea_temp; + } + else + { + TempDelta = 0; + retval |= BIT0; + } + } + /* Get Measure delta information */ + RTCTempData->RTCTempDelta = TempDelta; + +/*------------------------------ P parameters --------------------------------*/ + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Get PCLK */ + RTCTempData->APBClock = CLK_GetPCLKFreq(); + pclk_mul = RTCTempData->APBClock / 6553600.0; + + rtc_data1 = *NVR_RTC1_P1_P0; + rtc_data2 = *NVR_RTC1_P2; + rtc_data3 = *NVR_RTC1_P5_P4; + rtc_data4 = *NVR_RTC1_P7_P6; + /* Calculate checksum1 */ + checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4); + if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true + { + /* Get information */ + RTCTempData->RTCTempP0 = (int16_t)(rtc_data1); + RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16); + RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16); + RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul); + RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16); + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF); + RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF); + RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF); + RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul)); + RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF); + } + else + { + rtc_data1 = *NVR_RTC2_P1_P0; + rtc_data2 = *NVR_RTC2_P2; + rtc_data3 = *NVR_RTC2_P5_P4; + rtc_data4 = *NVR_RTC2_P7_P6; + /* Calculate checksum2 */ + checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4); + if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true + { + /* Get information */ + RTCTempData->RTCTempP0 = (int16_t)(rtc_data1); + RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16); + RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16); + RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul); + RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16); + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF); + RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF); + RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF); + RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul)); + RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF); + } + else + { + /* Get information */ + RTCTempData->RTCTempP0 = -214; + RTCTempData->RTCTempP1 = 1060; + RTCTempData->RTCTempP2 = -19746971 + (TempDelta*256); + RTCTempData->RTCTempP5 = 6444; + RTCTempData->RTCTempP6 = (uint32_t)((int32_t)(1342*pclk_mul)); + RTCTempData->RTCTempP7 = 0; + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(-214); + RTC->ACP1 = (uint16_t)(1060); + RTC->ACP2 = (uint32_t)(-19746971 + (TempDelta*256)); + RTC->ACP5 = (uint16_t)(6444); + RTC->ACP6 = (uint16_t)((int32_t)(1342*pclk_mul)); + RTC->ACP7 = (uint16_t)(0); + + retval |= BIT1; + } + } + +/*----------------------------------- P4 -------------------------------------*/ + /* Calculate checksum1 */ + rtc_p4 = *NVR_RTC1_P4; + checksum = ~rtc_p4; + if (checksum == (*NVR_RTC1_P4_CHKSUM))//checksum1 true + { + /* Get information */ + RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4); + RTC->ACP4 = *NVR_RTC1_P4; + } + else + { + rtc_p4 = *NVR_RTC2_P4; + checksum = ~rtc_p4; + if (checksum == (*NVR_RTC2_P4_CHKSUM))//checksum2 true + { + /* Get information */ + RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4); + RTC->ACP4 = *NVR_RTC1_P4; + } + else + { + RTCTempData->RTCTempP4 = 0; + RTC->ACP4 = 0; + + retval |= BIT2; + } + } + +/*-------------------------- RTC ACKx parameters -----------------------------*/ + rtc_ack[0] = *NVR_RTC1_ACK1; + rtc_ack[1] = *NVR_RTC1_ACK2; + rtc_ack[2] = *NVR_RTC1_ACK3; + rtc_ack[3] = *NVR_RTC1_ACK4; + rtc_ack[4] = *NVR_RTC1_ACK5; + checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]); + if (checksum == (*NVR_RTC1_ACK_CHKSUM))//checksum1 true + { + /* Get information */ + RTCTempData->RTCTempK1 = rtc_ack[0]; + RTCTempData->RTCTempK2 = rtc_ack[1]; + RTCTempData->RTCTempK3 = rtc_ack[2]; + RTCTempData->RTCTempK4 = rtc_ack[3]; + RTCTempData->RTCTempK5 = rtc_ack[4]; + + /* Load data to ACKx register */ + RTC->ACK1 = rtc_ack[0]; + RTC->ACK2 = rtc_ack[1]; + RTC->ACK3 = rtc_ack[2]; + RTC->ACK4 = rtc_ack[3]; + RTC->ACK5 = rtc_ack[4]; + } + else + { + rtc_ack[0] = *NVR_RTC2_ACK1; + rtc_ack[1] = *NVR_RTC2_ACK2; + rtc_ack[2] = *NVR_RTC2_ACK3; + rtc_ack[3] = *NVR_RTC2_ACK4; + rtc_ack[4] = *NVR_RTC2_ACK5; + checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]); + if (checksum == (*NVR_RTC2_ACK_CHKSUM))//checksum2 true + { + /* Get information */ + RTCTempData->RTCTempK1 = rtc_ack[0]; + RTCTempData->RTCTempK2 = rtc_ack[1]; + RTCTempData->RTCTempK3 = rtc_ack[2]; + RTCTempData->RTCTempK4 = rtc_ack[3]; + RTCTempData->RTCTempK5 = rtc_ack[4]; + + /* Load data to ACKx register */ + RTC->ACK1 = rtc_ack[0]; + RTC->ACK2 = rtc_ack[1]; + RTC->ACK3 = rtc_ack[2]; + RTC->ACK4 = rtc_ack[3]; + RTC->ACK5 = rtc_ack[4]; + } + else + { + /* Get information */ + RTCTempData->RTCTempK1 = 20827; + RTCTempData->RTCTempK2 = 21496; + RTCTempData->RTCTempK3 = 22020; + RTCTempData->RTCTempK4 = 24517; + RTCTempData->RTCTempK5 = 25257; + + /* Load data to ACKx register */ + RTC->ACK1 = 20827; + RTC->ACK2 = 21496; + RTC->ACK3 = 22020; + RTC->ACK4 = 24517; + RTC->ACK5 = 25257; + + retval |= BIT3; + } + } + +/*-------------------------- RTC ACTI parameters -----------------------------*/ + rtc_acti = *NVR_RTC1_ACTI; + checksum = ~rtc_acti; + if (checksum == (*NVR_RTC1_ACTI_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACTI = rtc_acti; + /* Load data to ACKx register */ + RTC->ACTI = rtc_acti; + } + else + { + rtc_acti = *NVR_RTC2_ACTI; + checksum = ~rtc_acti; + if (checksum == (*NVR_RTC2_ACTI_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACTI = rtc_acti; + /* Load data to ACKx register */ + RTC->ACTI = rtc_acti; + } + else + { + /* Get information */ + RTCTempData->RTCACTI = 0x1800; + RTC->ACTI = 0x1800; + + retval |= BIT4; + } + } + +/*------------------------- RTC ACKTemp parameters ---------------------------*/ + rtc_acktemp = *NVR_RTC1_ACKTEMP; + checksum = ~rtc_acktemp; + if (checksum == (*NVR_RTC1_ACKTEMP_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACKTemp = rtc_acktemp; + /* Load data to ACKx register */ + RTC->ACKTEMP = rtc_acktemp; + } + else + { + rtc_acktemp = *NVR_RTC2_ACKTEMP; + checksum = ~rtc_acktemp; + if (checksum == (*NVR_RTC2_ACKTEMP_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACKTemp = rtc_acktemp; + /* Load data to ACKx register */ + RTC->ACKTEMP = rtc_acktemp; + } + else + { + /* Get information */ + RTCTempData->RTCACKTemp = 0x3C2800EC; + RTC->ACKTEMP = 0x3C2800EC; + + retval |= BIT5; + } + } +/*--------------------------------- ACF200 -----------------------------------*/ + RTCTempData->RTCACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000)); + RTC->ACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000)); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + return retval; +} + +/** + * @breif Get Power/Clock Measure result. + * @param [out]MEAResult The pointer to struct NVR_PWRMEARES. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult) +{ + uint32_t avcc_data, dvcc_data, bgp_data, rcl_data, rch_data; + uint32_t checksum; + + avcc_data = *NVR_AVCC_MEA1; + dvcc_data = *NVR_DVCC_MEA1; + bgp_data = *NVR_BGP_MEA1; + rcl_data = *NVR_RCL_MEA1; + rch_data = *NVR_RCH_MEA1; + /* Calculate checksum1 */ + checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data); + if (checksum == (*NVR_PWR_CHECKSUM1)) + { + MEAResult->AVCCMEAResult = avcc_data; + MEAResult->DVCCMEAResult = dvcc_data; + MEAResult->BGPMEAResult = bgp_data; + MEAResult->RCLMEAResult = rcl_data; + MEAResult->RCHMEAResult = rch_data; + return 0; + } + + avcc_data = *NVR_AVCC_MEA2; + dvcc_data = *NVR_DVCC_MEA2; + bgp_data = *NVR_BGP_MEA2; + rcl_data = *NVR_RCL_MEA2; + rch_data = *NVR_RCH_MEA2; + /* Calculate checksum2 */ + checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data); + if (checksum == (*NVR_PWR_CHECKSUM2)) + { + MEAResult->AVCCMEAResult = avcc_data; + MEAResult->DVCCMEAResult = dvcc_data; + MEAResult->BGPMEAResult = bgp_data; + MEAResult->RCLMEAResult = rcl_data; + MEAResult->RCHMEAResult = rch_data; + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Get Chip ID. + * @param [out]ChipID The pointer to struct NVR_CHIPID. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetChipID(NVR_CHIPID *ChipID) +{ + uint32_t id0, id1; + uint32_t checksum; + + id0 = *NVR_CHIP1_ID0; + id1 = *NVR_CHIP1_ID1; + /* Calculate checksum1 */ + checksum = ~(id0 + id1); + if (checksum == (*NVR_CHIP1_CHECKSUM)) + { + ChipID->ChipID0 = id0; + ChipID->ChipID1 = id1; + return 0; + } + + id0 = *NVR_CHIP2_ID0; + id1 = *NVR_CHIP2_ID1; + /* Calculate checksum2 */ + checksum = ~(id0 + id1); + if (checksum == (*NVR_CHIP2_CHECKSUM)) + { + ChipID->ChipID0 = id0; + ChipID->ChipID1 = id1; + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Get LCD information. + * @param [out]LCDInfo The pointer to struct NVR_LCDINFO. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo) +{ + uint32_t lcd_ldo, lcd_vol; + uint32_t checksum; + + lcd_ldo = *NVR_LCD_LDO1; + lcd_vol = *NVR_LCD_VOL1; + /* Calculate checksum1 */ + checksum = ~(lcd_ldo + lcd_vol); + if (checksum == (*NVR_LCD_CHECKSUM1)) + { + LCDInfo->MEALCDLDO = lcd_ldo; + LCDInfo->MEALCDVol = lcd_vol; + return 0; + } + + lcd_ldo = *NVR_LCD_LDO2; + lcd_vol = *NVR_LCD_VOL2; + /* Calculate checksum2 */ + checksum = ~(lcd_ldo + lcd_vol); + if (checksum == (*NVR_LCD_CHECKSUM2)) + { + LCDInfo->MEALCDLDO = lcd_ldo; + LCDInfo->MEALCDVol = lcd_vol; + return 0; + } + else + { + return 1; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c new file mode 100644 index 0000000000..552365ff6e --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file lib_cortex.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Cortex module driver. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_cortex.h" +#include "core_cm0.h" + +/** + * @brief 1. Clears Pending of a device specific External Interrupt. + * 2. Sets Priority of a device specific External Interrupt. + * 3. Enables a device specific External Interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to target.h file) + * @param Priority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @retval None + */ +void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority)); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(IRQn); + /* Set Interrupt Priority */ + NVIC_SetPriority(IRQn, Priority); + /* Enable Interrupt in NVIC */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly before calling it. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Enable interrupt in NVIC */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Disable interrupt in NVIC */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void CORTEX_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Gets the Pending bit of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval 0 Interrupt status is not pending. + 1 Interrupt status is pending. + */ +uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Get priority for Cortex-M0 system or device specific interrupts */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Clear interrupt pending */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval Interrupt Priority. Value is aligned automatically to the implemented + * priority bits of the microcontroller. + */ +uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M0 system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to target.h file) + * @param Priority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @retval None + */ +void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority)); + /* Get priority for Cortex-M0 system or device specific interrupts */ + NVIC_SetPriority(IRQn, Priority); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum) +{ + return SysTick_Config(TicksNum); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/Vango_V85xx/drivers/board.h b/bsp/Vango_V85xx/drivers/board.h index b945ad59ef..a48528df35 100644 --- a/bsp/Vango_V85xx/drivers/board.h +++ b/bsp/Vango_V85xx/drivers/board.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-01-04 iysheng first version + * 2021-09-07 FuC Suit for Vango V85xx */ #ifndef __BOARD_H__ @@ -15,11 +16,21 @@ #include "drv_gpio.h" -#define V85XX_SRAM_SIZE 48 +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 32*/ +#define V85XX_SRAM_SIZE 32 #define V85XX_SRAM_END (0x20000000 + V85XX_SRAM_SIZE * 1024) +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + #define HEAP_END V85XX_SRAM_END