[bsp][stm32f429-disco] Fix assertion failed at function:rt_malloc
This commit is contained in:
xuzhuoyi
parent
119da5b035
commit
5f0102865d
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@ -17,9 +17,9 @@ src += Glob('STM32F4xx_HAL_Driver/Src/*.c')
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if rtconfig.CROSS_TOOL == 'gcc':
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src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s']
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elif rtconfig.CROSS_TOOL == 'keil':
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src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s']
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src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s']
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elif rtconfig.CROSS_TOOL == 'iar':
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src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s']
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src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s']
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path = [cwd + '/STM32F4xx_HAL_Driver/Inc',
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cwd + '/CMSIS/Device/ST/STM32F4xx/Include',
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@ -20,6 +20,11 @@
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#include "usart.h"
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#include "stm32f4xx_hal.h"
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void _init(void)
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{
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}
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/**
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* @brief This function is executed in case of error occurrence.
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* @param None
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@ -76,6 +76,8 @@ void rt_hw_board_init(void);
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#define FINSH_DEVICE_NAME CONSOLE_DEVICE
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void Error_Handler(void);
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#endif
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// <<< Use Configuration Wizard in Context Menu >>>
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@ -26,13 +26,193 @@
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#include "drv_sdram.h"
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#include "stm32f4xx_ll_fmc.h"
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#include <rtdevice.h>
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#include "board.h"
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SDRAM_HandleTypeDef hsdram1;
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FMC_SDRAM_CommandTypeDef command;
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/**
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* @brief SDRAM MSP Initialization
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* This function configures the hardware resources used in this example:
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* - Peripheral's clock enable
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* - Peripheral's GPIO Configuration
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* @param hsdram: SDRAM handle pointer
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* @retval None
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*/
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void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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{
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GPIO_InitTypeDef GPIO_Init_Structure;
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#ifndef USE_Delay
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static void delay(__IO uint32_t nCount);
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#endif /* USE_Delay*/
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/*##-1- Enable peripherals and GPIO Clocks #################################*/
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/* Enable GPIO clocks */
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/*##-2- Configure peripheral GPIO ##########################################*/
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/*
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+-------------------+--------------------+--------------------+--------------------+
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+ SDRAM pins assignment +
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+-------------------+--------------------+--------------------+--------------------+
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| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
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| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
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| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
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| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
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| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
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| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
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| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
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+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
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| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
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| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
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| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
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+-------------------+--------------------+--------------------+
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| PB5 <-> FMC_SDCKE1|
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| PB6 <-> FMC_SDNE1 |
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| PC0 <-> FMC_SDNWE |
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+-------------------+
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*/
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/* Common GPIO configuration */
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GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
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GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
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GPIO_Init_Structure.Pull = GPIO_NOPULL;
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GPIO_Init_Structure.Alternate = GPIO_AF12_FMC;
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/* GPIOB configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_5 | GPIO_PIN_6;
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HAL_GPIO_Init(GPIOB, &GPIO_Init_Structure);
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/* GPIOC configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0;
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HAL_GPIO_Init(GPIOC, &GPIO_Init_Structure);
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/* GPIOD configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 |
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure);
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/* GPIOE configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 |
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GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure);
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/* GPIOF configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
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GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 |
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure);
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/* GPIOG configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure);
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}
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/**
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* @brief SDRAM MSP De-Initialization
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* This function frees the hardware resources used in this example:
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* - Disable the Peripheral's clock
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* - Revert GPIO configuration to their default state
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* @param hsdram: SDRAM handle pointer
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* @retval None
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*/
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void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
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{
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/*## Disable peripherals and GPIO Clocks ###################################*/
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5 | GPIO_PIN_6);
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HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0);
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HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 |\
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 |\
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GPIO_PIN_15);
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HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 |\
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GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |\
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
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GPIO_PIN_14 | GPIO_PIN_15);
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HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |\
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GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 |\
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
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GPIO_PIN_14 | GPIO_PIN_15);
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HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
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}
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/**
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* @brief Perform the SDRAM exernal memory inialization sequence
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* @param hsdram: SDRAM handle
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* @param Command: Pointer to SDRAM command structure
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* @retval None
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*/
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static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
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{
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__IO uint32_t tmpmrd =0;
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/* Step 3: Configure a clock configuration enable command */
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Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 4: Insert 100 ms delay */
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/* interrupt is not enable, just to delay some time. */
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for (tmpmrd = 0; tmpmrd < 0xfffff; tmpmrd ++)
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;
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/* Step 5: Configure a PALL (precharge all) command */
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Command->CommandMode = FMC_SDRAM_CMD_PALL;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 6 : Configure a Auto-Refresh command */
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Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command->AutoRefreshNumber = 4;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 7: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 8: Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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/* Set the device refresh counter */
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HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
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}
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/**
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* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
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@ -43,36 +223,49 @@ static void delay(__IO uint32_t nCount);
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*/
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void SDRAM_Init(void)
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{
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FMC_SDRAM_TimingTypeDef SdramTiming;
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FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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/** Perform the SDRAM1 memory initialization sequence
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*/
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/*##-1- Configure the SDRAM device #########################################*/
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/* SDRAM device configuration */
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hsdram1.Instance = FMC_SDRAM_DEVICE;
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/* hsdram1.Init */
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hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_11;
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hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
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hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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/* SdramTiming */
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SdramTiming.LoadToActiveDelay = 16;
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SdramTiming.ExitSelfRefreshDelay = 16;
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SdramTiming.SelfRefreshTime = 16;
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SdramTiming.RowCycleDelay = 16;
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SdramTiming.WriteRecoveryTime = 16;
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SdramTiming.RPDelay = 16;
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SdramTiming.RCDDelay = 16;
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if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
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/* Timing configuration for 90 MHz of SD clock frequency (180MHz/2) */
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/* TMRD: 2 Clock cycles */
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SDRAM_Timing.LoadToActiveDelay = 2;
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/* TXSR: min=70ns (6x11.90ns) */
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SDRAM_Timing.ExitSelfRefreshDelay = 7;
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/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
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SDRAM_Timing.SelfRefreshTime = 4;
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/* TRC: min=63 (6x11.90ns) */
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SDRAM_Timing.RowCycleDelay = 7;
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/* TWR: 2 Clock cycles */
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SDRAM_Timing.WriteRecoveryTime = 2;
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/* TRP: 15ns => 2x11.90ns */
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SDRAM_Timing.RPDelay = 2;
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/* TRCD: 15ns => 2x11.90ns */
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SDRAM_Timing.RCDDelay = 2;
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hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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hsdram1.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
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hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram1.Init.SDClockPeriod = SDCLOCK_PERIOD;
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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/* Initialize the SDRAM controller */
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if(HAL_SDRAM_Init(&hsdram1, &SDRAM_Timing) != HAL_OK)
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{
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/* Initialization Error */
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Error_Handler();
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}
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/* Program the SDRAM external device */
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SDRAM_Initialization_Sequence(&hsdram1, &command);
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}
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rt_err_t sdram_hw_init(void)
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@ -25,57 +25,16 @@
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#include <board.h>
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#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
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#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
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/**
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* @brief FMC SDRAM Memory Width
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*/
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/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
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#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
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/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
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#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
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/**
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* @brief FMC SDRAM CAS Latency
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*/
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/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
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#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
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/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 */
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#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3
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/**
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* @brief FMC SDRAM Memory clock period
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*/
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#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
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/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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/**
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* @brief FMC SDRAM Memory Read Burst feature
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*/
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#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
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/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
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/**
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* @brief FMC SDRAM Bank Remap
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*/
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/* #define SDRAM_BANK_REMAP */
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/**
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* @brief Uncomment the line below if you want to use user defined Delay function
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* (for precise timing), otherwise default _delay_ function defined within
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* this driver is used (less precise timing).
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*/
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/* #define USE_Delay */
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#ifdef USE_Delay
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#define __Delay Delay /* User can provide more timing precise __Delay function
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(with 10ms time base), using SysTick for example */
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#else
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#define __Delay delay /* Default __Delay function with less precise timing */
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#endif
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/**
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* @brief FMC SDRAM Mode definition register defines
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*/
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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@ -88,6 +47,9 @@
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#define BUFFER_SIZE ((uint32_t)0x0100)
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#define WRITE_READ_ADDR ((uint32_t)0x0800)
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#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90MHz SD clock) */
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/**
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* @}
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*/
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@ -41,9 +41,9 @@ if PLATFORM == 'gcc':
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OBJCPY = PREFIX + 'objcopy'
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DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
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CFLAGS = DEVICE + ' -g -Wall -DSTM32F429ZI -DSTM32F429_439xx -DUSE_STDPERIPH_DRIVER -D__ASSEMBLY__'
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CFLAGS = DEVICE + ' -g -Wall -DSTM32F429ZI -DSTM32F429_439xx -D__ASSEMBLY__'
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AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
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LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
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||||
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
|
@ -65,7 +65,7 @@ elif PLATFORM == 'armcc':
|
|||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu=cortex-m4.fp'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork -DUSE_STDPERIPH_DRIVER -DSTM32F429_439xx'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork -DSTM32F429_439xx'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct'
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue