From 433e5f81473f71e36fbfb2a4ca5fcbb6b28f57b2 Mon Sep 17 00:00:00 2001 From: jiladahe1997 <972931182@qq.com> Date: Thu, 9 Dec 2021 11:22:46 +0800 Subject: [PATCH] =?UTF-8?q?[bugfix]=20libcpu/arm/cortex-m/context=5Fgcc:?= =?UTF-8?q?=20=E4=BF=AE=E5=A4=8Dthumb=E6=8C=87=E4=BB=A4=E9=9B=86=E6=B1=87?= =?UTF-8?q?=E7=BC=96=E8=AF=AD=E6=B3=95=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 当使用thumb指令集时，要求汇编语法中的“条件执行”要跟在IT指令后面，否则会编译不通过。 报错如下：Error: thumb conditional instruction should be in IT block -- `moveq r4,#0x01' 虽然可以通过指定"-Wa,-mimplicit-it=thumb"选项来告诉编译器识别隐式的IT指令，但是能在代码里面直接加上IT指令的话更好。 thumb指令集“条件执行”arm官网文档： https://developer.arm.com/documentation/dui0473/m/condition-codes/conditional-execution-in-thumb-state 参考论坛帖子： https://club.rt-thread.org/ask/question/433887.html https://club.rt-thread.org/ask/question/4188.html Signed-off-by: Mingrui Ren --- libcpu/arm/cortex-m33/context_gcc.S | 2 ++ libcpu/arm/cortex-m4/context_gcc.S | 4 ++++ libcpu/arm/cortex-m7/context_gcc.S | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S index 27596bf787..3c4ac8a236 100644 --- a/libcpu/arm/cortex-m33/context_gcc.S +++ b/libcpu/arm/cortex-m33/context_gcc.S @@ -143,6 +143,7 @@ contex_ns_store: #if defined (__VFP_FP__) && !defined(__SOFTFP__) TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ #endif @@ -187,6 +188,7 @@ contex_ns_load: #if defined (__VFP_FP__) && !defined(__SOFTFP__) TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ VLDMIAEQ r1!, {d8 - d15} /* pop FPU register s16~s31 */ #endif diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S index f569a35863..0c69b4d4dd 100644 --- a/libcpu/arm/cortex-m4/context_gcc.S +++ b/libcpu/arm/cortex-m4/context_gcc.S @@ -107,6 +107,7 @@ PendSV_Handler: #if defined (__VFP_FP__) && !defined(__SOFTFP__) TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ #endif @@ -116,6 +117,7 @@ PendSV_Handler: MOV r4, #0x00 /* flag = 0 */ TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ MOVEQ r4, #0x01 /* flag = 1 */ STMFD r1!, {r4} /* push flag */ @@ -137,6 +139,7 @@ switch_to_thread: #if defined (__VFP_FP__) && !defined(__SOFTFP__) CMP r3, #0 /* if(flag_r3 != 0) */ + IT NE VLDMIANE r1!, {d8 - d15} /* pop FPU register s16~s31 */ #endif @@ -145,6 +148,7 @@ switch_to_thread: #if defined (__VFP_FP__) && !defined(__SOFTFP__) ORR lr, lr, #0x10 /* lr |= (1 << 4), clean FPCA. */ CMP r3, #0 /* if(flag_r3 != 0) */ + IT NE BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */ #endif diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S index f569a35863..0c69b4d4dd 100644 --- a/libcpu/arm/cortex-m7/context_gcc.S +++ b/libcpu/arm/cortex-m7/context_gcc.S @@ -107,6 +107,7 @@ PendSV_Handler: #if defined (__VFP_FP__) && !defined(__SOFTFP__) TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ #endif @@ -116,6 +117,7 @@ PendSV_Handler: MOV r4, #0x00 /* flag = 0 */ TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ MOVEQ r4, #0x01 /* flag = 1 */ STMFD r1!, {r4} /* push flag */ @@ -137,6 +139,7 @@ switch_to_thread: #if defined (__VFP_FP__) && !defined(__SOFTFP__) CMP r3, #0 /* if(flag_r3 != 0) */ + IT NE VLDMIANE r1!, {d8 - d15} /* pop FPU register s16~s31 */ #endif @@ -145,6 +148,7 @@ switch_to_thread: #if defined (__VFP_FP__) && !defined(__SOFTFP__) ORR lr, lr, #0x10 /* lr |= (1 << 4), clean FPCA. */ CMP r3, #0 /* if(flag_r3 != 0) */ + IT NE BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */ #endif