libs/rt-thread
libs/rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

- fix indentations.

Browse Source
This commit is contained in:
0xcccccccccccc 2020-12-07 20:40:43 +08:00
parent 0fc2b13b45
commit 5d32b5d2d2
13 changed files with 1107 additions and 1050 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
bsp/ls2kdev/drivers/clk.c
View File

@ -14,7 +14,8 @@
#include <rtthread.h>
#include "ls2k1000.h"
struct loongson_pll {
struct loongson_pll
{
rt_uint64_t PLL_SYS_0;
rt_uint64_t PLL_SYS_1;
rt_uint64_t PLL_DDR_0;

9
bsp/ls2kdev/drivers/drv_gpio.c
View File

@ -25,7 +25,8 @@ static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t
gpio = (void *)device->user_data;
m = (rt_uint64_t)1 << pin;
switch (mode) {
switch (mode)
{
case PIN_MODE_OUTPUT:
gpio->GPIO0_OEN &= ~m;
break;
@ -52,7 +53,8 @@ static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_base_
struct loongson_gpio *gpio;
rt_uint64_t m;
if (pin < 0 || pin >= 60) {
if (pin < 0 || pin >= 60)
{
rt_kprintf("error\n");
return;
}
@ -212,7 +214,8 @@ static void gpio_irq_handler(int irq, void *param)
}
}
static struct rt_pin_ops loongson_pin_ops = {
static struct rt_pin_ops loongson_pin_ops =
{
.pin_mode = loongson_pin_mode,
.pin_write = loongson_pin_write,
.pin_read = loongson_pin_read,

15
bsp/ls2kdev/drivers/drv_pwm.c
View File

@ -28,7 +28,8 @@
#define CTRL_INVERT (1UL<<9)
#define CTRL_DZONE (1UL<<10)
struct loongson_pwm {
struct loongson_pwm
{
rt_uint32_t __PAD0;
rt_uint32_t low_buffer;
rt_uint32_t full_buffer;
@ -91,7 +92,8 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
cfg = (void *)arg;
switch (cmd) {
switch (cmd)
{
case PWM_CMD_ENABLE:
rc = loongson_pwm_enable(device, cfg->channel);
break;
@ -111,18 +113,21 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
return rc;
}
struct rt_pwm_ops loongson_pwm_ops = {
struct rt_pwm_ops loongson_pwm_ops =
{
.control = loongson_pwm_ioctl,
};
struct rt_device_pwm loongson_pwm = {
struct rt_device_pwm loongson_pwm =
{
.ops = &loongson_pwm_ops,
};
int loongson_pwm_init(void)
{
int rc = RT_EOK;
static rt_uint32_t *priv[] = {
static rt_uint32_t *priv[] =
{
(void *)PWM0_BASE,
(void *)PWM1_BASE,
(void *)PWM2_BASE,

12
bsp/ls2kdev/drivers/drv_rtc.c
View File

@ -19,7 +19,8 @@
#ifdef RT_USING_RTC
struct loongson_rtc {
struct loongson_rtc
{
rt_uint32_t sys_toytrim;
rt_uint32_t sys_toywrite0;
rt_uint32_t sys_toywrite1;
@ -45,7 +46,8 @@ struct loongson_rtc {
#define __BF(number, n, m) __RBF((number>>m), (n-m+1))
#define BF(number, n, m) (m<n ? __BF(number, n, m) : __BF(number, m, n))
struct rtctime {
struct rtctime
{
rt_uint32_t sys_toyread0;
rt_uint32_t sys_toyread1;
rt_uint32_t sys_rtcread0;
@ -133,7 +135,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
rtctm.sys_rtcread0 = hw_rtc->sys_rtcread0;
tmptime = *localrtctime(&rtctm);
switch (cmd) {
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*t = mktime(&tmptime);
break;
@ -164,7 +167,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
int rt_hw_rtc_init(void)
{
static struct rt_device rtc = {
static struct rt_device rtc =
{
.type = RT_Device_Class_RTC,
.init = RT_NULL,
.open = rt_rtc_open,

9
bsp/ls2kdev/drivers/drv_spi.c
View File

@ -36,7 +36,8 @@ static void spi_set_csn(uint8_t val) //old method
static void spi_set_cs(unsigned char cs, int new_status)
{
if(cs<4){
if (cs < 4)
{
unsigned char val = 0;
val = GET_SPI(SOFTCS);
@ -54,7 +55,8 @@ static void spi_set_cs(unsigned char cs, int new_status)
return ;
}
#ifdef RT_USING_SPI_GPIOCS
else{
else
{
//rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n ");
//rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status);
rt_pin_mode(cs, PIN_MODE_OUTPUT);
@ -182,7 +184,8 @@ static rt_err_t configure(struct rt_spi_device *device,
uint64_t div = (uint64_t)(spi_max_speed / (float)configuration->max_hz);
//rt_kprintf("require speed: %ld\n",configuration->max_hz);
int ctr = 0;
while(div!=1 && ctr<12){
while (div != 1 && ctr < 12)
{
ctr++;
div = div >> 1;
}

3
bsp/ls2kdev/drivers/drv_uart.c
View File

@ -22,7 +22,8 @@
#define TRUE 1
#define FALSE 0
const struct serial_configure config_uart0 = {
const struct serial_configure config_uart0 =
{
BAUD_RATE_115200, /* 921600 bits/s */
DATA_BITS_8, /* 8 databits */
STOP_BITS_1, /* 1 stopbit */

20
bsp/ls2kdev/drivers/net/mii.c
View File

@ -32,7 +32,8 @@ static int mii_check_gmii_support(struct mii_if_info *mii)
int reg;
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (reg & BMSR_ESTATEN) {
if (reg & BMSR_ESTATEN)
{
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS);
if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF))
return 1;
@ -84,11 +85,13 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
if (mii->supports_gmii) {
if (mii->supports_gmii)
{
bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
}
if (bmcr & BMCR_ANENABLE) {
if (bmcr & BMCR_ANENABLE)
{
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->autoneg = AUTONEG_ENABLE;
@ -101,14 +104,19 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
else
ecmd->speed = SPEED_10;
if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
nego == LPA_10FULL) {
nego == LPA_10FULL)
{
ecmd->duplex = DUPLEX_FULL;
mii->full_duplex = 1;
} else {
}
else
{
ecmd->duplex = DUPLEX_HALF;
mii->full_duplex = 0;
}
} else {
}
else
{
ecmd->autoneg = AUTONEG_DISABLE;
ecmd->speed = ((bmcr & BMCR_SPEED1000 &&

87
bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
View File

@ -1136,7 +1136,8 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev)
if (gmacdev -> Speed == SPEED1000)
synopGMAC_select_gmii(gmacdev);
else{
else
{
synopGMAC_select_mii(gmacdev);
if (gmacdev -> Speed == SPEED100)
@ -1870,11 +1871,13 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txover + 1;
if(synopGMAC_is_tx_desc_chained(txdesc)){
if (synopGMAC_is_tx_desc_chained(txdesc))
{
gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
synopGMAC_tx_desc_init_chain(txdesc);
}
else{
else
{
gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1);
synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev, txdesc));
}
@ -2105,7 +2108,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
if (!synopGMAC_is_desc_empty(rxdesc))
return -1;
if(synopGMAC_is_rx_desc_chained(rxdesc)){
if (synopGMAC_is_rx_desc_chained(rxdesc))
{
rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask);
rxdesc->buffer1 = Buffer1;
@ -2124,7 +2128,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
}
else{
else
{
rxdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
rxdesc->buffer1 = Buffer1;
@ -2177,7 +2182,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
if (!synopGMAC_is_desc_empty(rxdesc))
return -1;
if(synopGMAC_is_rx_desc_chained(rxdesc)){
if (synopGMAC_is_rx_desc_chained(rxdesc))
{
rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask);
rxdesc->buffer1 = Buffer1;
@ -2191,7 +2197,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
}
else{
else
{
rxdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
rxdesc->buffer1 = Buffer1;
@ -2229,7 +2236,8 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt
if (!synopGMAC_is_desc_empty(rxdesc))
return -1;
if(synopGMAC_is_rx_desc_chained(rxdesc)){
if (synopGMAC_is_rx_desc_chained(rxdesc))
{
rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask);
rxdesc->buffer1 = Buffer1;
@ -2244,7 +2252,8 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt
gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
}
else{
else
{
rxdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
rxdesc->buffer1 = Buffer1;
@ -2323,12 +2332,14 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
if(synopGMAC_is_rx_desc_chained(rxdesc)){
if (synopGMAC_is_rx_desc_chained(rxdesc))
{
gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2;
synopGMAC_rx_desc_init_chain(rxdesc);
//synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0);
}
else{
else
{
gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev, rxdesc));
}
@ -2392,11 +2403,13 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
len = synopGMAC_get_rx_desc_frame_length(*Status);
DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n", len);
gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
if(synopGMAC_is_rx_desc_chained(rxdesc)){
if (synopGMAC_is_rx_desc_chained(rxdesc))
{
gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2;
synopGMAC_rx_desc_init_chain(rxdesc);
}
else{
else
{
gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
//sw: raw data
#if SYNOP_RX_DEBUG
@ -2578,7 +2591,8 @@ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev)
*/
void synopGMAC_take_desc_ownership(DmaDesc *desc)
{
if(desc){
if (desc)
{
desc->status &= ~DescOwnByDma; //Clear the DMA own bit
// desc->status |= DescError; // Set the error to indicate this descriptor is bad
}
@ -2598,13 +2612,16 @@ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev)
s32 i;
DmaDesc *desc;
desc = gmacdev->RxDesc;
for(i = 0; i < gmacdev->RxDescCount; i++){
if(synopGMAC_is_rx_desc_chained(desc)){ //This descriptor is in chain mode
for (i = 0; i < gmacdev->RxDescCount; i++)
{
if (synopGMAC_is_rx_desc_chained(desc)) //This descriptor is in chain mode
{
synopGMAC_take_desc_ownership(desc);
desc = (DmaDesc *)desc->data2;
}
else{
else
{
synopGMAC_take_desc_ownership(desc + i);
}
}
@ -2624,12 +2641,15 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
s32 i;
DmaDesc *desc;
desc = gmacdev->TxDesc;
for(i = 0; i < gmacdev->TxDescCount; i++){
if(synopGMAC_is_tx_desc_chained(desc)){ //This descriptor is in chain mode
for (i = 0; i < gmacdev->TxDescCount; i++)
{
if (synopGMAC_is_tx_desc_chained(desc)) //This descriptor is in chain mode
{
synopGMAC_take_desc_ownership(desc);
desc = (DmaDesc *)desc->data2;
}
else{
else
{
synopGMAC_take_desc_ownership(desc + i);
}
}
@ -3544,15 +3564,18 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
{
u32 loop_variable;
synopGMACWriteReg(gmacdev->MacBase, GmacTSAddend, addend_value); // Load the addend_value in to Addend register
for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break
for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time
{
if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSADDREG)) // if it is cleared then break
{
break;
}
plat_delay(DEFAULT_DELAY_VARIABLE);
}
if (loop_variable < DEFAULT_LOOP_VARIABLE)
synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSADDREG);
else{
else
{
TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
return -ESYNOPGMACPHYERR;
}
@ -3572,15 +3595,18 @@ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32
u32 loop_variable;
synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register
synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register
for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break
for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time
{
if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSUPDT)) // if it is cleared then break
{
break;
}
plat_delay(DEFAULT_DELAY_VARIABLE);
}
if (loop_variable < DEFAULT_LOOP_VARIABLE)
synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSUPDT);
else{
else
{
TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
return -ESYNOPGMACPHYERR;
}
@ -3601,15 +3627,18 @@ s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 lo
u32 loop_variable;
synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register
synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register
for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break
for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time
{
if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSINT)) // if it is cleared then break
{
break;
}
plat_delay(DEFAULT_DELAY_VARIABLE);
}
if (loop_variable < DEFAULT_LOOP_VARIABLE)
synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSINT);
else{
else
{
TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
return -ESYNOPGMACPHYERR;
}

9
bsp/ls2kdev/drivers/net/synopGMAC_plat.c
View File

@ -69,13 +69,16 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3
// rt_kprintf("size = %d\n", size);
// rt_kprintf("bufaddr = %p\n", buf);
// rt_kprintf("i%%16 == %d\n", i%16);
if(i % 16 == 8){
if (i % 16 == 8)
{
i += 8;
}
else if(i % 16 == 4){
else if (i % 16 == 4)
{
i += 12;
}
else if(i % 16 == 12){
else if (i % 16 == 12)
{
i += 4;
}