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optimize code to improve network throughput performance (#6157)

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sheltonyu 2022-07-12 08:40:58 +08:00 committed by GitHub
parent 1fec9dc550
commit 5c6e7d815b
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 37 additions and 40 deletions
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77
bsp/at32/libraries/rt_drivers/drv_emac.c
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@ -6,6 +6,8 @@
* Change Logs:
* Date Author Notes
* 2022-05-16 shelton first version
* 2022-07-11 shelton optimize code to improve network throughput
* performance
*/
#include "drv_emac.h"
@ -22,8 +24,8 @@
#define CRYSTAL_ON_PHY 0
/* emac memory buffer configuration */
#define EMAC_NUM_RX_BUF 4 /* 0x1800 for rx (4 * 1536 = 6k) */
#define EMAC_NUM_TX_BUF 2 /* 0x0600 for tx (2 * 1536 = 3k) */
#define EMAC_NUM_RX_BUF 5 /* rx (5 * 1500) */
#define EMAC_NUM_TX_BUF 5 /* tx (5 * 1500) */
#define MAX_ADDR_LEN 6
@ -49,8 +51,6 @@ extern emac_dma_desc_type *dma_rx_desc_to_get, *dma_tx_desc_to_set;
static rt_uint8_t *rx_buff, *tx_buff;
static struct rt_at32_emac at32_emac_device;
static uint8_t phy_addr = 0xFF;
static struct rt_semaphore tx_wait;
static rt_bool_t tx_is_waiting = RT_FALSE;
#if defined(EMAC_RX_DUMP) || defined(EMAC_TX_DUMP)
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
@ -123,7 +123,6 @@ static void phy_reset(void)
rt_thread_mdelay(2000);
}
/**
* @brief phy clock config
*/
@ -143,7 +142,6 @@ static void phy_clock_config(void)
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
/* 9162 clkout output 25 mhz */
/* 83848 clkout output 50 mhz */
#if defined (SOC_SERIES_AT32F407)
@ -444,22 +442,15 @@ static rt_err_t rt_at32_emac_control(rt_device_t dev, int cmd, void *args)
*/
rt_err_t rt_at32_emac_tx(rt_device_t dev, struct pbuf *p)
{
rt_err_t ret = RT_ERROR;
struct pbuf *q;
rt_uint32_t offset;
while ((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != RESET)
if ((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != RESET)
{
rt_err_t result;
rt_uint32_t level;
level = rt_hw_interrupt_disable();
tx_is_waiting = RT_TRUE;
rt_hw_interrupt_enable(level);
/* it's own bit set, wait it */
result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER);
if (result == RT_EOK) break;
if (result == -RT_ERROR) return -RT_ERROR;
LOG_D("buffer not valid");
ret = ERR_USE;
goto __error;
}
offset = 0;
@ -499,6 +490,18 @@ rt_err_t rt_at32_emac_tx(rt_device_t dev, struct pbuf *p)
dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr);
return ERR_OK;
__error:
if (emac_dma_flag_get(EMAC_DMA_UNF_FLAG) != (uint32_t)RESET)
{
/* clear underflow ethernet dma flag */
emac_dma_flag_clear(EMAC_DMA_UNF_FLAG);
/* resume dma transmission*/
EMAC_DMA->tpd = 0;
}
return ret;
}
/**
@ -581,24 +584,6 @@ void EMAC_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
/* clear received it */
if(emac_dma_flag_get(EMAC_DMA_NIS_FLAG) != RESET)
{
emac_dma_flag_clear(EMAC_DMA_NIS_FLAG);
}
if(emac_dma_flag_get(EMAC_DMA_AIS_FLAG) != RESET)
{
emac_dma_flag_clear(EMAC_DMA_AIS_FLAG);
}
if(emac_dma_flag_get(EMAC_DMA_OVF_FLAG) != RESET)
{
emac_dma_flag_clear(EMAC_DMA_OVF_FLAG);
}
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG) != RESET)
{
emac_dma_flag_clear(EMAC_DMA_RBU_FLAG);
}
/* packet receiption */
if (emac_dma_flag_get(EMAC_DMA_RI_FLAG) == SET)
{
@ -610,13 +595,25 @@ void EMAC_IRQHandler(void)
/* packet transmission */
if (emac_dma_flag_get(EMAC_DMA_TI_FLAG) == SET)
{
if (tx_is_waiting == RT_TRUE)
emac_dma_flag_clear(EMAC_DMA_TI_FLAG);
}
/* clear normal interrupt */
emac_dma_flag_clear(EMAC_DMA_NIS_FLAG);
/* clear dma error */
if(emac_dma_flag_get(EMAC_DMA_AIS_FLAG) != RESET)
{
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG) != RESET)
{
tx_is_waiting = RT_FALSE;
rt_sem_release(&tx_wait);
emac_dma_flag_clear(EMAC_DMA_RBU_FLAG);
}
if(emac_dma_flag_get(EMAC_DMA_OVF_FLAG) != RESET)
{
emac_dma_flag_clear(EMAC_DMA_OVF_FLAG);
}
emac_dma_flag_clear(EMAC_DMA_TI_FLAG);
emac_dma_flag_clear(EMAC_DMA_AIS_FLAG);
}
/* leave interrupt */