Merge pull request #3808 from BernardXiong/stm32f429-disco
[BSP][stm32f429-st-disco] Add SDRAM, LCD port files
This commit is contained in:
Bernard Xiong
GitHub
commit
5a6a7e391e
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@ -42,7 +42,7 @@ CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_SIGNALS is not set
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CONFIG_RT_USING_SIGNALS=y
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#
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# Memory Management
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@ -50,10 +50,9 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
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CONFIG_RT_USING_MEMPOOL=y
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CONFIG_RT_USING_MEMHEAP=y
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SMALL_MEM is not set
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
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CONFIG_RT_USING_HEAP=y
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#
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@ -65,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x40002
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CONFIG_RT_VER_NUM=0x40003
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CONFIG_ARCH_ARM=y
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CONFIG_RT_USING_CPU_FFS=y
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CONFIG_ARCH_ARM_CORTEX_M=y
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@ -101,7 +100,7 @@ CONFIG_FINSH_CMD_SIZE=80
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_USING_MSH_DEFAULT=y
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# CONFIG_FINSH_USING_MSH_ONLY is not set
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CONFIG_FINSH_USING_MSH_ONLY=y
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CONFIG_FINSH_ARG_MAX=10
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#
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@ -133,16 +132,19 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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CONFIG_RT_USING_I2C=y
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# CONFIG_RT_I2C_DEBUG is not set
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CONFIG_RT_USING_I2C_BITOPS=y
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# CONFIG_RT_I2C_BITOPS_DEBUG is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_DAC is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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# CONFIG_RT_USING_PM is not set
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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CONFIG_RT_USING_SPI=y
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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@ -162,7 +164,8 @@ CONFIG_RT_USING_PIN=y
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# POSIX layer and C standard library
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#
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CONFIG_RT_USING_LIBC=y
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# CONFIG_RT_USING_PTHREADS is not set
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CONFIG_RT_USING_PTHREADS=y
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CONFIG_PTHREAD_NUM_MAX=8
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CONFIG_RT_USING_POSIX=y
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# CONFIG_RT_USING_POSIX_MMAP is not set
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# CONFIG_RT_USING_POSIX_TERMIOS is not set
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@ -213,10 +216,15 @@ CONFIG_RT_USING_POSIX=y
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#
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# IoT - internet of things
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#
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# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
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# CONFIG_PKG_USING_PAHOMQTT is not set
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# CONFIG_PKG_USING_UMQTT is not set
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# CONFIG_PKG_USING_WEBCLIENT is not set
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# CONFIG_PKG_USING_WEBNET is not set
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# CONFIG_PKG_USING_MONGOOSE is not set
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# CONFIG_PKG_USING_MYMQTT is not set
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# CONFIG_PKG_USING_KAWAII_MQTT is not set
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# CONFIG_PKG_USING_BC28_MQTT is not set
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# CONFIG_PKG_USING_WEBTERMINAL is not set
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# CONFIG_PKG_USING_CJSON is not set
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# CONFIG_PKG_USING_JSMN is not set
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@ -243,6 +251,7 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_COAP is not set
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# CONFIG_PKG_USING_NOPOLL is not set
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# CONFIG_PKG_USING_NETUTILS is not set
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# CONFIG_PKG_USING_CMUX is not set
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# CONFIG_PKG_USING_PPP_DEVICE is not set
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# CONFIG_PKG_USING_AT_DEVICE is not set
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# CONFIG_PKG_USING_ATSRV_SOCKET is not set
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@ -255,8 +264,10 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_GAGENT_CLOUD is not set
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# CONFIG_PKG_USING_ALI_IOTKIT is not set
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# CONFIG_PKG_USING_AZURE is not set
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# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
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# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
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# CONFIG_PKG_USING_JIOT-C-SDK is not set
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# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
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# CONFIG_PKG_USING_JOYLINK is not set
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# CONFIG_PKG_USING_NIMBLE is not set
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# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
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# CONFIG_PKG_USING_IPMSG is not set
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@ -268,6 +279,14 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_ONNX_PARSER is not set
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# CONFIG_PKG_USING_ONNX_BACKEND is not set
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# CONFIG_PKG_USING_DLT645 is not set
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# CONFIG_PKG_USING_QXWZ is not set
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# CONFIG_PKG_USING_SMTP_CLIENT is not set
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# CONFIG_PKG_USING_ABUP_FOTA is not set
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# CONFIG_PKG_USING_LIBCURL2RTT is not set
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# CONFIG_PKG_USING_CAPNP is not set
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# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
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# CONFIG_PKG_USING_AGILE_TELNET is not set
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# CONFIG_PKG_USING_NMEALIB is not set
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#
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# security packages
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@ -275,6 +294,8 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_MBEDTLS is not set
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# CONFIG_PKG_USING_libsodium is not set
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# CONFIG_PKG_USING_TINYCRYPT is not set
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# CONFIG_PKG_USING_TFM is not set
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# CONFIG_PKG_USING_YD_CRYPTO is not set
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#
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# language packages
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@ -303,6 +324,14 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_QRCODE is not set
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# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
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# CONFIG_PKG_USING_ADBD is not set
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# CONFIG_PKG_USING_COREMARK is not set
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# CONFIG_PKG_USING_DHRYSTONE is not set
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# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
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# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
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# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
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# CONFIG_PKG_USING_BS8116A is not set
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# CONFIG_PKG_USING_GPS_RMC is not set
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# CONFIG_PKG_USING_URLENCODE is not set
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#
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# system packages
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@ -314,6 +343,7 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_LWEXT4 is not set
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# CONFIG_PKG_USING_PARTITION is not set
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# CONFIG_PKG_USING_FAL is not set
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# CONFIG_PKG_USING_FLASHDB is not set
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# CONFIG_PKG_USING_SQLITE is not set
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# CONFIG_PKG_USING_RTI is not set
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# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
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@ -322,6 +352,13 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_LITTLEFS is not set
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# CONFIG_PKG_USING_THREAD_POOL is not set
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# CONFIG_PKG_USING_ROBOTS is not set
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# CONFIG_PKG_USING_EV is not set
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# CONFIG_PKG_USING_SYSWATCH is not set
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# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
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# CONFIG_PKG_USING_PLCCORE is not set
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# CONFIG_PKG_USING_RAMDISK is not set
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# CONFIG_PKG_USING_MININI is not set
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# CONFIG_PKG_USING_QBOOT is not set
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#
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# peripheral libraries and drivers
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@ -329,6 +366,7 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
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# CONFIG_PKG_USING_REALTEK_AMEBA is not set
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# CONFIG_PKG_USING_SHT2X is not set
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# CONFIG_PKG_USING_SHT3X is not set
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# CONFIG_PKG_USING_STM32_SDIO is not set
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# CONFIG_PKG_USING_ICM20608 is not set
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# CONFIG_PKG_USING_U8G2 is not set
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@ -337,10 +375,16 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_SX12XX is not set
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# CONFIG_PKG_USING_SIGNAL_LED is not set
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# CONFIG_PKG_USING_LEDBLINK is not set
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# CONFIG_PKG_USING_LITTLED is not set
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# CONFIG_PKG_USING_LKDGUI is not set
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# CONFIG_PKG_USING_NRF5X_SDK is not set
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# CONFIG_PKG_USING_NRFX is not set
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# CONFIG_PKG_USING_WM_LIBRARIES is not set
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# CONFIG_PKG_USING_KENDRYTE_SDK is not set
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# CONFIG_PKG_USING_INFRARED is not set
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# CONFIG_PKG_USING_ROSSERIAL is not set
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# CONFIG_PKG_USING_AGILE_BUTTON is not set
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# CONFIG_PKG_USING_AGILE_LED is not set
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# CONFIG_PKG_USING_AT24CXX is not set
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# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
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# CONFIG_PKG_USING_AD7746 is not set
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@ -348,9 +392,23 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_I2C_TOOLS is not set
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# CONFIG_PKG_USING_NRF24L01 is not set
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# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
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# CONFIG_PKG_USING_LCD_DRIVERS is not set
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# CONFIG_PKG_USING_MAX17048 is not set
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# CONFIG_PKG_USING_RPLIDAR is not set
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# CONFIG_PKG_USING_AS608 is not set
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# CONFIG_PKG_USING_RC522 is not set
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# CONFIG_PKG_USING_WS2812B is not set
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# CONFIG_PKG_USING_EMBARC_BSP is not set
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# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
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# CONFIG_PKG_USING_MULTI_RTIMER is not set
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# CONFIG_PKG_USING_MAX7219 is not set
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# CONFIG_PKG_USING_BEEP is not set
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# CONFIG_PKG_USING_EASYBLINK is not set
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# CONFIG_PKG_USING_PMS_SERIES is not set
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# CONFIG_PKG_USING_CAN_YMODEM is not set
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# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
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# CONFIG_PKG_USING_QLED is not set
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# CONFIG_PKG_USING_PAJ7620 is not set
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# CONFIG_PKG_USING_AGILE_CONSOLE is not set
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#
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# miscellaneous packages
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@ -385,6 +443,42 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_ELAPACK is not set
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# CONFIG_PKG_USING_ARMv7M_DWT is not set
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# CONFIG_PKG_USING_VT100 is not set
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# CONFIG_PKG_USING_ULAPACK is not set
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# CONFIG_PKG_USING_UKAL is not set
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# CONFIG_PKG_USING_CRCLIB is not set
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#
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# Privated Packages of RealThread
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#
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# CONFIG_PKG_USING_CODEC is not set
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# CONFIG_PKG_USING_PLAYER is not set
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# CONFIG_PKG_USING_MPLAYER is not set
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# CONFIG_PKG_USING_PERSIMMON_SRC is not set
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# CONFIG_PKG_USING_JS_PERSIMMON is not set
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# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
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#
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# Network Utilities
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#
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# CONFIG_PKG_USING_WICED is not set
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# CONFIG_PKG_USING_CLOUDSDK is not set
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# CONFIG_PKG_USING_POWER_MANAGER is not set
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# CONFIG_PKG_USING_RT_OTA is not set
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# CONFIG_PKG_USING_RDBD_SRC is not set
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# CONFIG_PKG_USING_RTINSIGHT is not set
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# CONFIG_PKG_USING_SMARTCONFIG is not set
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# CONFIG_PKG_USING_RTX is not set
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# CONFIG_RT_USING_TESTCASE is not set
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# CONFIG_PKG_USING_NGHTTP2 is not set
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# CONFIG_PKG_USING_AVS is not set
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# CONFIG_PKG_USING_ALI_LINKKIT is not set
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# CONFIG_PKG_USING_STS is not set
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# CONFIG_PKG_USING_DLMS is not set
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# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
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# CONFIG_PKG_USING_ZBAR is not set
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# CONFIG_PKG_USING_MCF is not set
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# CONFIG_PKG_USING_URPC is not set
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# CONFIG_PKG_USING_BSAL is not set
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CONFIG_SOC_FAMILY_STM32=y
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CONFIG_SOC_SERIES_STM32F4=y
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@ -393,6 +487,11 @@ CONFIG_SOC_SERIES_STM32F4=y
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#
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CONFIG_SOC_STM32F429ZI=y
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#
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# Onboard Peripheral Drivers
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#
|
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CONFIG_BSP_USING_SDRAM=y
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#
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# On-chip Peripheral Drivers
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#
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@ -400,12 +499,14 @@ CONFIG_BSP_USING_GPIO=y
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CONFIG_BSP_USING_UART=y
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CONFIG_BSP_USING_UART1=y
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# CONFIG_BSP_UART1_RX_USING_DMA is not set
|
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# CONFIG_BSP_USING_UART2 is not set
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# CONFIG_BSP_USING_I2C1 is not set
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# CONFIG_BSP_USING_SPI is not set
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# CONFIG_BSP_USING_QSPI is not set
|
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# CONFIG_BSP_USING_FMC is not set
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# CONFIG_BSP_USING_USBD_FS is not set
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# CONFIG_BSP_USING_LTDC is not set
|
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CONFIG_BSP_USING_FMC=y
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# CONFIG_BSP_USING_USBD is not set
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CONFIG_BSP_USING_LCD=y
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CONFIG_BSP_USING_LTDC=y
|
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# CONFIG_BSP_USING_RNG is not set
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# CONFIG_BSP_USING_UDID is not set
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File diff suppressed because one or more lines are too long
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@ -0,0 +1,30 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
|
||||
<name>stm32f429</name>
|
||||
<comment />
|
||||
<projects>
|
||||
</projects>
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||||
<buildSpec>
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||||
<buildCommand>
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||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
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||||
<arguments>
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||||
</arguments>
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||||
</buildCommand>
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||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.rt-thread.studio.rttnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
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||||
</natures>
|
||||
<linkedResources>
|
||||
</linkedResources>
|
||||
</projectDescription>
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Binary file not shown.
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@ -0,0 +1,14 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project>
|
||||
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1530062170212089103" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
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@ -0,0 +1,3 @@
|
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content-types/enabled=true
|
||||
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
|
||||
eclipse.preferences.version=1
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#RT-Thread Studio Project Configuration
|
||||
#Thu Aug 06 07:31:27 CST 2020
|
||||
qemu_supported_board=stm32f429-st-disco
|
||||
mcu_name=STM32F429ZI
|
||||
hardware_adapter=QEMU
|
||||
selected_rtt_version=latest
|
||||
mcu_base_nano_proj=true
|
||||
project_base_bsp=true
|
||||
cfg_version=v2.0
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.adapterName" value="DAP-LINK"/>
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|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.adapterName" value="ST-LINK"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${rtt_install_path}\repo\Extract\Chip_Support_Packages\RealThread\STM32F4\0.1.7\debug\svd\STM32F429x.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.connectMode" value="NORMAL"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.debugInterface" value="SWD"/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.flashVerify" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="org.eclipse.cdt.debug.gdbjtag.core.jtagdevice.genericDevice"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherDownloadOption" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherGdbserverOption" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61235"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetMode" value=" -hardRst"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetRun" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="stm32f429"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/stm32f429"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="true"/>
|
||||
</launchConfiguration>
|
||||
|
|
@ -7,7 +7,17 @@ config SOC_STM32F429ZI
|
|||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
select BSP_USING_FMC
|
||||
default n
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
|
|
@ -15,8 +25,8 @@ menu "On-chip Peripheral Drivers"
|
|||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
|
|
@ -26,14 +36,24 @@ menu "On-chip Peripheral Drivers"
|
|||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
default n
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
int "I2C1 scl pin number"
|
||||
|
|
@ -48,7 +68,7 @@ menu "On-chip Peripheral Drivers"
|
|||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI BUS"
|
||||
select RT_USING_SPI
|
||||
default n
|
||||
default y
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI3
|
||||
bool "Enable SPI3 BUS"
|
||||
|
|
@ -81,9 +101,16 @@ menu "On-chip Peripheral Drivers"
|
|||
select RT_USING_USB_DEVICE
|
||||
default n
|
||||
|
||||
config BSP_USING_LCD
|
||||
bool "Enable LCD"
|
||||
default n
|
||||
|
||||
config BSP_USING_LTDC
|
||||
bool "Enable LTDC"
|
||||
select BSP_USING_SDRAM
|
||||
select BSP_USING_LCD
|
||||
default n
|
||||
|
||||
source "../libraries/HAL_Drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -18,9 +18,6 @@ if GetDepend(['BSP_USING_QSPI_FLASH']):
|
|||
if GetDepend(['PKG_USING_FAL']):
|
||||
src += ['ports/qspi_mnt.c']
|
||||
|
||||
if GetDepend(['BSP_USING_LCD_OTM8009A']):
|
||||
src += ['ports/drv_otm8009a.c']
|
||||
|
||||
if GetDepend(['BSP_USING_TOUCH']):
|
||||
src += Glob('ports/touch/*.c')
|
||||
|
||||
|
|
@ -30,6 +27,9 @@ if GetDepend(['BSP_USING_SDCARD']):
|
|||
if GetDepend(['BSP_USING_QSPI']):
|
||||
src += ['ports/drv_qspi_flash.c']
|
||||
|
||||
if GetDepend(['BSP_USING_LCD']):
|
||||
src += ['ports/ili9341.c']
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/CubeMX_Config/Inc']
|
||||
path += [cwd + '/ports']
|
||||
|
|
|
|||
|
|
@ -48,12 +48,15 @@ void SystemClock_Config(void)
|
|||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/*##-2- LTDC Clock Configuration ###########################################*/
|
||||
/* LCD clock configuration */
|
||||
/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */
|
||||
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 MHz */
|
||||
/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/4 = 48 MHz */
|
||||
/* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDIVR_8 = 48/8 = 6 MHz */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
|
||||
PeriphClkInitStruct.PLLSAI.PLLSAIN = 50;
|
||||
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
|
||||
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
|
||||
PeriphClkInitStruct.PLLSAI.PLLSAIR = 4;
|
||||
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,313 @@
|
|||
/*
|
||||
* File : ili9341.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2020, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-11 RT-Thread the first version
|
||||
*/
|
||||
#include "rtthread.h"
|
||||
#include "stm32f4xx_hal.h"
|
||||
#include "ili9341.h"
|
||||
|
||||
/**
|
||||
* @brief LCD Control pin
|
||||
*/
|
||||
#define LCD_NCS_PIN GPIO_PIN_2
|
||||
#define LCD_NCS_GPIO_PORT GPIOC
|
||||
#define LCD_NCS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||
#define LCD_NCS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
|
||||
|
||||
/**
|
||||
* @brief LCD Command/data pin
|
||||
*/
|
||||
#define LCD_WRX_PIN GPIO_PIN_13
|
||||
#define LCD_WRX_GPIO_PORT GPIOD
|
||||
#define LCD_WRX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define LCD_WRX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
|
||||
|
||||
#define LCD_RDX_PIN GPIO_PIN_12
|
||||
#define LCD_RDX_GPIO_PORT GPIOD
|
||||
#define LCD_RDX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define LCD_RDX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
|
||||
|
||||
/* Maximum Timeout values for flags waiting loops */
|
||||
#define SPIx_TIMEOUT_MAX ((uint32_t)0x1000)
|
||||
|
||||
/* Chip Select macro definition */
|
||||
#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_SET)
|
||||
|
||||
/* Set WRX High to send data */
|
||||
#define LCD_WRX_LOW() HAL_GPIO_WritePin(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_WRX_HIGH() HAL_GPIO_WritePin(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PIN_SET)
|
||||
|
||||
/* Set WRX High to send data */
|
||||
#define LCD_RDX_LOW() HAL_GPIO_WritePin(LCD_RDX_GPIO_PORT, LCD_RDX_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_RDX_HIGH() HAL_GPIO_WritePin(LCD_RDX_GPIO_PORT, LCD_RDX_PIN, GPIO_PIN_SET)
|
||||
|
||||
static uint8_t Is_LCD_IO_Initialized = 0;
|
||||
static SPI_HandleTypeDef SpiHandle;
|
||||
|
||||
/**
|
||||
* @brief SPIx Bus initialization
|
||||
*/
|
||||
static void SPIx_Init(void)
|
||||
{
|
||||
if(HAL_SPI_GetState(&SpiHandle) == HAL_SPI_STATE_RESET)
|
||||
{
|
||||
/* SPI configuration -----------------------------------------------------*/
|
||||
SpiHandle.Instance = SPI5;
|
||||
/* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz)
|
||||
*/
|
||||
SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
||||
|
||||
/* On STM32F429I-Discovery, LCD ID cannot be read then keep a common configuration */
|
||||
/* for LCD and GYRO (SPI_DIRECTION_2LINES) */
|
||||
/* Note: To read a register a LCD, SPI_DIRECTION_1LINE should be set */
|
||||
SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
|
||||
SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||
SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
|
||||
SpiHandle.Init.CRCPolynomial = 7;
|
||||
SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||
SpiHandle.Init.NSS = SPI_NSS_SOFT;
|
||||
SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
|
||||
SpiHandle.Init.Mode = SPI_MODE_MASTER;
|
||||
|
||||
HAL_SPI_Init(&SpiHandle);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD_SPI interface.
|
||||
*/
|
||||
static void LCD_GPIO_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
if(Is_LCD_IO_Initialized == 0)
|
||||
{
|
||||
Is_LCD_IO_Initialized = 1;
|
||||
|
||||
/* Configure NCS in Output Push-Pull mode */
|
||||
LCD_WRX_GPIO_CLK_ENABLE();
|
||||
GPIO_InitStructure.Pin = LCD_WRX_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(LCD_WRX_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
LCD_RDX_GPIO_CLK_ENABLE();
|
||||
GPIO_InitStructure.Pin = LCD_RDX_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(LCD_RDX_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
/* Configure the LCD Control pins ----------------------------------------*/
|
||||
LCD_NCS_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Configure NCS in Output Push-Pull mode */
|
||||
GPIO_InitStructure.Pin = LCD_NCS_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
/* Set or Reset the control line */
|
||||
LCD_CS_LOW();
|
||||
LCD_CS_HIGH();
|
||||
|
||||
SPIx_Init();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the selected LCD register.
|
||||
* @param data: data to lcd.
|
||||
* @retval None
|
||||
*/
|
||||
static void ili9341_write_data(uint16_t data)
|
||||
{
|
||||
/* Set WRX to send data */
|
||||
LCD_WRX_HIGH();
|
||||
|
||||
/* Reset LCD control line(/CS) and Send data */
|
||||
LCD_CS_LOW();
|
||||
|
||||
HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX);
|
||||
|
||||
/* Deselect: Chip Select high */
|
||||
LCD_CS_HIGH();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes to the selected LCD register.
|
||||
* @param reg: address of the selected register.
|
||||
* @retval None
|
||||
*/
|
||||
static void ili9341_write_register(uint8_t reg)
|
||||
{
|
||||
/* Reset WRX to send command */
|
||||
LCD_WRX_LOW();
|
||||
|
||||
/* Reset LCD control line(/CS) and Send command */
|
||||
LCD_CS_LOW();
|
||||
|
||||
HAL_SPI_Transmit(&SpiHandle, (uint8_t*) ®, 1, SPIx_TIMEOUT_MAX);
|
||||
|
||||
/* Deselect: Chip Select high */
|
||||
LCD_CS_HIGH();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power on the LCD.
|
||||
* @param None
|
||||
* @retval int
|
||||
*/
|
||||
int ili9341_hw_init(void)
|
||||
{
|
||||
/* Initialize ILI9341 low level bus layer ----------------------------------*/
|
||||
LCD_GPIO_Init();
|
||||
|
||||
/* Configure LCD */
|
||||
ili9341_write_register(0xCA);
|
||||
ili9341_write_data(0xC3);
|
||||
ili9341_write_data(0x08);
|
||||
ili9341_write_data(0x50);
|
||||
ili9341_write_register(LCD_POWERB);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0xC1);
|
||||
ili9341_write_data(0x30);
|
||||
ili9341_write_register(LCD_POWER_SEQ);
|
||||
ili9341_write_data(0x64);
|
||||
ili9341_write_data(0x03);
|
||||
ili9341_write_data(0x12);
|
||||
ili9341_write_data(0x81);
|
||||
ili9341_write_register(LCD_DTCA);
|
||||
ili9341_write_data(0x85);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x78);
|
||||
ili9341_write_register(LCD_POWERA);
|
||||
ili9341_write_data(0x39);
|
||||
ili9341_write_data(0x2C);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x34);
|
||||
ili9341_write_data(0x02);
|
||||
ili9341_write_register(LCD_PRC);
|
||||
ili9341_write_data(0x20);
|
||||
ili9341_write_register(LCD_DTCB);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_register(LCD_FRMCTR1);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x1B);
|
||||
ili9341_write_register(LCD_DFC);
|
||||
ili9341_write_data(0x0A);
|
||||
ili9341_write_data(0xA2);
|
||||
ili9341_write_register(LCD_POWER1);
|
||||
ili9341_write_data(0x10);
|
||||
ili9341_write_register(LCD_POWER2);
|
||||
ili9341_write_data(0x10);
|
||||
ili9341_write_register(LCD_VCOM1);
|
||||
ili9341_write_data(0x45);
|
||||
ili9341_write_data(0x15);
|
||||
ili9341_write_register(LCD_VCOM2);
|
||||
ili9341_write_data(0x90);
|
||||
ili9341_write_register(LCD_MAC);
|
||||
ili9341_write_data(0xC8);
|
||||
ili9341_write_register(LCD_3GAMMA_EN);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_register(LCD_RGB_INTERFACE);
|
||||
ili9341_write_data(0xC2);
|
||||
ili9341_write_register(LCD_DFC);
|
||||
ili9341_write_data(0x0A);
|
||||
ili9341_write_data(0xA7);
|
||||
ili9341_write_data(0x27);
|
||||
ili9341_write_data(0x04);
|
||||
|
||||
/* Colomn address set */
|
||||
ili9341_write_register(LCD_COLUMN_ADDR);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0xEF);
|
||||
/* Page address set */
|
||||
ili9341_write_register(LCD_PAGE_ADDR);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x01);
|
||||
ili9341_write_data(0x3F);
|
||||
ili9341_write_register(LCD_INTERFACE);
|
||||
ili9341_write_data(0x01);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x06);
|
||||
|
||||
ili9341_write_register(LCD_GRAM);
|
||||
rt_thread_mdelay(20);
|
||||
|
||||
ili9341_write_register(LCD_GAMMA);
|
||||
ili9341_write_data(0x01);
|
||||
|
||||
ili9341_write_register(LCD_PGAMMA);
|
||||
ili9341_write_data(0x0F);
|
||||
ili9341_write_data(0x29);
|
||||
ili9341_write_data(0x24);
|
||||
ili9341_write_data(0x0C);
|
||||
ili9341_write_data(0x0E);
|
||||
ili9341_write_data(0x09);
|
||||
ili9341_write_data(0x4E);
|
||||
ili9341_write_data(0x78);
|
||||
ili9341_write_data(0x3C);
|
||||
ili9341_write_data(0x09);
|
||||
ili9341_write_data(0x13);
|
||||
ili9341_write_data(0x05);
|
||||
ili9341_write_data(0x17);
|
||||
ili9341_write_data(0x11);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_register(LCD_NGAMMA);
|
||||
ili9341_write_data(0x00);
|
||||
ili9341_write_data(0x16);
|
||||
ili9341_write_data(0x1B);
|
||||
ili9341_write_data(0x04);
|
||||
ili9341_write_data(0x11);
|
||||
ili9341_write_data(0x07);
|
||||
ili9341_write_data(0x31);
|
||||
ili9341_write_data(0x33);
|
||||
ili9341_write_data(0x42);
|
||||
ili9341_write_data(0x05);
|
||||
ili9341_write_data(0x0C);
|
||||
ili9341_write_data(0x0A);
|
||||
ili9341_write_data(0x28);
|
||||
ili9341_write_data(0x2F);
|
||||
ili9341_write_data(0x0F);
|
||||
|
||||
ili9341_write_register(LCD_SLEEP_OUT);
|
||||
rt_thread_mdelay(20);
|
||||
ili9341_write_register(LCD_DISPLAY_ON);
|
||||
/* GRAM start writing */
|
||||
ili9341_write_register(LCD_GRAM);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(ili9341_hw_init);
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* File : ili9341.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2020, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-11 RT-Thread the first version
|
||||
*/
|
||||
#ifndef __ILI9341_H
|
||||
#define __ILI9341_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief ILI9341 chip IDs
|
||||
*/
|
||||
#define ILI9341_ID 0x9341
|
||||
|
||||
/**
|
||||
* @brief ILI9341 Registers
|
||||
*/
|
||||
|
||||
/* Level 1 Commands */
|
||||
#define LCD_SWRESET 0x01 /* Software Reset */
|
||||
#define LCD_READ_DISPLAY_ID 0x04 /* Read display identification information */
|
||||
#define LCD_RDDST 0x09 /* Read Display Status */
|
||||
#define LCD_RDDPM 0x0A /* Read Display Power Mode */
|
||||
#define LCD_RDDMADCTL 0x0B /* Read Display MADCTL */
|
||||
#define LCD_RDDCOLMOD 0x0C /* Read Display Pixel Format */
|
||||
#define LCD_RDDIM 0x0D /* Read Display Image Format */
|
||||
#define LCD_RDDSM 0x0E /* Read Display Signal Mode */
|
||||
#define LCD_RDDSDR 0x0F /* Read Display Self-Diagnostic Result */
|
||||
#define LCD_SPLIN 0x10 /* Enter Sleep Mode */
|
||||
#define LCD_SLEEP_OUT 0x11 /* Sleep out register */
|
||||
#define LCD_PTLON 0x12 /* Partial Mode ON */
|
||||
#define LCD_NORMAL_MODE_ON 0x13 /* Normal Display Mode ON */
|
||||
#define LCD_DINVOFF 0x20 /* Display Inversion OFF */
|
||||
#define LCD_DINVON 0x21 /* Display Inversion ON */
|
||||
#define LCD_GAMMA 0x26 /* Gamma register */
|
||||
#define LCD_DISPLAY_OFF 0x28 /* Display off register */
|
||||
#define LCD_DISPLAY_ON 0x29 /* Display on register */
|
||||
#define LCD_COLUMN_ADDR 0x2A /* Colomn address register */
|
||||
#define LCD_PAGE_ADDR 0x2B /* Page address register */
|
||||
#define LCD_GRAM 0x2C /* GRAM register */
|
||||
#define LCD_RGBSET 0x2D /* Color SET */
|
||||
#define LCD_RAMRD 0x2E /* Memory Read */
|
||||
#define LCD_PLTAR 0x30 /* Partial Area */
|
||||
#define LCD_VSCRDEF 0x33 /* Vertical Scrolling Definition */
|
||||
#define LCD_TEOFF 0x34 /* Tearing Effect Line OFF */
|
||||
#define LCD_TEON 0x35 /* Tearing Effect Line ON */
|
||||
#define LCD_MAC 0x36 /* Memory Access Control register*/
|
||||
#define LCD_VSCRSADD 0x37 /* Vertical Scrolling Start Address */
|
||||
#define LCD_IDMOFF 0x38 /* Idle Mode OFF */
|
||||
#define LCD_IDMON 0x39 /* Idle Mode ON */
|
||||
#define LCD_PIXEL_FORMAT 0x3A /* Pixel Format register */
|
||||
#define LCD_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */
|
||||
#define LCD_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */
|
||||
#define LCD_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */
|
||||
#define LCD_GET_SCANLINE 0x45 /* Get Scanline */
|
||||
#define LCD_WDB 0x51 /* Write Brightness Display register */
|
||||
#define LCD_RDDISBV 0x52 /* Read Display Brightness */
|
||||
#define LCD_WCD 0x53 /* Write Control Display register*/
|
||||
#define LCD_RDCTRLD 0x54 /* Read CTRL Display */
|
||||
#define LCD_WRCABC 0x55 /* Write Content Adaptive Brightness Control */
|
||||
#define LCD_RDCABC 0x56 /* Read Content Adaptive Brightness Control */
|
||||
#define LCD_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */
|
||||
#define LCD_READ_CABC 0x5F /* Read CABC Minimum Brightness */
|
||||
#define LCD_READ_ID1 0xDA /* Read ID1 */
|
||||
#define LCD_READ_ID2 0xDB /* Read ID2 */
|
||||
#define LCD_READ_ID3 0xDC /* Read ID3 */
|
||||
|
||||
/* Level 2 Commands */
|
||||
#define LCD_RGB_INTERFACE 0xB0 /* RGB Interface Signal Control */
|
||||
#define LCD_FRMCTR1 0xB1 /* Frame Rate Control (In Normal Mode) */
|
||||
#define LCD_FRMCTR2 0xB2 /* Frame Rate Control (In Idle Mode) */
|
||||
#define LCD_FRMCTR3 0xB3 /* Frame Rate Control (In Partial Mode) */
|
||||
#define LCD_INVTR 0xB4 /* Display Inversion Control */
|
||||
#define LCD_BPC 0xB5 /* Blanking Porch Control register */
|
||||
#define LCD_DFC 0xB6 /* Display Function Control register */
|
||||
#define LCD_ETMOD 0xB7 /* Entry Mode Set */
|
||||
#define LCD_BACKLIGHT1 0xB8 /* Backlight Control 1 */
|
||||
#define LCD_BACKLIGHT2 0xB9 /* Backlight Control 2 */
|
||||
#define LCD_BACKLIGHT3 0xBA /* Backlight Control 3 */
|
||||
#define LCD_BACKLIGHT4 0xBB /* Backlight Control 4 */
|
||||
#define LCD_BACKLIGHT5 0xBC /* Backlight Control 5 */
|
||||
#define LCD_BACKLIGHT7 0xBE /* Backlight Control 7 */
|
||||
#define LCD_BACKLIGHT8 0xBF /* Backlight Control 8 */
|
||||
#define LCD_POWER1 0xC0 /* Power Control 1 register */
|
||||
#define LCD_POWER2 0xC1 /* Power Control 2 register */
|
||||
#define LCD_VCOM1 0xC5 /* VCOM Control 1 register */
|
||||
#define LCD_VCOM2 0xC7 /* VCOM Control 2 register */
|
||||
#define LCD_NVMWR 0xD0 /* NV Memory Write */
|
||||
#define LCD_NVMPKEY 0xD1 /* NV Memory Protection Key */
|
||||
#define LCD_RDNVM 0xD2 /* NV Memory Status Read */
|
||||
#define LCD_READ_ID4 0xD3 /* Read ID4 */
|
||||
#define LCD_PGAMMA 0xE0 /* Positive Gamma Correction register */
|
||||
#define LCD_NGAMMA 0xE1 /* Negative Gamma Correction register */
|
||||
#define LCD_DGAMCTRL1 0xE2 /* Digital Gamma Control 1 */
|
||||
#define LCD_DGAMCTRL2 0xE3 /* Digital Gamma Control 2 */
|
||||
#define LCD_INTERFACE 0xF6 /* Interface control register */
|
||||
|
||||
/* Extend register commands */
|
||||
#define LCD_POWERA 0xCB /* Power control A register */
|
||||
#define LCD_POWERB 0xCF /* Power control B register */
|
||||
#define LCD_DTCA 0xE8 /* Driver timing control A */
|
||||
#define LCD_DTCB 0xEA /* Driver timing control B */
|
||||
#define LCD_POWER_SEQ 0xED /* Power on sequence register */
|
||||
#define LCD_3GAMMA_EN 0xF2 /* 3 Gamma enable register */
|
||||
#define LCD_PRC 0xF7 /* Pump ratio control register */
|
||||
|
||||
/* Size of read registers */
|
||||
#define LCD_READ_ID4_SIZE 3 /* Size of Read ID4 */
|
||||
|
||||
|
||||
/** @defgroup ILI9341_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
int ili9341_hw_init(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ILI9341_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-08 bernard The first version for STM32F429 DISCO
|
||||
*/
|
||||
|
||||
#ifndef __LCD_PORT_H__
|
||||
#define __LCD_PORT_H__
|
||||
|
||||
/* 240 * 320 */
|
||||
#define LCD_WIDTH 240
|
||||
#define LCD_HEIGHT 320
|
||||
#define LCD_BITS_PER_PIXEL 16
|
||||
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
|
||||
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
|
||||
|
||||
#define LCD_HSYNC_WIDTH 10
|
||||
#define LCD_VSYNC_HEIGHT 2
|
||||
#define LCD_HBP 20
|
||||
#define LCD_VBP 2
|
||||
#define LCD_HFP 10
|
||||
#define LCD_VFP 5
|
||||
|
||||
#define LCD_BACKLIGHT_USING_GPIO
|
||||
#define LCD_BL_GPIO_NUM GET_PIN(D, 7)
|
||||
#define LCD_DISP_GPIO_NUM GET_PIN(D, 4)
|
||||
|
||||
#endif /* __LCD_PORT_H__ */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-08 bernard The first version for STM32F429 DISCO
|
||||
*/
|
||||
|
||||
#ifndef __SDRAM_PORT_H__
|
||||
#define __SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
/* Bank1 or Bank2 */
|
||||
#define SDRAM_TARGET_BANK 2
|
||||
/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */
|
||||
#define SDRAM_BANK_ADDR ((uint32_t)0XD0000000)
|
||||
/* data width: 8, 16, 32 */
|
||||
#define SDRAM_DATA_WIDTH 16
|
||||
/* column bit numbers: 8, 9, 10, 11 */
|
||||
#define SDRAM_COLUMN_BITS 8
|
||||
/* row bit numbers: 11, 12, 13 */
|
||||
#define SDRAM_ROW_BITS 12
|
||||
/* cas latency clock number: 1, 2, 3 */
|
||||
#define SDRAM_CAS_LATENCY 3
|
||||
/* read pipe delay: 0, 1, 2 */
|
||||
#define SDRAM_RPIPE_DELAY 1
|
||||
/* clock divid: 2, 3 */
|
||||
#define SDCLOCK_PERIOD 2
|
||||
/* refresh rate counter */
|
||||
#define SDRAM_REFRESH_COUNT ((uint32_t)0x056A)
|
||||
#define SDRAM_SIZE ((uint32_t)0x800000)
|
||||
|
||||
/* Timing configuration for IS42S16400J */
|
||||
/* 90 MHz of SD clock frequency (180MHz/2) */
|
||||
/* TMRD: 2 Clock cycles */
|
||||
#define LOADTOACTIVEDELAY 2
|
||||
/* TXSR: 7x11.90ns */
|
||||
#define EXITSELFREFRESHDELAY 7
|
||||
/* TRAS: 4x11.90ns */
|
||||
#define SELFREFRESHTIME 4
|
||||
/* TRC: 7x11.90ns */
|
||||
#define ROWCYCLEDELAY 7
|
||||
/* TWR: 2 Clock cycles */
|
||||
#define WRITERECOVERYTIME 2
|
||||
/* TRP: 2x11.90ns */
|
||||
#define RPDELAY 2
|
||||
/* TRCD: 2x11.90ns */
|
||||
#define RCDDELAY 2
|
||||
|
||||
/* memory mode register */
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
|
||||
#endif
|
||||
|
|
@ -26,12 +26,13 @@
|
|||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
#define RT_USING_SIGNALS
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_MEMHEAP_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
|
@ -40,7 +41,7 @@
|
|||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40002
|
||||
#define RT_VER_NUM 0x40003
|
||||
#define ARCH_ARM
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
|
|
@ -69,6 +70,7 @@
|
|||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_USING_MSH_ONLY
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
|
@ -90,13 +92,15 @@
|
|||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
|
||||
#define RT_USING_SPI
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_USING_PTHREADS
|
||||
#define PTHREAD_NUM_MAX 8
|
||||
#define RT_USING_POSIX
|
||||
|
||||
/* Network */
|
||||
|
|
@ -158,6 +162,12 @@
|
|||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* Privated Packages of RealThread */
|
||||
|
||||
|
||||
/* Network Utilities */
|
||||
|
||||
#define SOC_FAMILY_STM32
|
||||
#define SOC_SERIES_STM32F4
|
||||
|
||||
|
|
@ -165,11 +175,18 @@
|
|||
|
||||
#define SOC_STM32F429ZI
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_SDRAM
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_USING_FMC
|
||||
#define BSP_USING_LCD
|
||||
#define BSP_USING_LTDC
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue