[bsp/renesas/ra2l1-cpk] 添加RA2L1-CPK开发板BSP
[bsp/renesas] 更新flash、gpio驱动和配置头文件。更新FSP配置文档
This commit is contained in:
Sherman
guo
parent
37fcfdb972
commit
5a67132cf8
@ -5,9 +5,11 @@ RA 系列 BSP 目前支持情况如下表所示：
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| **BSP 文件夹名称** | **开发板名称** |
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|:------------------------- |:-------------------------- |
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| **RA6 系列** | |
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| **RA6 系列** | |
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| [ra6m4-cpk](ra6m4-cpk) | Renesas 官方 CPK-RA6M4 开发板 |
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| [ra6m4-iot](ra6m4-iot) | Renesas 官方 IOT-RA6M4 开发板 |
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| **RA2 系列** | |
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| [ra2l1-cpk](ra2l1-cpk) | Renesas 官方 CPK-RA2L1 开发板 |
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可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
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@ -63,7 +63,7 @@ How to add an IO interrupt?
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3. Create stack and enter configuration. Because it needs to adapt to the naming used in the RT-Thread driver, it is necessary to modify the naming and set **name** , **channel** , **callback** to be the same label. Select the trigger method you want, and finally save the configuration to generate the configuration code.
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3. Create stack and enter configuration. Because it needs to adapt to the naming used in the RT-Thread driver, it is necessary to modify the naming and set **name** , **channel** to be the same label. Select the trigger method you want, and finally save the configuration to generate the configuration code.
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@ -63,7 +63,7 @@ RA系列已更新 **FSP 3.5.0** 版本的支持，请使用 **FSP 3.5.0** 版本
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3. 创建 stack 并进入配置。因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置 **name** 、**channel** 、**callback** 为一致的标号。选择你希望的触发方式，最后保存配置，生成配置代码。
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3. 创建 stack 并进入配置。因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置 **name** 、**channel** 为一致的标号，**callback**统一命名为`irq_callback`。选择你希望的触发方式，最后保存配置，生成配置代码。
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41
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/adc_config.h
Normal file
41
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/adc_config.h
Normal file
@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-19 Mr.Tiger first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
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struct ra_adc_map
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{
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char name;
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const adc_cfg_t *g_cfg;
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const adc_instance_ctrl_t *g_ctrl;
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const adc_channel_cfg_t *g_channel_cfg;
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};
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struct ra_dev
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{
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rt_adc_device_t ra_adc_device_t;
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struct ra_adc_map *ra_adc_dev;
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};
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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48
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/can_config.h
Normal file
48
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/can_config.h
Normal file
@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-29 mazhiyuan first version
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*/
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#ifndef __CAN_CONFIG_H__
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#define __CAN_CONFIG_H__
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#include <rtthread.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_CAN0)
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#ifndef CAN0_CONFIG
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#define CAN0_CONFIG \
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{ \
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.name = "can0", \
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.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0, \
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.p_api_ctrl = &g_can0_ctrl, \
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.p_cfg = &g_can0_cfg, \
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}
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#endif /* CAN0_CONFIG */
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#endif /* BSP_USING_CAN0 */
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#if defined(BSP_USING_CAN1)
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#ifndef CAN1_CONFIG
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#define CAN1_CONFIG \
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{ \
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.name = "can1", \
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.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1, \
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.p_api_ctrl = &g_can1_ctrl, \
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.p_cfg = &g_can1_cfg, \
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}
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#endif /* CAN1_CONFIG */
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#endif /* BSP_USING_CAN1 */
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#ifdef __cplusplus
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}
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#endif
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#endif
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41
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/dac_config.h
Normal file
41
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/dac_config.h
Normal file
@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-19 Mr.Tiger first version
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*/
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#ifndef __DAC_CONFIG_H__
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#define __DAC_CONFIG_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_DAC
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struct ra_dac_map
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{
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char name;
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const struct st_dac_cfg *g_cfg;
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const struct st_dac_instance_ctrl *g_ctrl;
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};
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struct ra_dac_dev
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{
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rt_dac_device_t ra_dac_device_t;
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struct ra_dac_map *ra_dac_map_dev;
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};
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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68
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/pwm_config.h
Normal file
68
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/pwm_config.h
Normal file
@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-26 KevinXu first version
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#include <drv_config.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum
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{
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#ifdef BSP_USING_PWM0
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BSP_PWM0_INDEX,
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#endif
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#ifdef BSP_USING_PWM1
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BSP_PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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BSP_PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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BSP_PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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BSP_PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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BSP_PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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BSP_PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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BSP_PWM7_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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BSP_PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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BSP_PWM9_INDEX,
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#endif
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BSP_PWMS_NUM
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};
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#define PWM_DRV_INITIALIZER(num) \
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{ \
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.name = "pwm"#num , \
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.g_cfg = &g_timer##num##_cfg, \
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.g_ctrl = &g_timer##num##_ctrl, \
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.g_timer = &g_timer##num, \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PWM_CONFIG_H__ */
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80
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/uart_config.h
Normal file
80
bsp/renesas/libraries/HAL_Drivers/config/ra2l1/uart_config.h
Normal file
@ -0,0 +1,80 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-07-29 KyleChan first version
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*/
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#ifndef __UART_CONFIG_H__
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#define __UART_CONFIG_H__
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#include <rtthread.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_UART0)
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#ifndef UART0_CONFIG
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#define UART0_CONFIG \
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{ \
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.name = "uart0", \
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.p_api_ctrl = &g_uart0_ctrl, \
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.p_cfg = &g_uart0_cfg, \
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}
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#endif /* UART0_CONFIG */
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#endif /* BSP_USING_UART0 */
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#if defined(BSP_USING_UART1)
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#ifndef UART1_CONFIG
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#define UART1_CONFIG \
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{ \
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.name = "uart1", \
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.p_api_ctrl = &g_uart1_ctrl, \
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.p_cfg = &g_uart1_cfg, \
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}
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#endif /* UART1_CONFIG */
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#endif /* BSP_USING_UART1 */
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#if defined(BSP_USING_UART2)
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#ifndef UART2_CONFIG
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#define UART2_CONFIG \
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{ \
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.name = "uart2", \
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.p_api_ctrl = &g_uart2_ctrl, \
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.p_cfg = &g_uart2_cfg, \
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}
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#endif /* UART2_CONFIG */
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#endif /* BSP_USING_UART2 */
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#if defined(BSP_USING_UART3)
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#ifndef UART3_CONFIG
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#define UART3_CONFIG \
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{ \
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.name = "uart3", \
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.p_api_ctrl = &g_uart3_ctrl, \
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.p_cfg = &g_uart3_cfg, \
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}
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#endif /* UART3_CONFIG */
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#endif /* BSP_USING_UART3 */
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#if defined(BSP_USING_UART9)
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#ifndef UART9_CONFIG
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#define UART9_CONFIG \
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{ \
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.name = "uart9", \
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.p_api_ctrl = &g_uart9_ctrl, \
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.p_cfg = &g_uart9_cfg, \
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}
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#endif /* UART9_CONFIG */
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#endif /* BSP_USING_UART9 */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -14,9 +14,8 @@
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#include "board.h"
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#include "hal_data.h"
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#include "drv_flash.h"
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#include <rtthread.h>
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#include "drv_common.h"
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#if defined(RT_USING_FAL)
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#include "fal.h"
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@ -31,18 +30,40 @@
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#endif /* DRV_DEBUG */
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#include <rtdbg.h>
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#if BSP_FEATURE_FLASH_HP_VERSION
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/* FLASH API */
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#define R_FLASH_Open R_FLASH_HP_Open
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#define R_FLASH_Reset R_FLASH_HP_Reset
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#define R_FLASH_Write R_FLASH_HP_Write
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#define R_FLASH_Erase R_FLASH_HP_Erase
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#define R_FLASH_StartUpAreaSelect R_FLASH_HP_StartUpAreaSelect
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/* BSP_FEATURE_FLASH */
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#define FLASH_CF_WRITE_SIZE BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE
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#else /* FLASH LP */
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/* FLASH API */
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#define R_FLASH_Open R_FLASH_LP_Open
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#define R_FLASH_Reset R_FLASH_LP_Reset
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#define R_FLASH_Write R_FLASH_LP_Write
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#define R_FLASH_Erase R_FLASH_LP_Erase
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#define R_FLASH_StartUpAreaSelect R_FLASH_LP_StartUpAreaSelect
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/* BSP_FEATURE_FLASH */
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#define FLASH_CF_WRITE_SIZE BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE
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#endif
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int _flash_init(void)
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{
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fsp_err_t err = FSP_SUCCESS;
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/* Open Flash_HP */
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err = R_FLASH_HP_Open(&g_flash_ctrl, &g_flash_cfg);
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err = R_FLASH_Open(&g_flash_ctrl, &g_flash_cfg);
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/* Handle Error */
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if (FSP_SUCCESS != err)
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{
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LOG_E("\r\n Flah_HP_Open API failed");
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}
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/* Setup Default Block 0 as Startup Setup Block */
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err = R_FLASH_HP_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
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err = R_FLASH_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
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if (err != FSP_SUCCESS)
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{
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LOG_E("\r\n Flah_HP_StartUpAreaSelect API failed");
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@ -90,18 +111,18 @@ int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
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fsp_err_t err = FSP_SUCCESS;
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size_t written_size = 0;
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if (size % BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE)
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if (size % FLASH_CF_WRITE_SIZE)
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{
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LOG_E("Flash Write size must be an integer multiple of %d", BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
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LOG_E("Flash Write size must be an integer multiple of %d", FLASH_CF_WRITE_SIZE);
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return -RT_EINVAL;
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}
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while (written_size < size)
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{
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level = rt_hw_interrupt_disable();
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R_FLASH_HP_Reset(&g_flash_ctrl);
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R_FLASH_Reset(&g_flash_ctrl);
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/* Write code flash data*/
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err = R_FLASH_HP_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
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err = R_FLASH_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, FLASH_CF_WRITE_SIZE);
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rt_hw_interrupt_enable(level);
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/* Error Handle */
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@ -111,7 +132,7 @@ int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
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return -RT_EIO;
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}
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written_size += BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE;
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written_size += FLASH_CF_WRITE_SIZE;
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}
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if (result != RT_EOK)
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@ -132,12 +153,20 @@ int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
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*
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* @return result
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*/
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int _flash_erase_8k(rt_uint32_t addr, size_t size)
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#if BSP_FEATURE_FLASH_HP_VERSION
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int _flash_hp0_erase(rt_uint32_t addr, size_t size)
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#else
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int _flash_lp_erase(rt_uint32_t addr, size_t size)
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#endif
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{
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fsp_err_t err = FSP_SUCCESS;
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rt_base_t level;
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#if BSP_FEATURE_FLASH_HP_VERSION
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if ((addr + size) > BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE)
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#else
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if ((addr + size) > BSP_ROM_SIZE_BYTES)
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#endif
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{
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LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
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return -RT_EINVAL;
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@ -149,14 +178,22 @@ int _flash_erase_8k(rt_uint32_t addr, size_t size)
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}
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level = rt_hw_interrupt_disable();
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R_FLASH_HP_Reset(&g_flash_ctrl);
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R_FLASH_Reset(&g_flash_ctrl);
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/* Erase Block */
|
||||
err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_8KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE + 1);
|
||||
#if BSP_FEATURE_FLASH_HP_VERSION
|
||||
err = R_FLASH_Erase(&g_flash_ctrl,
|
||||
RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE),
|
||||
((size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE + 1));
|
||||
#else
|
||||
err = R_FLASH_Erase(&g_flash_ctrl,
|
||||
RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE),
|
||||
((size - 1) / BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE + 1));
|
||||
#endif
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
if (err != FSP_SUCCESS)
|
||||
{
|
||||
LOG_E("Erase API failed");
|
||||
LOG_E("Erase failed:addr (0x%p), size %d", (void *)addr, size);
|
||||
return -RT_EIO;
|
||||
}
|
||||
|
||||
@ -164,7 +201,8 @@ int _flash_erase_8k(rt_uint32_t addr, size_t size)
|
||||
return size;
|
||||
}
|
||||
|
||||
int _flash_erase_32k(rt_uint32_t addr, size_t size)
|
||||
#if BSP_FEATURE_FLASH_HP_VERSION
|
||||
int _flash_hp1_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
rt_base_t level;
|
||||
@ -175,9 +213,9 @@ int _flash_erase_32k(rt_uint32_t addr, size_t size)
|
||||
}
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
R_FLASH_HP_Reset(&g_flash_ctrl);
|
||||
R_FLASH_Reset(&g_flash_ctrl);
|
||||
/* Erase Block */
|
||||
err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_32KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE + 1);
|
||||
err = R_FLASH_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE + 1);
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
if (err != FSP_SUCCESS)
|
||||
@ -189,84 +227,164 @@ int _flash_erase_32k(rt_uint32_t addr, size_t size)
|
||||
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
|
||||
return size;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_FAL)
|
||||
|
||||
static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
|
||||
#define FLASH_START_ADDRESS 0x00000000
|
||||
|
||||
static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
#if BSP_FEATURE_FLASH_HP_VERSION
|
||||
|
||||
static int fal_flash_erase_8k(long offset, size_t size);
|
||||
static int fal_flash_erase_32k(long offset, size_t size);
|
||||
static int fal_flash_hp0_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_hp0_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_hp0_erase(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev _onchip_flash_8k = { "onchip_flash_8k", FLASH_HP_CF_BLCOK_0, FLASH_HP_CF_BLOCK_8, (8 * 1024), {_flash_init, fal_flash_read_8k, fal_flash_write_8k, fal_flash_erase_8k} };
|
||||
const struct fal_flash_dev _onchip_flash_32k = { "onchip_flash_32k", FLASH_HP_CF_BLOCK_8, 32 * 30 * 1024, (32 * 1024), {_flash_init, fal_flash_read_32k, fal_flash_write_32k, fal_flash_erase_32k} };
|
||||
static int fal_flash_hp1_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_hp1_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_hp1_erase(long offset, size_t size);
|
||||
|
||||
static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size)
|
||||
const struct fal_flash_dev _onchip_flash_hp0 =
|
||||
{
|
||||
return _flash_read(_onchip_flash_8k.addr + offset, buf, size);
|
||||
"onchip_flash_hp0",
|
||||
FLASH_START_ADDRESS,
|
||||
BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE,
|
||||
BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE,
|
||||
{
|
||||
_flash_init,
|
||||
fal_flash_hp0_read,
|
||||
fal_flash_hp0_write,
|
||||
fal_flash_hp0_erase
|
||||
},
|
||||
(BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE * 8)
|
||||
};
|
||||
const struct fal_flash_dev _onchip_flash_hp1 =
|
||||
{
|
||||
"onchip_flash_hp1",
|
||||
BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE,
|
||||
(BSP_ROM_SIZE_BYTES - BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE),
|
||||
BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE,
|
||||
{
|
||||
_flash_init,
|
||||
fal_flash_hp1_read,
|
||||
fal_flash_hp1_write,
|
||||
fal_flash_hp1_erase
|
||||
},
|
||||
(BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE * 8)
|
||||
};
|
||||
|
||||
/* code flash region0 */
|
||||
static int fal_flash_hp0_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return _flash_read(_onchip_flash_hp0.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size)
|
||||
static int fal_flash_hp0_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return _flash_read(_onchip_flash_32k.addr + offset, buf, size);
|
||||
return _flash_write(_onchip_flash_hp0.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
static int fal_flash_hp0_erase(long offset, size_t size)
|
||||
{
|
||||
return _flash_write(_onchip_flash_8k.addr + offset, buf, size);
|
||||
return _flash_hp0_erase(_onchip_flash_hp0.addr + offset, size);
|
||||
}
|
||||
/* code flash region1 */
|
||||
static int fal_flash_hp1_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return _flash_read(_onchip_flash_hp1.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
static int fal_flash_hp1_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return _flash_write(_onchip_flash_32k.addr + offset, buf, size);
|
||||
return _flash_write(_onchip_flash_hp1.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase_8k(long offset, size_t size)
|
||||
static int fal_flash_hp1_erase(long offset, size_t size)
|
||||
{
|
||||
return _flash_erase_8k(_onchip_flash_8k.addr + offset, size);
|
||||
return _flash_hp1_erase(_onchip_flash_hp1.addr + offset, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase_32k(long offset, size_t size)
|
||||
#else /* flash lp code flash */
|
||||
|
||||
static int fal_flash_lp_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_lp_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_lp_erase(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev _onchip_flash_lp =
|
||||
{
|
||||
return _flash_erase_32k(_onchip_flash_32k.addr + offset, size);
|
||||
"onchip_flash_lp",
|
||||
FLASH_START_ADDRESS,
|
||||
BSP_ROM_SIZE_BYTES,
|
||||
BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE,
|
||||
{
|
||||
_flash_init,
|
||||
fal_flash_lp_read,
|
||||
fal_flash_lp_write,
|
||||
fal_flash_lp_erase
|
||||
},
|
||||
(BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE * 8)
|
||||
};
|
||||
|
||||
static int fal_flash_lp_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return _flash_read(_onchip_flash_lp.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_lp_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return _flash_write(_onchip_flash_lp.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_lp_erase(long offset, size_t size)
|
||||
{
|
||||
return _flash_lp_erase(_onchip_flash_lp.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int flash_test(void)
|
||||
{
|
||||
#define TEST_OFF (_onchip_flash_32k.len - BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
|
||||
#if BSP_FEATURE_FLASH_HP_VERSION
|
||||
#define TEST_OFF (_onchip_flash_hp1.len - BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
|
||||
#else
|
||||
#define TEST_OFF (_onchip_flash_lp.len - BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE)
|
||||
#endif
|
||||
const struct fal_partition *param;
|
||||
uint8_t write_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
|
||||
uint8_t read_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
|
||||
uint8_t write_buffer[FLASH_CF_WRITE_SIZE] = {0};
|
||||
uint8_t read_buffer[FLASH_CF_WRITE_SIZE] = {0};
|
||||
|
||||
/* Set write buffer, clear read buffer */
|
||||
for (uint8_t index = 0; index < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; index++)
|
||||
for (uint8_t index = 0; index < FLASH_CF_WRITE_SIZE; index++)
|
||||
{
|
||||
write_buffer[index] = index;
|
||||
read_buffer[index] = 0;
|
||||
}
|
||||
|
||||
fal_init();
|
||||
|
||||
#if BSP_FEATURE_FLASH_HP_VERSION
|
||||
param = fal_partition_find("param");
|
||||
#else
|
||||
param = fal_partition_find("app");
|
||||
#endif
|
||||
if (param == RT_NULL)
|
||||
{
|
||||
LOG_E("not find partition param!");
|
||||
return -1;
|
||||
}
|
||||
LOG_I("Erase Start...");
|
||||
#if BSP_FEATURE_FLASH_HP_VERSION
|
||||
fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE);
|
||||
#else
|
||||
fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE);
|
||||
#endif
|
||||
LOG_I("Erase succeeded!");
|
||||
LOG_I("Write Start...");
|
||||
fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
|
||||
LOG_I("Write succeeded!");
|
||||
LOG_I("Read Start...");
|
||||
fal_partition_read(param, TEST_OFF, read_buffer, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
|
||||
fal_partition_read(param, TEST_OFF, read_buffer, FLASH_CF_WRITE_SIZE);
|
||||
LOG_I("Read succeeded!");
|
||||
|
||||
for (int i = 0; i < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; i++)
|
||||
for (int i = 0; i < FLASH_CF_WRITE_SIZE; i++)
|
||||
{
|
||||
if (read_buffer[i] != write_buffer[i])
|
||||
{
|
||||
|
||||
@ -1,64 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-11-30 flybreak first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_FLASH_H__
|
||||
#define __DRV_FLASH_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Code Flash */
|
||||
#define FLASH_HP_CF_BLOCK_SIZE_32KB (32*1024) /* Block Size 32 KB */
|
||||
#define FLASH_HP_CF_BLOCK_SIZE_8KB (8*1024) /* Block Size 8KB */
|
||||
|
||||
#define FLASH_HP_CF_BLCOK_0 0x00000000U /* 8 KB: 0x00000000 - 0x00001FFF */
|
||||
#define FLASH_HP_CF_BLOCK_1 0x00002000U /* 8 KB: 0x00002000 - 0x00003FFF */
|
||||
#define FLASH_HP_CF_BLOCK_2 0x00004000U /* 8 KB: 0x00004000 - 0x00005FFF */
|
||||
#define FLASH_HP_CF_BLOCK_3 0x00006000U /* 8 KB: 0x00006000 - 0x00007FFF */
|
||||
#define FLASH_HP_CF_BLOCK_4 0x00008000U /* 8 KB: 0x00008000 - 0x00009FFF */
|
||||
#define FLASH_HP_CF_BLOCK_5 0x0000A000U /* 8 KB: 0x0000A000 - 0x0000BFFF */
|
||||
#define FLASH_HP_CF_BLOCK_6 0x0000C000U /* 8 KB: 0x0000C000 - 0x0000DFFF */
|
||||
#define FLASH_HP_CF_BLOCK_7 0x0000E000U /* 8 KB: 0x0000E000 - 0x0000FFFF */
|
||||
#define FLASH_HP_CF_BLOCK_8 0x00010000U /* 32 KB: 0x00010000 - 0x00017FFF */
|
||||
#define FLASH_HP_CF_BLOCK_9 0x00018000U /* 32 KB: 0x00018000 - 0x0001FFFF */
|
||||
#define FLASH_HP_CF_BLCOK_10 0x00020000U /* 32 KB: 0x00020000 - 0x0004FFFF */
|
||||
|
||||
#define FLASH_HP_DF_BLOCK_SIZE (64)
|
||||
/* Data Flash */
|
||||
#if (defined (BOARD_RA6M4_EK) || defined (BOARD_RA6M5_EK) || defined (BOARD_RA4M3_EK)||defined(BOARD_RA4M2_EK))
|
||||
|
||||
#define FLASH_HP_DF_BLOCK_0 0x08000000U /* 64 B: 0x40100000 - 0x4010003F */
|
||||
#define FLASH_HP_DF_BLOCK_1 0x08000040U /* 64 B: 0x40100040 - 0x4010007F */
|
||||
#define FLASH_HP_DF_BLOCK_2 0x08000080U /* 64 B: 0x40100080 - 0x401000BF */
|
||||
#define FLASH_HP_DF_BLOCK_3 0x080000C0U /* 64 B: 0x401000C0 - 0x401000FF */
|
||||
|
||||
#else
|
||||
|
||||
#define FLASH_HP_DF_BLOCK_0 0x40100000U /* 64 B: 0x40100000 - 0x4010003F */
|
||||
#define FLASH_HP_DF_BLOCK_1 0x40100040U /* 64 B: 0x40100040 - 0x4010007F */
|
||||
#define FLASH_HP_DF_BLOCK_2 0x40100080U /* 64 B: 0x40100080 - 0x401000BF */
|
||||
#define FLASH_HP_DF_BLOCK_3 0x401000C0U /* 64 B: 0x401000C0 - 0x401000FF */
|
||||
|
||||
#endif
|
||||
|
||||
#define BLOCK_SIZE (128)
|
||||
#define BLOCK_NUM (2)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_FLASH_H__ */
|
||||
@ -340,162 +340,12 @@ int rt_hw_pin_init(void)
|
||||
}
|
||||
|
||||
#ifdef R_ICU_H
|
||||
void irq0_callback(external_irq_callback_args_t *p_args)
|
||||
void irq_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (0 == pin_irq_hdr_tab[0].pin)
|
||||
if (p_args->channel == pin_irq_hdr_tab[p_args->channel].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[0].hdr(pin_irq_hdr_tab[0].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq1_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (1 == pin_irq_hdr_tab[1].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[1].hdr(pin_irq_hdr_tab[1].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq2_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (2 == pin_irq_hdr_tab[2].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[2].hdr(pin_irq_hdr_tab[2].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq3_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (3 == pin_irq_hdr_tab[3].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[3].hdr(pin_irq_hdr_tab[3].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq4_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (4 == pin_irq_hdr_tab[4].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[4].hdr(pin_irq_hdr_tab[4].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq5_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (5 == pin_irq_hdr_tab[5].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[5].hdr(pin_irq_hdr_tab[5].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq6_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (6 == pin_irq_hdr_tab[6].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[6].hdr(pin_irq_hdr_tab[6].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq7_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (7 == pin_irq_hdr_tab[7].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[7].hdr(pin_irq_hdr_tab[7].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq8_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (8 == pin_irq_hdr_tab[8].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[8].hdr(pin_irq_hdr_tab[8].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq9_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (9 == pin_irq_hdr_tab[9].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[9].hdr(pin_irq_hdr_tab[9].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq10_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (10 == pin_irq_hdr_tab[10].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[10].hdr(pin_irq_hdr_tab[10].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq11_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (11 == pin_irq_hdr_tab[11].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[11].hdr(pin_irq_hdr_tab[11].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq12_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (12 == pin_irq_hdr_tab[12].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[12].hdr(pin_irq_hdr_tab[12].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq13_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (13 == pin_irq_hdr_tab[13].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[13].hdr(pin_irq_hdr_tab[13].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq14_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (14 == pin_irq_hdr_tab[14].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[14].hdr(pin_irq_hdr_tab[14].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
void irq15_callback(external_irq_callback_args_t *p_args)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
if (15 == pin_irq_hdr_tab[15].pin)
|
||||
{
|
||||
pin_irq_hdr_tab[15].hdr(pin_irq_hdr_tab[15].args);
|
||||
pin_irq_hdr_tab[p_args->channel].hdr(pin_irq_hdr_tab[p_args->channel].args);
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
};
|
||||
|
||||
5
bsp/renesas/ra2l1-cpk/.gitignore
vendored
Normal file
5
bsp/renesas/ra2l1-cpk/.gitignore
vendored
Normal file
@ -0,0 +1,5 @@
|
||||
/RTE
|
||||
/Listings
|
||||
/Objects
|
||||
ra_cfg.txt
|
||||
|
||||
9
bsp/renesas/ra2l1-cpk/.ignore_format.yml
Normal file
9
bsp/renesas/ra2l1-cpk/.ignore_format.yml
Normal file
@ -0,0 +1,9 @@
|
||||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
dir_path:
|
||||
- ra
|
||||
- ra_gen
|
||||
- ra_cfg
|
||||
- RTE
|
||||
21
bsp/renesas/ra2l1-cpk/.settings/standalone.prefs
Normal file
21
bsp/renesas/ra2l1-cpk/.settings/standalone.prefs
Normal file
@ -0,0 +1,21 @@
|
||||
#Fri Jul 22 15:41:36 CST 2022
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=2985489297,ra/board/ra2l1_cpk/board_init.h|383876238,ra/board/ra2l1_cpk/board_leds.h|2918861270,ra/board/ra2l1_cpk/board_leds.c|586415029,ra/board/ra2l1_cpk/board.h|1521504391,ra/board/ra2l1_cpk/board_init.c
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2425160085,ra/fsp/inc/api/bsp_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2208590403,ra/fsp/inc/instances/r_ioport.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3297195641,ra/fsp/inc/fsp_version.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1728953905,ra/fsp/inc/fsp_features.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#R7FA2L1AB2DFM\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
|
||||
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|1906465970,ra/fsp/inc/api/r_external_irq_api.h|3018483678,ra/fsp/src/r_icu/r_icu.c
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h
|
||||
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.629312687=false
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
|
||||
29
bsp/renesas/ra2l1-cpk/Kconfig
Normal file
29
bsp/renesas/ra2l1-cpk/Kconfig
Normal file
@ -0,0 +1,29 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
# you can change the RTT_ROOT default "../.." to your rtthread_root,
|
||||
# example : default "F:/git_repositories/rt-thread"
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
config ENV_DIR
|
||||
string
|
||||
option env="ENV_ROOT"
|
||||
default "/"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../libraries/Kconfig"
|
||||
source "$BSP_DIR/board/Kconfig"
|
||||
22
bsp/renesas/ra2l1-cpk/R7FA2L1AB2DFM.pincfg
Normal file
22
bsp/renesas/ra2l1-cpk/R7FA2L1AB2DFM.pincfg
Normal file
@ -0,0 +1,22 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
|
||||
<v1:pinMappingsRef version="2.05" file="" />
|
||||
<v1:deviceSetting id="renesas.ra2l1_fm" pattern="R7FA2L1****FM">
|
||||
<v1:packageSetting id="renesas.64lqfp" />
|
||||
</v1:deviceSetting>
|
||||
<v1:configSetting configurationId="debug0.mode" altId="debug0.mode.swd" />
|
||||
<v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
|
||||
<v1:configSetting configurationId="p108" altId="p108.debug0.swdio">
|
||||
<v1:connectionSetting altId="debug0.swdio.p108" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="debug0.swdio" altId="debug0.swdio.p108">
|
||||
<v1:connectionSetting altId="p108.debug0.swdio" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
|
||||
<v1:configSetting configurationId="p300" altId="p300.debug0.swclk">
|
||||
<v1:connectionSetting altId="debug0.swclk.p300" />
|
||||
</v1:configSetting>
|
||||
<v1:configSetting configurationId="debug0.swclk" altId="debug0.swclk.p300">
|
||||
<v1:connectionSetting altId="p300.debug0.swclk" />
|
||||
</v1:configSetting>
|
||||
</v1:pinSettings>
|
||||
168
bsp/renesas/ra2l1-cpk/README.md
Normal file
168
bsp/renesas/ra2l1-cpk/README.md
Normal file
@ -0,0 +1,168 @@
|
||||
# 瑞萨 CPK-RA2L1 开发板
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为瑞萨 CPK-RA2L1 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板介绍
|
||||
- BSP 快速上手指南
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
CPK-RA2L1 评估板可通过灵活配置软件包和 IDE，可帮助用户对[RA2L1 MCU 群组](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra2l1-48mhz-arm-cortex-m23-ultra-low-power-general-purpose-microcontroller)的特性轻松进行评估，并对嵌入系统应用程序进行开发。
|
||||
|
||||
开发板正面外观如下图：
|
||||
|
||||
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：R7FA2L1AB2DFM，48MHz，Arm Cortex®-M23 内核，256kB 代码闪存, 32kB SRAM
|
||||
- 调试接口：板载 J-Link 接口
|
||||
- 扩展接口：两个 PMOD 连接器
|
||||
|
||||
**更多详细资料及工具**
|
||||
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
**硬件连接**
|
||||
|
||||
使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART9：P109(TXD)、P110(RXD)。
|
||||
|
||||
|
||||
|
||||
**编译下载**
|
||||
|
||||
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
|
||||
|
||||
> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
|
||||
|
||||
- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA6M4AF，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
**查看运行结果**
|
||||
|
||||
下载程序成功之后，系统会自动运行并打印系统信息。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.1.0 build Jul 7 2022 14:44:40
|
||||
2006 - 2022 Copyright by RT-Thread team
|
||||
|
||||
Hello RT-Thread!
|
||||
msh >
|
||||
msh >
|
||||
RT-Thread shell commands:
|
||||
reboot - Reboot System
|
||||
help - RT - Thread shell help.
|
||||
ps - List threads in the system.
|
||||
free - Show the memory usage in the system.
|
||||
hello - say hello world
|
||||
clear - clear the terminal screen
|
||||
version - show RT - Thread version information
|
||||
list_thread - list thread
|
||||
list_sem - list semaphore in system
|
||||
list_event - list event in system
|
||||
list_mutex - list mutex in system
|
||||
list_mailbox - list mail box in system
|
||||
list_msgqueue - list message queue in system
|
||||
list_timer - list timer in system
|
||||
list_device - list device in system
|
||||
list - list all commands in system
|
||||
icu_sample - icu sample
|
||||
|
||||
msh >
|
||||
```
|
||||
|
||||
**应用入口函数**
|
||||
|
||||
应用层的入口函数在 **bsp\ra6m4-cpk\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
|
||||
|
||||
```c
|
||||
void hal_entry(void)
|
||||
{
|
||||
rt_kprintf("\nHello RT-Thread!\n");
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED3_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED3_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
**资料及文档**
|
||||
|
||||
- [开发板官网主页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra2l1-evaluation-board#overview)
|
||||
- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
|
||||
- [datasheet](https://www2.renesas.cn/cn/zh/document/dst/ra2l1-group-datasheet?language=en&r=1596841)
|
||||
- [User’s Manual: Hardware](https://www2.renesas.cn/jp/zh/document/mah/ra2l1-group-users-manual-hardware?language=en&r=1398061)
|
||||
|
||||
**FSP 配置**
|
||||
|
||||
需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
|
||||
|
||||
1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 3.5.0 版本
|
||||
2. 下载安装完成后，需要添加 CPK-RA6M4 开发板的官方板级支持包
|
||||
> 打开[ 开发板详情页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra2l1-evaluation-board#overview)，在**“软件下载”**列表中找到 **CPK-RA2L1板级支持包**，点击链接即可下载
|
||||
3. 如何将 **板级支持包**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/cn/zh/document/gde/1596896?language=zh&r=1596841)
|
||||
4. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
|
||||
|
||||
**ENV 配置**
|
||||
|
||||
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
|
||||
|
||||
此 BSP 默认只开启了UART和IRQ3外设功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
|
||||
|
||||
步骤如下：
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
4. 输入`scons --target=mdk5` 命令重新生成工程。
|
||||
|
||||
|
||||
## FAQ
|
||||
|
||||
### 使用 MDK 的 DEBUG 时如果遇到提示 “Error: Flash Download failed Cortex-M23” 怎么办？
|
||||
|
||||
可按照下图操作，修改 Utilities 中的选项：
|
||||
|
||||
|
||||
|
||||
## 联系人信息
|
||||
|
||||
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
|
||||
|
||||
## 贡献代码
|
||||
|
||||
如果您对此BSP感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
|
||||
30
bsp/renesas/ra2l1-cpk/SConscript
Normal file
30
bsp/renesas/ra2l1-cpk/SConscript
Normal file
@ -0,0 +1,30 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = []
|
||||
CPPPATH = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
print("\nThe current project does not support iar build\n")
|
||||
Return('group')
|
||||
elif rtconfig.PLATFORM == 'gcc':
|
||||
CPPPATH = [cwd + './src']
|
||||
src = Glob('./src/*.c')
|
||||
elif rtconfig.PLATFORM == 'armclang':
|
||||
if GetOption('target') != 'mdk5':
|
||||
CPPPATH = [cwd + './src']
|
||||
src = Glob('./src/*.c')
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
54
bsp/renesas/ra2l1-cpk/SConstruct
Normal file
54
bsp/renesas/ra2l1-cpk/SConstruct
Normal file
@ -0,0 +1,54 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
303
bsp/renesas/ra2l1-cpk/board/Kconfig
Normal file
303
bsp/renesas/ra2l1-cpk/board/Kconfig
Normal file
@ -0,0 +1,303 @@
|
||||
menu "Hardware Drivers Config"
|
||||
config CPK_R7FA2L1AB
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_R7FA2L1AB
|
||||
bool
|
||||
select SOC_SERIES_R7FA2L1
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
source "../libraries/HAL_Drivers/Kconfig"
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
select RT_USING_SERIAL_V2
|
||||
if BSP_USING_UART
|
||||
|
||||
menuconfig BSP_USING_UART0
|
||||
bool "Enable UART0"
|
||||
default n
|
||||
if BSP_USING_UART0
|
||||
config BSP_UART0_RX_USING_DMA
|
||||
bool "Enable UART0 RX DMA"
|
||||
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART0_TX_USING_DMA
|
||||
bool "Enable UART0 TX DMA"
|
||||
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART0_RX_BUFSIZE
|
||||
int "Set UART0 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART0_TX_BUFSIZE
|
||||
int "Set UART0 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default n
|
||||
if BSP_USING_UART1
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART1_TX_USING_DMA
|
||||
bool "Enable UART1 TX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART1_RX_BUFSIZE
|
||||
int "Set UART1 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART1_TX_BUFSIZE
|
||||
int "Set UART1 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
if BSP_USING_UART2
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART2_TX_USING_DMA
|
||||
bool "Enable UART2 TX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART2_RX_BUFSIZE
|
||||
int "Set UART2 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART2_TX_BUFSIZE
|
||||
int "Set UART2 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART3
|
||||
bool "Enable UART3"
|
||||
default n
|
||||
if BSP_USING_UART3
|
||||
config BSP_UART3_RX_USING_DMA
|
||||
bool "Enable UART3 RX DMA"
|
||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART3_TX_USING_DMA
|
||||
bool "Enable UART3 TX DMA"
|
||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART3_RX_BUFSIZE
|
||||
int "Set UART3 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART3_TX_BUFSIZE
|
||||
int "Set UART3 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART9
|
||||
bool "Enable UART9"
|
||||
default n
|
||||
if BSP_USING_UART9
|
||||
config BSP_UART9_RX_USING_DMA
|
||||
bool "Enable UART9 RX DMA"
|
||||
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART9_TX_USING_DMA
|
||||
bool "Enable UART9 TX DMA"
|
||||
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART9_RX_BUFSIZE
|
||||
int "Set UART9 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART9_TX_BUFSIZE
|
||||
int "Set UART9 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Enable I2C BUS"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
if BSP_USING_I2C
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default y
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
hex "i2c1 scl pin number"
|
||||
range 0x0000 0x0B0F
|
||||
default 0x0512
|
||||
config BSP_I2C1_SDA_PIN
|
||||
hex "I2C1 sda pin number"
|
||||
range 0x0000 0x0B0F
|
||||
default 0x0511
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI BUS"
|
||||
default n
|
||||
select RT_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_SPI_USING_DTC_DMA
|
||||
bool "Enable SPI DTC transfers data without using the CPU."
|
||||
default n
|
||||
|
||||
config BSP_USING_SPI0
|
||||
bool "Enable SPI0 BUS"
|
||||
default n
|
||||
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
select RT_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_DAC
|
||||
bool "Enable DAC"
|
||||
default n
|
||||
select RT_USING_DAC
|
||||
if BSP_USING_DAC
|
||||
config BSP_USING_DAC0
|
||||
bool "Enable DAC0"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_PWM
|
||||
bool "Enable PWM"
|
||||
default n
|
||||
select RT_USING_PWM
|
||||
if BSP_USING_PWM
|
||||
config BSP_USING_PWM0
|
||||
bool "Enable GPT0 (32-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM1
|
||||
bool "Enable GPT1 (32-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM2
|
||||
bool "Enable GPT2 (32-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM3
|
||||
bool "Enable GPT3 (32-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM4
|
||||
bool "Enable GPT4 (16-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM5
|
||||
bool "Enable GPT5 (16-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM6
|
||||
bool "Enable GPT6 (16-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM7
|
||||
bool "Enable GPT7 (16-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM8
|
||||
bool "Enable GPT8 (16-Bits) output PWM"
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM9
|
||||
bool "Enable GPT9 (16-Bits) output PWM"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Enable CAN"
|
||||
default n
|
||||
select RT_USING_CAN
|
||||
if BSP_USING_CAN
|
||||
config BSP_USING_CAN0
|
||||
bool "Enable CAN0"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_LPM
|
||||
bool "Enable LPM"
|
||||
select RT_USING_PM
|
||||
default n
|
||||
if BSP_USING_LPM
|
||||
config BSP_LPM_SLEEP
|
||||
bool "Enable LPM sleep mode"
|
||||
default n
|
||||
|
||||
config BSP_LPM_SNOOZE
|
||||
bool "Enable LPM snooze mode"
|
||||
default n
|
||||
|
||||
config BSP_LPM_STANDBY
|
||||
bool "Enable LPM standby mode"
|
||||
default n
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
endmenu
|
||||
19
bsp/renesas/ra2l1-cpk/board/SConscript
Normal file
19
bsp/renesas/ra2l1-cpk/board/SConscript
Normal file
@ -0,0 +1,19 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
list = os.listdir(cwd)
|
||||
CPPPATH = [cwd]
|
||||
src = []
|
||||
|
||||
if GetDepend(['BSP_USING_LPM']):
|
||||
src += ['drv_pm.c']
|
||||
|
||||
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
38
bsp/renesas/ra2l1-cpk/board/board.h
Normal file
38
bsp/renesas/ra2l1-cpk/board/board.h
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-10 Sherman first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RA_SRAM_SIZE 32
|
||||
#define RA_SRAM_END (0x20000000 + RA_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RAM_END$$ZI$$Base;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
|
||||
#elif __ICCARM__
|
||||
#pragma section="CSTACK"
|
||||
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||
#else
|
||||
extern int __RAM_segment_used_end__;
|
||||
#define HEAP_BEGIN (&__RAM_segment_used_end__)
|
||||
#endif
|
||||
|
||||
#define HEAP_END RA_SRAM_END
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
761
bsp/renesas/ra2l1-cpk/board/drv_pm.c
Normal file
761
bsp/renesas/ra2l1-cpk/board/drv_pm.c
Normal file
@ -0,0 +1,761 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-03-22 Sherman first version
|
||||
*/
|
||||
|
||||
// #define DRV_DEBUG
|
||||
#define DBG_TAG "drv.pm"
|
||||
#ifdef DRV_DEBUG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#else
|
||||
#define DBG_LVL DBG_INFO
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
#include <rtdbg.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
#include <drivers/pm.h>
|
||||
|
||||
#define RESET_VALUE (0x00)
|
||||
#define CLOCK_START (0U)
|
||||
#define CLOCK_STOP (1U)
|
||||
|
||||
/* Control block configuration in LPM mode */
|
||||
#ifdef BSP_LPM_SLEEP
|
||||
#define LPM_SLEEP_CTRL (lpm_instance_ctrl_t *)&g_lpm_sleep_ctrl
|
||||
#define LPM_SLEEP_CFG (lpm_cfg_t *)&g_lpm_sleep_cfg
|
||||
#else
|
||||
#define LPM_SLEEP_CTRL RT_NULL
|
||||
#define LPM_SLEEP_CFG RT_NULL
|
||||
#endif
|
||||
|
||||
#ifdef BSP_LPM_STANDBY
|
||||
#define LPM_SW_STANDBY_CTRL (lpm_instance_ctrl_t *)&g_lpm_sw_standby_ctrl
|
||||
#define LPM_SW_STANDBY_CFG (lpm_cfg_t *)&g_lpm_sw_standby_cfg
|
||||
#else
|
||||
#define LPM_SW_STANDBY_CTRL RT_NULL
|
||||
#define LPM_SW_STANDBY_CFG RT_NULL
|
||||
#endif
|
||||
|
||||
#ifdef BSP_LPM_SNOOZE
|
||||
#define LPM_SW_SNOOZE_CTRL (lpm_instance_ctrl_t *)&g_lpm_sw_standby_with_snooze_ctrl
|
||||
#define LPM_SW_SNOOZE_CFG (lpm_cfg_t *)&g_lpm_sw_standby_with_snooze_cfg
|
||||
#else
|
||||
#define LPM_SW_SNOOZE_CFG RT_NULL
|
||||
#define LPM_SW_SNOOZE_CTRL RT_NULL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* These are LPM Mode instances for Sleep, Software Standby, Snooze and Deep
|
||||
* Software Standby Modes.These instances are created by the FSP. We need these
|
||||
* at the Application level to take the MCU to different LPM modes with configured
|
||||
* trigger/cancel sources
|
||||
*/
|
||||
lpm_instance_ctrl_t *g_lpm_ctrl_instance_ctrls[] =
|
||||
{
|
||||
LPM_SLEEP_CTRL,
|
||||
LPM_SW_STANDBY_CTRL,
|
||||
LPM_SW_SNOOZE_CTRL,
|
||||
};
|
||||
|
||||
lpm_cfg_t *g_lpm_ctrl_instance_cfgs[] =
|
||||
{
|
||||
LPM_SLEEP_CFG,
|
||||
LPM_SW_STANDBY_CFG,
|
||||
LPM_SW_SNOOZE_CFG,
|
||||
};
|
||||
|
||||
/**
|
||||
* Low Power Mode Definitions for LPM app
|
||||
* Since there are no Normal mode definition in LPM driver, use this enum to keep LPM app state including:
|
||||
* Sleep, SW Standby, SW Standby with Snooze enabled, Deep SW Standby, Normal.
|
||||
* Power consumption: NORMAL_STATE > SLEEP_STATE > SW_STANDBY_SNOOZE_STATE > SW_STANDBY_STATE > DEEP_SW_STANDBY_STATE
|
||||
*/
|
||||
enum
|
||||
{
|
||||
SLEEP_STATE = 0, /* Sleep mode */
|
||||
SW_STANDBY_STATE, /* SW Standby mode */
|
||||
SW_STANDBY_SNOOZE_STATE, /* SW Standby mode with Snooze enabled */
|
||||
DEEP_SW_STANDBY_STATE, /* Deep SW Standby mode */
|
||||
NORMAL_STATE /* Normal mode */
|
||||
};
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
static char *lpmstate_to_string(rt_uint8_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case SLEEP_STATE:
|
||||
return "SLEEP";
|
||||
case SW_STANDBY_STATE:
|
||||
return "SW STANDBY";
|
||||
case SW_STANDBY_SNOOZE_STATE:
|
||||
return "SW STANDBY SNOOZE";
|
||||
case DEEP_SW_STANDBY_STATE:
|
||||
return "DEEP SW STANDBY";
|
||||
case NORMAL_STATE:
|
||||
return "NORMAL";
|
||||
default:
|
||||
return "UNKNOWN";
|
||||
}
|
||||
return "UNKNOWN";
|
||||
}
|
||||
|
||||
static char *clk_to_string(cgc_clock_t cstate)
|
||||
{
|
||||
switch (cstate)
|
||||
{
|
||||
case CGC_CLOCK_HOCO:
|
||||
return "HOCO CLOCK";
|
||||
case CGC_CLOCK_MOCO:
|
||||
return "MOCO CLOCK";
|
||||
case CGC_CLOCK_LOCO:
|
||||
return "LOCO CLOCK";
|
||||
case CGC_CLOCK_MAIN_OSC:
|
||||
return "MAIN OSC CLOCK";
|
||||
case CGC_CLOCK_SUBCLOCK:
|
||||
return "SUB OSC CLOCK";
|
||||
case CGC_CLOCK_PLL:
|
||||
return "PLL OSC CLOCK";
|
||||
default:
|
||||
return "UNKNOWN";
|
||||
}
|
||||
return "UNKNOWN";
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief This function enables and puts the MCU in sleep mode.
|
||||
* @param[IN] Requested LPM Mode and the pointer to it's instance
|
||||
* @retval FSP_SUCCESS: Upon successful entering sleep mode
|
||||
* @retval Any Other Error code apart from FSP_SUCCESS
|
||||
*/
|
||||
static fsp_err_t lpm_mode_enter(uint8_t lpm_mode, lpm_instance_ctrl_t *const p_current_ctrl)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
|
||||
switch (lpm_mode)
|
||||
{
|
||||
|
||||
case SW_STANDBY_STATE:
|
||||
/* Enter SW Standby mode */
|
||||
err = R_LPM_LowPowerModeEnter(p_current_ctrl);
|
||||
break;
|
||||
|
||||
case SLEEP_STATE:
|
||||
/* Enter Sleep mode */
|
||||
err = R_LPM_LowPowerModeEnter(p_current_ctrl);
|
||||
break;
|
||||
|
||||
case SW_STANDBY_SNOOZE_STATE:
|
||||
/* Enter SW Standby with Snooze enabled mode */
|
||||
err = R_LPM_LowPowerModeEnter(p_current_ctrl);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* return error */
|
||||
err = FSP_ERR_INVALID_MODE;
|
||||
break;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the LPM mode based on the incoming state
|
||||
* @param[IN] state: This is requested LPM state
|
||||
* @retval None.
|
||||
*/
|
||||
static void entry_lpm(uint8_t state)
|
||||
{
|
||||
if (RT_NULL == g_lpm_ctrl_instance_ctrls[state])
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
/* Disable IO port if it's not in Deep SW Standby mode */
|
||||
if (DEEP_SW_STANDBY_STATE != state)
|
||||
{
|
||||
/* Disable IO port before going to LPM mode*/
|
||||
err = R_IOPORT_PinsCfg(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
|
||||
/* Open LPM instance*/
|
||||
err = R_LPM_Open(g_lpm_ctrl_instance_ctrls[state], g_lpm_ctrl_instance_cfgs[state]);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
/* Enter LPM mode. Function will return after waking from low power mode. */
|
||||
err = lpm_mode_enter(state, g_lpm_ctrl_instance_ctrls[state]);
|
||||
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS == err)
|
||||
{
|
||||
/* Close LPM instance.*/
|
||||
err = R_LPM_Close(g_lpm_ctrl_instance_ctrls[state]);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
/* Put IO port configuration back to user's selections */
|
||||
err = R_IOPORT_PinsCfg(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* @brief This function does necessary setups before entering SW Standby with Snooze enabled.
|
||||
* @retval FSP_SUCCESS Upon successful checking and starting LOCO clock, AGT1 timer
|
||||
* @retval Any Other Error code apart from FSP_SUCCESS
|
||||
**********************************************************************************************************************/
|
||||
static fsp_err_t standby_snooze_set(void)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
agt_extended_cfg_t const *p_agt0_extend = agt1_timer_cascade_trigger_cfg.p_extend;
|
||||
|
||||
/* Turn off part of the clock before entering Snooze */
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MAIN_OSC);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_SUBCLOCK);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check and start LOCO clock. LOCO is needed since it is selected as AGT1 timer counter source
|
||||
* CGC module is opened in user_clocks_set function
|
||||
*/
|
||||
if (AGT_CLOCK_LOCO == p_agt0_extend->count_source)
|
||||
{
|
||||
if (CLOCK_STOP == R_SYSTEM->LOCOCR_b.LCSTP)
|
||||
{
|
||||
/* Start LOCO clock */
|
||||
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_LOCO, NULL);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
return err;
|
||||
}
|
||||
/* LOCO does not have Oscillation Stabilization Flag, wait for its stabilization by adding delay */
|
||||
R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void ra_sleep(struct rt_pm *pm, rt_uint8_t mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case PM_SLEEP_MODE_NONE:
|
||||
break;
|
||||
|
||||
case PM_SLEEP_MODE_IDLE:
|
||||
#ifdef BSP_LPM_SLEEP
|
||||
/* enrty sleep mode */
|
||||
entry_lpm(SLEEP_STATE);
|
||||
#else
|
||||
LOG_W("Disable mode:%s", lpmstate_to_string(SLEEP_STATE));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PM_SLEEP_MODE_LIGHT:
|
||||
LOG_W("PM_SLEEP_MODE_LIGHT:This mode is not supported!");
|
||||
break;
|
||||
|
||||
case PM_SLEEP_MODE_DEEP:
|
||||
#ifdef BSP_LPM_SNOOZE
|
||||
/* enrty standby snooze mode */
|
||||
standby_snooze_set();
|
||||
entry_lpm(SW_STANDBY_SNOOZE_STATE);
|
||||
#else
|
||||
LOG_W("Disable mode:%s", lpmstate_to_string(SW_STANDBY_SNOOZE_STATE));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PM_SLEEP_MODE_STANDBY:
|
||||
#ifdef BSP_LPM_STANDBY
|
||||
/* enrty standby mode */
|
||||
entry_lpm(SW_STANDBY_STATE);
|
||||
#else
|
||||
LOG_W("Disable mode:%s", lpmstate_to_string(SW_STANDBY_STATE));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PM_SLEEP_MODE_SHUTDOWN:
|
||||
LOG_W("PM_SLEEP_MODE_SHUTDOWN:This mode is not supported!");
|
||||
break;
|
||||
|
||||
default:
|
||||
RT_ASSERT(0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function changes the System Clock. Currently MOSC and SOSC are not connected on RA2L1 board.
|
||||
* So these needs to be turned OFF
|
||||
*/
|
||||
static void preffered_ra_clock_setting(void)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
/* Stop the Main Oscillator as it is not available on RA2L1-EK Board */
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MAIN_OSC);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
/* Stop the Sub Oscillator as it is not available on RA2L1-EK Board */
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_SUBCLOCK);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef R_CGC_H
|
||||
void uart_update(rt_uint8_t clockmode)
|
||||
{
|
||||
baud_setting_t baud_setting;
|
||||
uint32_t baud_rate = BAUD_RATE_115200;
|
||||
bool enable_bitrate_modulation = false;
|
||||
uint32_t error_rate_x_1000 = 5000;
|
||||
|
||||
switch (clockmode)
|
||||
{
|
||||
case CGC_CLOCK_HOCO:
|
||||
baud_rate = BAUD_RATE_115200;
|
||||
break;
|
||||
case CGC_CLOCK_MOCO:
|
||||
baud_rate = BAUD_RATE_38400;
|
||||
break;
|
||||
case CGC_CLOCK_LOCO:
|
||||
case CGC_CLOCK_SUBCLOCK:
|
||||
baud_rate = 600;
|
||||
break;
|
||||
default:
|
||||
baud_rate = BAUD_RATE_115200;
|
||||
break;
|
||||
}
|
||||
|
||||
fsp_err_t err = R_SCI_UART_BaudCalculate(baud_rate,
|
||||
enable_bitrate_modulation,
|
||||
error_rate_x_1000,
|
||||
&baud_setting);
|
||||
err = R_SCI_UART_BaudSet(&g_uart9_ctrl, (void *) &baud_setting);
|
||||
assert(FSP_SUCCESS == err);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to changes the System Clock.
|
||||
*/
|
||||
static void change_system_clock(rt_uint8_t clockmode)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
cgc_divider_cfg_t sys_divider_cf = { RESET_VALUE };
|
||||
cgc_clock_t sys_clock_source = { RESET_VALUE };
|
||||
cgc_clocks_cfg_t sys_clk_cfg = { RESET_VALUE };
|
||||
cgc_pll_cfg_t new_clk = { RESET_VALUE };
|
||||
|
||||
#if defined (CPK_R7FA2L1AB)
|
||||
preffered_ra_clock_setting();
|
||||
sys_clk_cfg.mainosc_state = CGC_CLOCK_CHANGE_STOP;
|
||||
#endif
|
||||
|
||||
err = R_CGC_SystemClockGet(&g_cgc0_ctrl, &sys_clock_source, &sys_divider_cf);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
LOG_D("MCU Running with Clock Source = %s.", clk_to_string(sys_clock_source));
|
||||
switch (clockmode)
|
||||
{
|
||||
case CGC_CLOCK_HOCO:
|
||||
case CGC_CLOCK_MOCO:
|
||||
{
|
||||
sys_clock_source = clockmode;
|
||||
sys_clk_cfg.hoco_state = CGC_CLOCK_CHANGE_START;
|
||||
|
||||
sys_clk_cfg.pll_cfg.source_clock = sys_clock_source;
|
||||
sys_clk_cfg.pll_cfg.divider = CGC_PLL_DIV_1;
|
||||
sys_clk_cfg.pll_cfg.multiplier = 0;
|
||||
|
||||
sys_clk_cfg.pll2_cfg.source_clock = sys_clock_source;
|
||||
sys_clk_cfg.pll2_cfg.divider = CGC_PLL_DIV_1;
|
||||
sys_clk_cfg.pll2_cfg.multiplier = 0;
|
||||
|
||||
sys_clk_cfg.divider_cfg.pclka_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.pclkb_div = CGC_SYS_CLOCK_DIV_2;
|
||||
sys_clk_cfg.divider_cfg.pclkc_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.pclkd_div = CGC_SYS_CLOCK_DIV_1;
|
||||
|
||||
sys_clk_cfg.divider_cfg.iclk_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.bclk_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.fclk_div = CGC_SYS_CLOCK_DIV_1;
|
||||
break;
|
||||
}
|
||||
|
||||
case CGC_CLOCK_LOCO:
|
||||
case CGC_CLOCK_SUBCLOCK:
|
||||
{
|
||||
sys_clock_source = clockmode;
|
||||
sys_clk_cfg.hoco_state = CGC_CLOCK_CHANGE_START;
|
||||
|
||||
sys_clk_cfg.pll_cfg.source_clock = sys_clock_source;
|
||||
sys_clk_cfg.pll_cfg.divider = CGC_PLL_DIV_1;
|
||||
sys_clk_cfg.pll_cfg.multiplier = 0;
|
||||
|
||||
sys_clk_cfg.pll2_cfg.source_clock = sys_clock_source;
|
||||
sys_clk_cfg.pll2_cfg.divider = CGC_PLL_DIV_1;
|
||||
sys_clk_cfg.pll2_cfg.multiplier = 0;
|
||||
|
||||
sys_clk_cfg.divider_cfg.pclka_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.pclkb_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.pclkc_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.pclkd_div = CGC_SYS_CLOCK_DIV_1;
|
||||
|
||||
sys_clk_cfg.divider_cfg.iclk_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.bclk_div = CGC_SYS_CLOCK_DIV_1;
|
||||
sys_clk_cfg.divider_cfg.fclk_div = CGC_SYS_CLOCK_DIV_1;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
sys_clock_source = CGC_CLOCK_PLL;
|
||||
sys_clk_cfg.pll_state = CGC_CLOCK_CHANGE_NONE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
sys_clk_cfg.system_clock = sys_clock_source;
|
||||
|
||||
err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &sys_clk_cfg);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_SystemClockSet(&g_cgc0_ctrl, sys_clock_source, &sys_clk_cfg.divider_cfg);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
LOG_D("Requested Clock Source for MCU = %s.", clk_to_string(sys_clock_source));
|
||||
|
||||
if (CGC_CLOCK_SUBCLOCK == sys_clock_source)
|
||||
{
|
||||
new_clk.source_clock = CGC_CLOCK_SUBCLOCK;
|
||||
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_SUBCLOCK, &new_clk);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_LOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
else if (CGC_CLOCK_LOCO == sys_clock_source)
|
||||
{
|
||||
new_clk.source_clock = CGC_CLOCK_LOCO;
|
||||
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_LOCO, &new_clk);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
else if (CGC_CLOCK_MOCO == sys_clock_source)
|
||||
{
|
||||
new_clk.source_clock = CGC_CLOCK_MOCO;
|
||||
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_MOCO, &new_clk);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
else if (CGC_CLOCK_HOCO == sys_clock_source)
|
||||
{
|
||||
new_clk.source_clock = CGC_CLOCK_HOCO;
|
||||
|
||||
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_HOCO, &new_clk);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
|
||||
err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
}
|
||||
}
|
||||
|
||||
/* Clock Oscillation Stabilization, wait for its stabilization by adding delay */
|
||||
R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
|
||||
|
||||
extern void rt_hw_systick_init(void);
|
||||
rt_hw_systick_init();
|
||||
uart_update(clockmode);
|
||||
}
|
||||
|
||||
static void ra_run(struct rt_pm *pm, rt_uint8_t mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case PM_RUN_MODE_HIGH_SPEED:
|
||||
case PM_RUN_MODE_NORMAL_SPEED:
|
||||
change_system_clock(CGC_CLOCK_HOCO);
|
||||
break;
|
||||
case PM_RUN_MODE_MEDIUM_SPEED:
|
||||
change_system_clock(CGC_CLOCK_MOCO);
|
||||
break;
|
||||
case PM_RUN_MODE_LOW_SPEED:
|
||||
change_system_clock(CGC_CLOCK_LOCO);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Agt1 serves as a low-power timer */
|
||||
/**
|
||||
* @brief This function opens AGT modules
|
||||
*/
|
||||
static fsp_err_t agt_timer_init(void)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
/* Open AGT1 Timer in Periodic mode */
|
||||
err = R_AGT_Open(&agt1_timer_cascade_trigger_ctrl, &agt1_timer_cascade_trigger_cfg);
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function starts AGT modules
|
||||
*/
|
||||
#define AGT_SECOND_COUNT 512 /* clock_frequency / clock_divider */
|
||||
#define PERIOD_MAX 0xFFFF
|
||||
static fsp_err_t agt_timer_start(rt_uint32_t timeout)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
rt_uint32_t tick = timeout * AGT_SECOND_COUNT / RT_TICK_PER_SECOND;
|
||||
rt_uint32_t period1 = tick > PERIOD_MAX ? PERIOD_MAX : tick;
|
||||
if (period1)
|
||||
{
|
||||
/* PeriodSet AGT1 timer */
|
||||
err = R_AGT_PeriodSet(&agt1_timer_cascade_trigger_ctrl, period1);
|
||||
if (FSP_SUCCESS == err)
|
||||
{
|
||||
/* Start AGT1 timer */
|
||||
err = R_AGT_Start(&agt1_timer_cascade_trigger_ctrl);
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function stops AGT modules
|
||||
*/
|
||||
static fsp_err_t agt_timer_stop(void)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
timer_status_t agt_status = {0};
|
||||
|
||||
err = R_AGT_StatusGet(&agt1_timer_cascade_trigger_ctrl, &agt_status);
|
||||
if (FSP_SUCCESS == err)
|
||||
{
|
||||
if (agt_status.state)
|
||||
{
|
||||
/* Stop Timer */
|
||||
err = R_AGT_Stop(&agt1_timer_cascade_trigger_ctrl);
|
||||
if (FSP_SUCCESS == err)
|
||||
{
|
||||
/* Reset counter */
|
||||
err = R_AGT_PeriodSet(&agt1_timer_cascade_trigger_ctrl, 0);
|
||||
err = R_AGT_Reset(&agt1_timer_cascade_trigger_ctrl);
|
||||
}
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
static rt_uint32_t agt_timer_get(void)
|
||||
{
|
||||
rt_uint32_t tick = 0;
|
||||
rt_uint32_t counter = 0;
|
||||
|
||||
timer_status_t agt1_status = {0};
|
||||
timer_info_t agt1_info = {RESET_VALUE};
|
||||
/* Stop AGT timers if they are counting */
|
||||
R_AGT_InfoGet(&agt1_timer_cascade_trigger_ctrl, &agt1_info);
|
||||
R_AGT_StatusGet(&agt1_timer_cascade_trigger_ctrl, &agt1_status);
|
||||
counter = agt1_status.counter < agt1_info.period_counts ?
|
||||
agt1_info.period_counts : (agt1_info.period_counts - agt1_status.counter);
|
||||
|
||||
tick = counter * RT_TICK_PER_SECOND / AGT_SECOND_COUNT;
|
||||
LOG_D("get tick %u counter %u", tick, counter);
|
||||
return tick;
|
||||
}
|
||||
|
||||
static void ra_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
|
||||
{
|
||||
agt_timer_start(timeout);
|
||||
}
|
||||
|
||||
static void ra_timer_stop(struct rt_pm *pm)
|
||||
{
|
||||
agt_timer_stop();
|
||||
}
|
||||
|
||||
static rt_tick_t ra_timer_get_tick(struct rt_pm *pm)
|
||||
{
|
||||
return agt_timer_get();
|
||||
}
|
||||
|
||||
static const struct rt_pm_ops _ops =
|
||||
{
|
||||
ra_sleep,
|
||||
#ifdef R_CGC_H
|
||||
ra_run,
|
||||
#else
|
||||
RT_NULL,
|
||||
#endif
|
||||
ra_timer_start,
|
||||
ra_timer_stop,
|
||||
ra_timer_get_tick
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief This function initializes clock module by opening the CGC Module and Changes the System Clock to MOSC
|
||||
* @param[IN] None
|
||||
* @retval FSP_SUCCESS: Upon successful initialization.
|
||||
* @retval Any Other Error code apart from FSP_SUCCESS
|
||||
*/
|
||||
static fsp_err_t init_cgc(void)
|
||||
{
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
|
||||
cgc_clock_t lsys_clock_source = {RESET_VALUE};
|
||||
cgc_divider_cfg_t sys_divider_cf = {RESET_VALUE};
|
||||
|
||||
/* Open CGC module */
|
||||
err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS == err)
|
||||
{
|
||||
/* Get system clock source */
|
||||
err = R_CGC_SystemClockGet(&g_cgc0_ctrl, &lsys_clock_source, &sys_divider_cf);
|
||||
/* Handle error */
|
||||
if (FSP_SUCCESS == err)
|
||||
{
|
||||
LOG_D("MCU Running with Clock Source = %s.", clk_to_string(lsys_clock_source));
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function initialize the power manager
|
||||
*/
|
||||
int drv_pm_hw_init(void)
|
||||
{
|
||||
rt_uint8_t timer_mask = 0;
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
/* Initialize the CGC(Clock Generation Circuit) module.
|
||||
* The CGC module API is used to dynamically change the required clock source */
|
||||
err = init_cgc();
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_D("CGC Initialization Failed \r\n");
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
return -1;
|
||||
}
|
||||
|
||||
err = agt_timer_init();
|
||||
if (FSP_SUCCESS != err)
|
||||
{
|
||||
LOG_D("AGT Initialization Failed \r\n");
|
||||
LOG_E("Returned Error Code: 0x%x", err);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* initialize timer mask */
|
||||
timer_mask = (1UL << PM_SLEEP_MODE_DEEP) | (1UL << PM_SLEEP_MODE_STANDBY);
|
||||
|
||||
/* initialize system pm module */
|
||||
rt_system_pm_init(&_ops, timer_mask, RT_NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(drv_pm_hw_init);
|
||||
24
bsp/renesas/ra2l1-cpk/board/ports/SConscript
Normal file
24
bsp/renesas/ra2l1-cpk/board/ports/SConscript
Normal file
@ -0,0 +1,24 @@
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = []
|
||||
|
||||
if GetDepend(['BSP_USING_RW007']):
|
||||
src += Glob('drv_rw007.c')
|
||||
|
||||
CPPPATH = [cwd]
|
||||
LOCAL_CCFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
LOCAL_CCFLAGS += ' -std=c99'
|
||||
elif rtconfig.PLATFORM == 'armcc':
|
||||
LOCAL_CCFLAGS += ' --c99'
|
||||
elif rtconfig.PLATFORM == 'armclang':
|
||||
LOCAL_CCFLAGS += ' -std=c99'
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS)
|
||||
|
||||
Return('group')
|
||||
54
bsp/renesas/ra2l1-cpk/board/ports/gpio_cfg.h
Normal file
54
bsp/renesas/ra2l1-cpk/board/ports/gpio_cfg.h
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-01-19 Sherman first version
|
||||
*/
|
||||
|
||||
/* Number of IRQ channels on the device */
|
||||
#define RA_IRQ_MAX 8
|
||||
|
||||
/* PIN to IRQx table */
|
||||
#define PIN2IRQX_TABLE(pin) \
|
||||
{ \
|
||||
switch (pin) \
|
||||
{ \
|
||||
case BSP_IO_PORT_04_PIN_00: \
|
||||
case BSP_IO_PORT_02_PIN_06: \
|
||||
case BSP_IO_PORT_01_PIN_05: \
|
||||
return 0; \
|
||||
case BSP_IO_PORT_02_PIN_05: \
|
||||
case BSP_IO_PORT_01_PIN_01: \
|
||||
case BSP_IO_PORT_01_PIN_04: \
|
||||
return 1; \
|
||||
case BSP_IO_PORT_01_PIN_00: \
|
||||
case BSP_IO_PORT_00_PIN_02: \
|
||||
case BSP_IO_PORT_02_PIN_13: \
|
||||
return 2; \
|
||||
case BSP_IO_PORT_00_PIN_04: \
|
||||
case BSP_IO_PORT_01_PIN_10: \
|
||||
case BSP_IO_PORT_02_PIN_12: \
|
||||
return 3; \
|
||||
case BSP_IO_PORT_04_PIN_02: \
|
||||
case BSP_IO_PORT_01_PIN_11: \
|
||||
case BSP_IO_PORT_04_PIN_11: \
|
||||
return 4; \
|
||||
case BSP_IO_PORT_04_PIN_01: \
|
||||
case BSP_IO_PORT_03_PIN_02: \
|
||||
case BSP_IO_PORT_04_PIN_10: \
|
||||
return 5; \
|
||||
case BSP_IO_PORT_03_PIN_01: \
|
||||
case BSP_IO_PORT_00_PIN_00: \
|
||||
case BSP_IO_PORT_04_PIN_09: \
|
||||
return 6; \
|
||||
case BSP_IO_PORT_00_PIN_15: \
|
||||
case BSP_IO_PORT_00_PIN_01: \
|
||||
case BSP_IO_PORT_04_PIN_08: \
|
||||
return 7; \
|
||||
default : \
|
||||
return -1; \
|
||||
} \
|
||||
}
|
||||
149
bsp/renesas/ra2l1-cpk/buildinfo.gpdsc
Normal file
149
bsp/renesas/ra2l1-cpk/buildinfo.gpdsc
Normal file
@ -0,0 +1,149 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<vendor>Renesas</vendor>
|
||||
<name>Project Content</name>
|
||||
<description>Project content managed by the Renesas Smart Configurator</description>
|
||||
<url/>
|
||||
<releases>
|
||||
<release version="1.0.0"/>
|
||||
</releases>
|
||||
<generators>
|
||||
<generator id="Renesas RA Smart Configurator">
|
||||
<project_files>
|
||||
<file category="include" name="src/"/>
|
||||
<file category="source" name="src/hal_entry.c"/>
|
||||
</project_files>
|
||||
</generator>
|
||||
</generators>
|
||||
<components generator="Renesas RA Smart Configurator">
|
||||
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
|
||||
<files>
|
||||
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
|
||||
<file category="include" name="ra/fsp/inc/"/>
|
||||
<file category="include" name="ra/fsp/inc/api/"/>
|
||||
<file category="include" name="ra/fsp/inc/instances/"/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
|
||||
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
|
||||
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
|
||||
<file category="header" name="ra/board/ra2l1_cpk/board.h" path=""/>
|
||||
<file category="source" name="ra/board/ra2l1_cpk/board_init.c"/>
|
||||
<file category="header" name="ra/board/ra2l1_cpk/board_init.h" path=""/>
|
||||
<file category="source" name="ra/board/ra2l1_cpk/board_leds.c"/>
|
||||
<file category="header" name="ra/board/ra2l1_cpk/board_leds.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
|
||||
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
|
||||
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
|
||||
<file category="other" name="ra/SConscript"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cclass="Flex Software" Cgroup="Build Configuration">
|
||||
<files>
|
||||
<file category="include" name="ra_cfg/fsp_cfg/"/>
|
||||
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
|
||||
<file category="other" name="ra_cfg/SConscript"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cclass="Flex Software" Cgroup="Generated Data">
|
||||
<files>
|
||||
<file category="include" name="ra_gen/"/>
|
||||
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
|
||||
<file category="source" name="ra_gen/common_data.c"/>
|
||||
<file category="header" name="ra_gen/common_data.h" path=""/>
|
||||
<file category="source" name="ra_gen/hal_data.c"/>
|
||||
<file category="header" name="ra_gen/hal_data.h" path=""/>
|
||||
<file category="source" name="ra_gen/main.c"/>
|
||||
<file category="source" name="ra_gen/pin_data.c"/>
|
||||
<file category="other" name="ra_gen/SConscript"/>
|
||||
<file category="source" name="ra_gen/vector_data.c"/>
|
||||
<file category="header" name="ra_gen/vector_data.h" path=""/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cclass="Flex Software" Cgroup="Linker Script">
|
||||
<files>
|
||||
<file category="linkerScript" name="script/fsp.scat"/>
|
||||
<file category="other" name="script/ac6/fsp_keep.via"/>
|
||||
</files>
|
||||
</component>
|
||||
</components>
|
||||
</package>
|
||||
403
bsp/renesas/ra2l1-cpk/configuration.xml
Normal file
403
bsp/renesas/ra2l1-cpk/configuration.xml
Normal file
@ -0,0 +1,403 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="7">
|
||||
<generalSettings>
|
||||
<option key="#Board#" value="board.ra2l1cpk"/>
|
||||
<option key="CPU" value="RA2L1"/>
|
||||
<option key="#TargetName#" value="R7FA2L1AB2DFM"/>
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m23"/>
|
||||
<option key="#DeviceCommand#" value="R7FA2L1AB"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA2L1AB2DFM.pincfg"/>
|
||||
<option key="#FSPVersion#" value="3.5.0"/>
|
||||
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2l1_cpk##"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra2l1.R7FA2L1AB2DFM">
|
||||
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||
<property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
|
||||
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
|
||||
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra2l1">
|
||||
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra2l1.fsp">
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS1.internal_clock_supply" value="config.bsp.fsp.OFS1.internal_clock_supply.type_a"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
|
||||
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
|
||||
<property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_start" value="0x000FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_end" value="0x000FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_start" value="0x000FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_end" value="0x000FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_start" value="0x000FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_end" value="0x000FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
|
||||
<property id="config.bsp.fsp.dcdc" value="config.bsp.fsp.dcdc.disabled"/>
|
||||
<property id="config.bsp.fsp.dcdc_range" value="config.bsp.fsp.dcdc_range.2v7_3v6"/>
|
||||
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="3333333"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="8000000"/>
|
||||
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="16000000"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
|
||||
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
|
||||
<property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
|
||||
<property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
|
||||
<property id="config.bsp.common.id1" value=""/>
|
||||
<property id="config.bsp.common.id2" value=""/>
|
||||
<property id="config.bsp.common.id3" value=""/>
|
||||
<property id="config.bsp.common.id4" value=""/>
|
||||
<property id="config.bsp.common.id_fixed" value=""/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x400"/>
|
||||
<property id="config.bsp.common.heap" value="0"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.disabled"/>
|
||||
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
|
||||
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.disabled"/>
|
||||
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
|
||||
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
|
||||
</config>
|
||||
</raBspConfiguration>
|
||||
<raClockConfiguration>
|
||||
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
|
||||
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
|
||||
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
|
||||
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
|
||||
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
|
||||
<node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
|
||||
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
|
||||
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
|
||||
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
|
||||
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
|
||||
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
|
||||
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
|
||||
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
|
||||
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
|
||||
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
|
||||
</raClockConfiguration>
|
||||
<raComponentSelection>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Board Support Package Common Files</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>I/O Port</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.8.0+renesas.0.fsp.3.5.0">
|
||||
<description>Arm CMSIS Version 5 - Core (M)</description>
|
||||
<originalPack>Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2l1" subgroup="device" variant="R7FA2L1AB2DFM" vendor="Renesas" version="3.5.0">
|
||||
<description>Board support package for R7FA2L1AB2DFM</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2l1.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2l1" subgroup="device" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Board support package for RA2L1</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2l1.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2l1" subgroup="fsp" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>Board support package for RA2L1 - FSP Data</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2l1.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra2l1_cpk" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>RA2L1-CPK Board Support Files</description>
|
||||
<originalPack>Renesas.RA_board_ra2l1_cpk.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>SCI UART</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_icu" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>External Interrupt</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioportb" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioportc" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioportd" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioporte" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<module id="module.driver.uart_on_sci_uart.629312687">
|
||||
<property id="module.driver.uart.name" value="g_uart9"/>
|
||||
<property id="module.driver.uart.channel" value="9"/>
|
||||
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
|
||||
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
|
||||
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
|
||||
<property id="module.driver.uart.baud" value="115200"/>
|
||||
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
|
||||
<property id="module.driver.uart.baudrate_max_err" value="5"/>
|
||||
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
|
||||
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
|
||||
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
|
||||
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
|
||||
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
|
||||
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
|
||||
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
|
||||
<property id="module.driver.uart.callback" value="user_uart9_callback"/>
|
||||
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority2"/>
|
||||
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority2"/>
|
||||
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority2"/>
|
||||
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority2"/>
|
||||
</module>
|
||||
<module id="module.driver.external_irq_on_icu.832378872">
|
||||
<property id="module.driver.external_irq.name" value="g_external_irq3"/>
|
||||
<property id="module.driver.external_irq.channel" value="3"/>
|
||||
<property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
|
||||
<property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
|
||||
<property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
|
||||
<property id="module.driver.external_irq.p_callback" value="irq_callback"/>
|
||||
<property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority2"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
<stack module="module.driver.uart_on_sci_uart.629312687"/>
|
||||
<stack module="module.driver.external_irq_on_icu.832378872"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
<config id="config.driver.icu">
|
||||
<property id="config.driver.icu.param_checking_enable" value="config.driver.icu.param_checking_enable.bsp"/>
|
||||
</config>
|
||||
<config id="config.driver.sci_uart">
|
||||
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
|
||||
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
|
||||
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
|
||||
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<symbolicName propertyId="p000.symbolic_name" value="ARDUINO_AN00"/>
|
||||
<symbolicName propertyId="p004.symbolic_name" value="SW1"/>
|
||||
<symbolicName propertyId="p012.symbolic_name" value="CTSU_TS1"/>
|
||||
<symbolicName propertyId="p013.symbolic_name" value="CTSU_TS2"/>
|
||||
<symbolicName propertyId="p015.symbolic_name" value="CTSU_TS3"/>
|
||||
<symbolicName propertyId="p100.symbolic_name" value="PMODA_MISOA_RXD0"/>
|
||||
<symbolicName propertyId="p101.symbolic_name" value="PMODA_MOSIA_TXD0"/>
|
||||
<symbolicName propertyId="p102.symbolic_name" value="PMODA_RSPCKA_SCK0"/>
|
||||
<symbolicName propertyId="p103.symbolic_name" value="PMODA_SSLA0_CTS0"/>
|
||||
<symbolicName propertyId="p104.symbolic_name" value="ARDUINO_GPIO_IRQ01"/>
|
||||
<symbolicName propertyId="p105.symbolic_name" value="PMODA_IO2"/>
|
||||
<symbolicName propertyId="p106.symbolic_name" value="PMODA_IO3"/>
|
||||
<symbolicName propertyId="p107.symbolic_name" value="ARDUINO_GPIO_KRM07"/>
|
||||
<symbolicName propertyId="p108.symbolic_name" value="DEBUG_SWDIO_TMS"/>
|
||||
<symbolicName propertyId="p109.symbolic_name" value="DEBUG_TDO"/>
|
||||
<symbolicName propertyId="p110.symbolic_name" value="DEBUG_TDI"/>
|
||||
<symbolicName propertyId="p111.symbolic_name" value="ARDUINO_GPIO_GTIOC6"/>
|
||||
<symbolicName propertyId="p112.symbolic_name" value="ARDUINO_GPIO_CLK"/>
|
||||
<symbolicName propertyId="p113.symbolic_name" value="ARDUINO_GPIO"/>
|
||||
<symbolicName propertyId="p201.symbolic_name" value="MD"/>
|
||||
<symbolicName propertyId="p205.symbolic_name" value="ARDUINO_TXD"/>
|
||||
<symbolicName propertyId="p207.symbolic_name" value="ARDUINO_RST"/>
|
||||
<symbolicName propertyId="p208.symbolic_name" value="PMODA_IO1"/>
|
||||
<symbolicName propertyId="p212.symbolic_name" value="EXTAL"/>
|
||||
<symbolicName propertyId="p213.symbolic_name" value="XTAL"/>
|
||||
<symbolicName propertyId="p214.symbolic_name" value="XCOUT"/>
|
||||
<symbolicName propertyId="p215.symbolic_name" value="XCIN"/>
|
||||
<symbolicName propertyId="p300.symbolic_name" value="DEBUG_SWDCLK_TCK"/>
|
||||
<symbolicName propertyId="p301.symbolic_name" value="GROVE_SCL"/>
|
||||
<symbolicName propertyId="p302.symbolic_name" value="GROVE_SDA"/>
|
||||
<symbolicName propertyId="p303.symbolic_name" value="PMODB_IO1"/>
|
||||
<symbolicName propertyId="p304.symbolic_name" value="PMODB_IO3"/>
|
||||
<symbolicName propertyId="p400.symbolic_name" value="PMODB_SCK1"/>
|
||||
<symbolicName propertyId="p401.symbolic_name" value="PMODB_MOSI_TXD1"/>
|
||||
<symbolicName propertyId="p402.symbolic_name" value="PMODB_MISO_RXD1"/>
|
||||
<symbolicName propertyId="p403.symbolic_name" value="PMODB_SSL_CTS1"/>
|
||||
<symbolicName propertyId="p407.symbolic_name" value="ARDUINO_SDA"/>
|
||||
<symbolicName propertyId="p408.symbolic_name" value="ARDUINO_SCL"/>
|
||||
<symbolicName propertyId="p409.symbolic_name" value="PMODB_IRQ06"/>
|
||||
<symbolicName propertyId="p410.symbolic_name" value="PMODB_IO2"/>
|
||||
<symbolicName propertyId="p411.symbolic_name" value="PMODA_IRQ04"/>
|
||||
<symbolicName propertyId="p500.symbolic_name" value="ARDUINO_GPIO_GTIOC5"/>
|
||||
<symbolicName propertyId="p501.symbolic_name" value="LED2"/>
|
||||
<symbolicName propertyId="p502.symbolic_name" value="LED1"/>
|
||||
<pincfg active="true" name="RA2L1 CPK" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/>
|
||||
<configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/>
|
||||
<configSetting altId="adc0.an02.p002" configurationId="adc0.an02"/>
|
||||
<configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/>
|
||||
<configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
|
||||
<configSetting altId="ctsu0.cfcts28.p015" configurationId="ctsu0.cfcts28"/>
|
||||
<configSetting altId="ctsu0.cfcts32.p012" configurationId="ctsu0.cfcts32"/>
|
||||
<configSetting altId="ctsu0.cfcts33.p013" configurationId="ctsu0.cfcts33"/>
|
||||
<configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
|
||||
<configSetting altId="ctsu0.tscap.p112" configurationId="ctsu0.tscap"/>
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="iic0.mode.enabled.free" configurationId="iic0.mode"/>
|
||||
<configSetting altId="iic0.pairing.free" configurationId="iic0.pairing"/>
|
||||
<configSetting altId="iic0.scl.p408" configurationId="iic0.scl"/>
|
||||
<configSetting altId="iic0.sda.p407" configurationId="iic0.sda"/>
|
||||
<configSetting altId="irq0.irq01.p104" configurationId="irq0.irq01"/>
|
||||
<configSetting altId="irq0.irq03.p004" configurationId="irq0.irq03"/>
|
||||
<configSetting altId="irq0.irq04.p411" configurationId="irq0.irq04"/>
|
||||
<configSetting altId="irq0.irq06.p409" configurationId="irq0.irq06"/>
|
||||
<configSetting altId="irq0.mode.enabled" configurationId="irq0.mode"/>
|
||||
<configSetting altId="p000.adc0.an00" configurationId="p000"/>
|
||||
<configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
|
||||
<configSetting altId="p001.adc0.an01" configurationId="p001"/>
|
||||
<configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
|
||||
<configSetting altId="p002.adc0.an02" configurationId="p002"/>
|
||||
<configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
|
||||
<configSetting altId="p003.adc0.an03" configurationId="p003"/>
|
||||
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
|
||||
<configSetting altId="p004.irq0.irq03" configurationId="p004"/>
|
||||
<configSetting altId="p004.gpio_irq.gpio_irq_enabled" configurationId="p004.gpio_irq"/>
|
||||
<configSetting altId="p004.gpio_mode.gpio_mode_irq" configurationId="p004.gpio_mode"/>
|
||||
<configSetting altId="p012.ctsu0.cfcts32" configurationId="p012"/>
|
||||
<configSetting altId="p012.gpio_mode.gpio_mode_peripheral" configurationId="p012.gpio_mode"/>
|
||||
<configSetting altId="p013.ctsu0.cfcts33" configurationId="p013"/>
|
||||
<configSetting altId="p013.gpio_mode.gpio_mode_peripheral" configurationId="p013.gpio_mode"/>
|
||||
<configSetting altId="p015.ctsu0.cfcts28" configurationId="p015"/>
|
||||
<configSetting altId="p015.gpio_mode.gpio_mode_peripheral" configurationId="p015.gpio_mode"/>
|
||||
<configSetting altId="p100.sci0.rxd" configurationId="p100"/>
|
||||
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
|
||||
<configSetting altId="p101.sci0.txd" configurationId="p101"/>
|
||||
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
|
||||
<configSetting altId="p102.sci0.sck" configurationId="p102"/>
|
||||
<configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
|
||||
<configSetting altId="p103.sci0.cts" configurationId="p103"/>
|
||||
<configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
|
||||
<configSetting altId="p104.irq0.irq01" configurationId="p104"/>
|
||||
<configSetting altId="p104.gpio_irq.gpio_irq_enabled" configurationId="p104.gpio_irq"/>
|
||||
<configSetting altId="p104.gpio_mode.gpio_mode_irq" configurationId="p104.gpio_mode"/>
|
||||
<configSetting altId="p105.output.low" configurationId="p105"/>
|
||||
<configSetting altId="p105.gpio_mode.gpio_mode_out.low" configurationId="p105.gpio_mode"/>
|
||||
<configSetting altId="p106.output.low" configurationId="p106"/>
|
||||
<configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
|
||||
<configSetting altId="p107.output.low" configurationId="p107"/>
|
||||
<configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p109.sci9.txd" configurationId="p109"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p110.sci9.rxd" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p111.output.low" configurationId="p111"/>
|
||||
<configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/>
|
||||
<configSetting altId="p112.ctsu0.tscap" configurationId="p112"/>
|
||||
<configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/>
|
||||
<configSetting altId="p113.output.low" configurationId="p113"/>
|
||||
<configSetting altId="p113.gpio_mode.gpio_mode_out.low" configurationId="p113.gpio_mode"/>
|
||||
<configSetting altId="p207.output.low" configurationId="p207"/>
|
||||
<configSetting altId="p207.gpio_mode.gpio_mode_out.low" configurationId="p207.gpio_mode"/>
|
||||
<configSetting altId="p208.output.low" configurationId="p208"/>
|
||||
<configSetting altId="p208.gpio_mode.gpio_mode_out.low" configurationId="p208.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p301.sci2.scl" configurationId="p301"/>
|
||||
<configSetting altId="p301.gpio_mode.gpio_mode_peripheral" configurationId="p301.gpio_mode"/>
|
||||
<configSetting altId="p301.gpio_otype.gpio_otype_n_ch_od" configurationId="p301.gpio_otype"/>
|
||||
<configSetting altId="p302.sci2.sda" configurationId="p302"/>
|
||||
<configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/>
|
||||
<configSetting altId="p302.gpio_otype.gpio_otype_n_ch_od" configurationId="p302.gpio_otype"/>
|
||||
<configSetting altId="p303.output.low" configurationId="p303"/>
|
||||
<configSetting altId="p303.gpio_mode.gpio_mode_out.low" configurationId="p303.gpio_mode"/>
|
||||
<configSetting altId="p304.output.low" configurationId="p304"/>
|
||||
<configSetting altId="p304.gpio_mode.gpio_mode_out.low" configurationId="p304.gpio_mode"/>
|
||||
<configSetting altId="p400.sci1.sck" configurationId="p400"/>
|
||||
<configSetting altId="p400.gpio_mode.gpio_mode_peripheral" configurationId="p400.gpio_mode"/>
|
||||
<configSetting altId="p401.sci1.txd" configurationId="p401"/>
|
||||
<configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
|
||||
<configSetting altId="p402.sci1.rxd" configurationId="p402"/>
|
||||
<configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/>
|
||||
<configSetting altId="p403.sci1.cts" configurationId="p403"/>
|
||||
<configSetting altId="p403.gpio_mode.gpio_mode_peripheral" configurationId="p403.gpio_mode"/>
|
||||
<configSetting altId="p407.iic0.sda" configurationId="p407"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="p408.iic0.scl" configurationId="p408"/>
|
||||
<configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/>
|
||||
<configSetting altId="p409.irq0.irq06" configurationId="p409"/>
|
||||
<configSetting altId="p409.gpio_irq.gpio_irq_enabled" configurationId="p409.gpio_irq"/>
|
||||
<configSetting altId="p409.gpio_mode.gpio_mode_irq" configurationId="p409.gpio_mode"/>
|
||||
<configSetting altId="p410.output.low" configurationId="p410"/>
|
||||
<configSetting altId="p410.gpio_mode.gpio_mode_out.low" configurationId="p410.gpio_mode"/>
|
||||
<configSetting altId="p411.irq0.irq04" configurationId="p411"/>
|
||||
<configSetting altId="p411.gpio_irq.gpio_irq_enabled" configurationId="p411.gpio_irq"/>
|
||||
<configSetting altId="p411.gpio_mode.gpio_mode_irq" configurationId="p411.gpio_mode"/>
|
||||
<configSetting altId="p501.output.low" configurationId="p501"/>
|
||||
<configSetting altId="p501.gpio_mode.gpio_mode_out.low" configurationId="p501.gpio_mode"/>
|
||||
<configSetting altId="p502.output.low" configurationId="p502"/>
|
||||
<configSetting altId="p502.gpio_mode.gpio_mode_out.low" configurationId="p502.gpio_mode"/>
|
||||
<configSetting altId="sci0.cts.p103" configurationId="sci0.cts"/>
|
||||
<configSetting altId="sci0.mode.spi.free" configurationId="sci0.mode"/>
|
||||
<configSetting altId="sci0.rxd.p100" configurationId="sci0.rxd"/>
|
||||
<configSetting altId="sci0.sck.p102" configurationId="sci0.sck"/>
|
||||
<configSetting altId="sci0.txd.p101" configurationId="sci0.txd"/>
|
||||
<configSetting altId="sci1.cts.p403" configurationId="sci1.cts"/>
|
||||
<configSetting altId="sci1.mode.spi.free" configurationId="sci1.mode"/>
|
||||
<configSetting altId="sci1.rxd.p402" configurationId="sci1.rxd"/>
|
||||
<configSetting altId="sci1.sck.p400" configurationId="sci1.sck"/>
|
||||
<configSetting altId="sci1.txd.p401" configurationId="sci1.txd"/>
|
||||
<configSetting altId="sci2.mode.iic.free" configurationId="sci2.mode"/>
|
||||
<configSetting altId="sci2.scl.p301" configurationId="sci2.scl"/>
|
||||
<configSetting altId="sci2.sda.p302" configurationId="sci2.sda"/>
|
||||
<configSetting altId="sci9.mode.asynchronous.free" configurationId="sci9.mode"/>
|
||||
<configSetting altId="sci9.rxd.p110" configurationId="sci9.rxd"/>
|
||||
<configSetting altId="sci9.txd.p109" configurationId="sci9.txd"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R7FA2L1AB2DFM.pincfg" selected="false" symbol="">
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
324
bsp/renesas/ra2l1-cpk/docs/LPM低功耗配置说明.md
Normal file
324
bsp/renesas/ra2l1-cpk/docs/LPM低功耗配置说明.md
Normal file
@ -0,0 +1,324 @@
|
||||
# LPM低功耗配置说明
|
||||
|
||||
## 基础知识
|
||||
|
||||
低功耗的本质是系统空闲时 CPU 停止工作，中断或事件唤醒后继续工作。在 RTOS 中，通常包含一个 IDLE 任务，该任务的优先级最低且一直保持就绪状态，当高优先级任务未就绪时，OS 执行 IDLE 任务。一般地，未进行低功耗处理时，CPU 在 IDLE 任务中循环执行空指令。RT-Thread 的电源管理组件在 IDLE 任务中，通过对 CPU 、时钟和设备等进行管理，从而有效降低系统的功耗。
|
||||
|
||||
|
||||
|
||||
在上图所示，当高优先级任务运行结束或被挂起时，系统将进入 IDLE 任务中。在 IDLE 任务执行后，它将判断系统是否可以进入到休眠状态（以节省功耗）。如果可以进入休眠， 将根据芯片情况关闭部分硬件模块，OS Tick 也非常有可能进入暂停状态。此时电源管理框架会根据系统定时器情况，计算出下一个超时时间点，并设置低功耗定时器，让设备能够在这个时刻点唤醒，并进行后续的工作。当系统被（低功耗定时器中断或其他唤醒中断源）唤醒后，系统也需要知道睡眠时间长度是多少，并对OS Tick 进行补偿，让系统的OS tick值调整为一个正确的值。
|
||||
|
||||
### [PM组件](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/pm/pm)
|
||||
|
||||
PM组件是RT-Thread系统中针对电源管理而设计的基础功能组件， 组件采用分层设计思想，分离架构和芯片相关的部分，提取公共部分作为核心。支持多种运行模式和休眠模式的管理切换，以及低功耗定时器的管理。
|
||||
|
||||
PM 组件有以下特点：
|
||||
|
||||
- PM 组件是基于模式来管理功耗
|
||||
- PM 组件可以根据模式自动更新设备的频率配置，确保在不同的运行模式都可以正常工作
|
||||
- PM 组件可以根据模式自动管理设备的挂起和恢复，确保在不同的休眠模式下可以正确的挂起和恢复
|
||||
- PM 组件支持可选的休眠时间补偿，让依赖 OS Tick 的应用可以透明使用
|
||||
- PM 组件向上层提供设备接口，如果使用了设备文件系统组件，那么也可以用文件系统接口来访问
|
||||
|
||||
PM组件支持的休眠模式有：
|
||||
|
||||
| 模式 | 描述 |
|
||||
| -------------------- | ---------------------------------- |
|
||||
| PM_SLEEP_MODE_NONE | 系统处于活跃状态，未采取任何的降低功耗状态 |
|
||||
| PM_SLEEP_MODE_IDLE | **空闲模式**，该模式在系统空闲时停止 CPU 和部分时钟，任意事件或中断均可以唤醒 |
|
||||
| PM_SLEEP_MODE_LIGHT | **轻度睡眠模式**，CPU 停止，多数时钟和外设停止，唤醒后需要进行时间补偿 |
|
||||
| PM_SLEEP_MODE_DEEP | **深度睡眠模式**，CPU 停止，仅少数低功耗外设工作，可被特殊中断唤醒 |
|
||||
| PM_SLEEP_MODE_STANDBY | **待机模式**，CPU 停止，设备上下文丢失(可保存至特殊外设)，唤醒后通常复位 |
|
||||
| PM_SLEEP_MODE_SHUTDOWN | **关断模式**，比 Standby 模式功耗更低， 上下文通常不可恢复， 唤醒后复位 |
|
||||
|
||||
### RA系列LPM功能
|
||||
|
||||
RA2 MCU支持的LPM类型有:
|
||||
|
||||
- Sleep mode
|
||||
- Software Standby mode
|
||||
- Snooze mode
|
||||
|
||||
| 休眠模式 | 描述 |
|
||||
| ----------------------- | ------------------------------------------------------------ |
|
||||
| LPM_MODE_SLEEP | **睡眠模式**，CPU停止工作，但其内部寄存器的内容被保留。其他外围功能在单片机中不停止。休眠模式下可用的复位或中断会导致MCU取消休眠模式。在这种模式下，所有的中断源都可用来取消Sleep模式。 |
|
||||
| LPM_MODE_STANDBY | **软件待机模式**，CPU、大部分片上外设功能和振荡器停止运行。但是，CPU内部寄存器的内容和SRAM数据、芯片上外围功能的状态和I/O端口状态都被保留。软件待机模式可以显著降低功耗，因为大多数振荡器在这种模式下停止。 |
|
||||
| LPM_MODE_STANDBY_SNOOZE | **小睡模式**，是软件待机模式的扩展，在这种模式下，有限的外设模块可以在不唤醒CPU的情况下运行。通过配置中断源，可以通过软件待机模式进入小睡模式。类似地，系统可以通过snooze模式支持的中断从snooze模式中唤醒。 |
|
||||
|
||||
低功耗模式转换和触发源如图所示。
|
||||
|
||||
|
||||
|
||||
不同模式间的切换如图所示，从图中也可以看出三种模式的功耗关系是Sleep>Snooze>Standby。
|
||||
|
||||
RA2芯片的休眠模式对应PM组件的模式关系：
|
||||
|
||||
| RA2芯片 | PM组件 |
|
||||
| ----------------------- | --------------------- |
|
||||
| LPM_MODE_SLEEP | PM_SLEEP_MODE_IDLE |
|
||||
| LPM_MODE_STANDBY | PM_SLEEP_MODE_DEEP |
|
||||
| LPM_MODE_STANDBY_SNOOZE | PM_SLEEP_MODE_STANDBY |
|
||||
|
||||
|
||||
## 配置LPM功能
|
||||
|
||||
要使用RA2系列芯片的LPM功能，需要进入bsp\renesas\ra2l1-cpk目录。
|
||||
|
||||
- 在menuconfig中使能LPM驱动，并勾选要开启的休眠模式，然后保存配置，生成MDK5工程。
|
||||
|
||||
|
||||
|
||||
- 打开PM组件和驱动后，需要增加idle的线程栈大小，可改为1024。
|
||||
|
||||
|
||||
|
||||
- 打开生成的MDK5工程project.uvprojx，然后打开FSP配置工具添加LPM相关配置。下图是需要添加的stack，包括三种LPM模式的配置以及低功耗定时器AGT1。
|
||||
|
||||
|
||||
|
||||
- 创建LPM如下图所示新建r_lpm，**需要根据使用的模式进行配置且不同模式要创建不同的r_lpm**。下面将分别介绍三种不同模式的配置，创建步骤就不再赘述。
|
||||
|
||||
|
||||
|
||||
### Sleep mode休眠模式
|
||||
|
||||
创建出r_lpm后需要修改Name和Low Power Mode这两个配置项。Name需要改为g_lpm_sleep，因为在驱动文件中已经定义了sleep模式对应的stack名称。Low Power Mode选择Sleep mode即可。
|
||||
|
||||
|
||||
|
||||
### Standby mode软件待机模式
|
||||
|
||||
Name需要改为g_lpm_sw_standby。Low Power Mode选择Software Standby mode即可。
|
||||
|
||||
另外在此模式下还需要配置唤醒MCU的中断源，因为会使用到AGT1做为低功耗定时器所以AGT1的中断需要勾选。如果在应用中还需要其他中断源在此模式下唤醒MCU，则勾选对应选项即可。
|
||||
|
||||
|
||||
|
||||
### Snooze mode小睡模式
|
||||
|
||||
Name需要改为g_lpm_sw_standby_with_snooze。Low Power Mode选择Snooze mode即可。
|
||||
|
||||
另外在此模式下同样要配置唤醒MCU的中断源，因为会使用到AGT1做为低功耗定时器所以AGT1的中断需要勾选。如果在应用中还需要其他中断源在此模式下唤醒MCU，则勾选对应选项即可。
|
||||
|
||||
|
||||
|
||||
### AGT1低功耗定时器
|
||||
|
||||
在驱动中使用了MCU的AGT1做为PM组件的低功耗定时器，用于在休眠状态下的系统时钟补偿。
|
||||
|
||||
|
||||
|
||||
完成上述配置步骤就已经把LPM低功耗模式的相关配置做完了。然后再根据应用要实现的功能配置其他外设。
|
||||
|
||||
|
||||
## 低功耗DEMO
|
||||
|
||||
上文介绍了在RT-Thread的RA2L1上怎么配置LPM的不同模式，接下来就用一个小DEMO来验证下MCU在各种模式下的工作情况。
|
||||
|
||||
低功耗DEMO要实现的功能是，在CPK-RA2L1开发板上用S1按钮切换不同的低功耗模式，并在msh中打印出模式切换的提示信息。要实现这个功能需要在刚才的基础上添加一个低功耗的唤醒源。
|
||||
|
||||
### 添加配置
|
||||
|
||||
- 创建IRQ中断，IRQ中断选择通道3，详细配置如下。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
- 在刚才的Snooze和Standby模式的配置里添加IRQ3的唤醒源
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
- 然后保存并生成配置代码。
|
||||
|
||||
### 添加测试代码
|
||||
|
||||
```c
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_LPM
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
#include <drivers/pm.h>
|
||||
|
||||
#define WAKEUP_APP_THREAD_STACK_SIZE 512
|
||||
#define WAKEUP_APP__THREAD_PRIORITY RT_THREAD_PRIORITY_MAX / 3
|
||||
#define WAKEUP_EVENT_BUTTON (1 << 0)
|
||||
|
||||
static rt_event_t wakeup_event;
|
||||
|
||||
#define USER_INPUT "P004"
|
||||
#define LED2_PIN "P501" /* Onboard LED pins */
|
||||
|
||||
void rt_lptimer_init(rt_lptimer_t timer,
|
||||
const char *name,
|
||||
void (*timeout)(void *parameter),
|
||||
void *parameter,
|
||||
rt_tick_t time,
|
||||
rt_uint8_t flag);
|
||||
|
||||
rt_err_t rt_lptimer_detach(rt_lptimer_t timer);
|
||||
rt_err_t rt_lptimer_start(rt_lptimer_t timer);
|
||||
rt_err_t rt_lptimer_stop(rt_lptimer_t timer);
|
||||
|
||||
rt_err_t rt_lptimer_control(rt_lptimer_t timer, int cmd, void *arg);
|
||||
|
||||
static struct rt_lptimer lptimer;
|
||||
|
||||
static void timeout_cb(void *parameter)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
rt_kprintf("\n lptimer callback \n");
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
static void lptimer_init(void)
|
||||
{
|
||||
rt_lptimer_init(&lptimer,
|
||||
"lpm",
|
||||
timeout_cb,
|
||||
(void*)&wakeup_event,
|
||||
1000,
|
||||
RT_TIMER_FLAG_PERIODIC);
|
||||
}
|
||||
|
||||
static void lptimer_stop(void)
|
||||
{
|
||||
rt_lptimer_stop(&lptimer);
|
||||
}
|
||||
|
||||
static void lptimer_start(void)
|
||||
{
|
||||
rt_lptimer_start(&lptimer);
|
||||
}
|
||||
|
||||
static void led_app(void)
|
||||
{
|
||||
static uint8_t key_status = 0x00;
|
||||
rt_uint32_t led2_pin = rt_pin_get(LED2_PIN);
|
||||
|
||||
rt_pin_write(led2_pin, PIN_HIGH);
|
||||
switch(key_status%4)
|
||||
{
|
||||
case 0:/* IDLE */
|
||||
lptimer_stop();
|
||||
rt_pm_release(PM_SLEEP_MODE_NONE);
|
||||
rt_kprintf("\trequest:IDLE\n");
|
||||
rt_pm_request(PM_SLEEP_MODE_IDLE);
|
||||
break;
|
||||
case 1:/* DEEP */
|
||||
lptimer_stop();
|
||||
lptimer_start();
|
||||
rt_pm_release(PM_SLEEP_MODE_IDLE);
|
||||
rt_kprintf("\trequest:DEEP\n");
|
||||
rt_pm_request(PM_SLEEP_MODE_DEEP);
|
||||
break;
|
||||
case 2:/* STANDBY */
|
||||
lptimer_stop();
|
||||
lptimer_start();
|
||||
rt_pm_release(PM_SLEEP_MODE_DEEP);
|
||||
rt_kprintf("\trequest:STANDBY\n");
|
||||
rt_pm_request(PM_SLEEP_MODE_STANDBY);
|
||||
break;
|
||||
case 3:/* NONE */
|
||||
lptimer_stop();
|
||||
rt_pm_release(PM_SLEEP_MODE_STANDBY);
|
||||
rt_kprintf("\trequest:NONE\n");
|
||||
rt_pm_request(PM_SLEEP_MODE_NONE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
key_status++;
|
||||
rt_pin_write(led2_pin, PIN_LOW);
|
||||
}
|
||||
|
||||
static void wakeup_callback(void* p)
|
||||
{
|
||||
rt_event_send(wakeup_event, WAKEUP_EVENT_BUTTON);
|
||||
}
|
||||
|
||||
void wakeup_sample(void)
|
||||
{
|
||||
/* init */
|
||||
rt_uint32_t pin = rt_pin_get(USER_INPUT);
|
||||
rt_kprintf("\n pin number : 0x%04X \n", pin);
|
||||
rt_err_t err = rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING, wakeup_callback, RT_NULL);
|
||||
if (RT_EOK != err)
|
||||
{
|
||||
rt_kprintf("\n attach irq failed. \n");
|
||||
}
|
||||
err = rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
|
||||
if (RT_EOK != err)
|
||||
{
|
||||
rt_kprintf("\n enable irq failed. \n");
|
||||
}
|
||||
}
|
||||
|
||||
static void wakeup_init(void)
|
||||
{
|
||||
wakeup_event = rt_event_create("wakup", RT_IPC_FLAG_FIFO);
|
||||
RT_ASSERT(wakeup_event != RT_NULL);
|
||||
wakeup_sample();
|
||||
}
|
||||
|
||||
static void pm_mode_init(void)
|
||||
{
|
||||
rt_pm_release_all(RT_PM_DEFAULT_SLEEP_MODE);
|
||||
rt_pm_request(PM_SLEEP_MODE_NONE);
|
||||
}
|
||||
|
||||
void pm_test_entry(void* para)
|
||||
{
|
||||
/* 唤醒回调函数初始化 */
|
||||
wakeup_init();
|
||||
|
||||
/* 电源管理初始化 */
|
||||
pm_mode_init();
|
||||
|
||||
lptimer_init();
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* 等待唤醒事件 */
|
||||
if (rt_event_recv(wakeup_event,
|
||||
WAKEUP_EVENT_BUTTON,
|
||||
RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR,
|
||||
RT_WAITING_FOREVER, RT_NULL) == RT_EOK)
|
||||
{
|
||||
led_app();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int pm_test(void)
|
||||
{
|
||||
|
||||
rt_thread_t tid = rt_thread_create(
|
||||
"pmtest",pm_test_entry,RT_NULL,512,10,10);
|
||||
if(tid)
|
||||
rt_thread_startup(tid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
MSH_CMD_EXPORT(pm_test, pm_test);
|
||||
// INIT_APP_EXPORT(pm_test);
|
||||
#endif
|
||||
```
|
||||
|
||||
将DEMO代码加入到工程中，可以直接添加到hal_entry.c或新建一个源文件。
|
||||
|
||||
|
||||
### 测试验证
|
||||
|
||||
然后编译下载。开发板连接串口工具，输入`pm_test`命令启动测试DEMO。
|
||||
|
||||
按下S1按钮切换工作模式，在DEEP、STANDBY模式下会启动低功耗定时器，当定时唤醒后会打印出回调接口的提示信息。
|
||||
|
||||
|
||||
|
||||
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 4.8 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash1.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash1.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 9.7 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash2.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash2.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 3.9 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash3.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/jflash3.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 21 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 24 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config1.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config1.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 32 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config2.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config2.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 36 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config3.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config3.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 28 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config4.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config4.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 51 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config5.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config5.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 45 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config6.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_config6.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 42 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo1.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo1.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 31 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo2.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo2.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 15 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo3.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo3.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 25 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo4.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo4.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 38 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo5.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo5.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 34 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo6.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_demo6.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 18 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_mode.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/lpm_mode.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 221 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/pm_ostick.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/pm_ostick.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 11 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/ra2l1-cpk.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/ra2l1-cpk.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 77 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/ra2l1-cpk1.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/ra2l1-cpk1.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 76 KiB |
BIN
bsp/renesas/ra2l1-cpk/docs/picture/readme_faq1.png
Normal file
BIN
bsp/renesas/ra2l1-cpk/docs/picture/readme_faq1.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 19 KiB |
801
bsp/renesas/ra2l1-cpk/project.uvoptx
Normal file
801
bsp/renesas/ra2l1-cpk/project.uvoptx
Normal file
@ -0,0 +1,801 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>1</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>4</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>Segger\JL2CM3.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA2L1_256K -FS00 -FL040000 -FF1RA2L1_DATA -FS140100000 -FL12000 -FF2RA2L1_CONF -FS21010000 -FL234 -FP0($$Device:R7FA2L1AB2DFM$Flash\RA2L1_256K.FLM) -FP1($$Device:R7FA2L1AB2DFM$Flash\RA2L1_DATA.FLM) -FP2($$Device:R7FA2L1AB2DFM$Flash\RA2L1_CONF.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>d</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U831004110 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8013 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>43</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>9320</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\src\hal_entry.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\rtthread\src/hal_entry.c\43</Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
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<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\clock.c</PathWithFileName>
|
||||
<FilenameWithoutPath>clock.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>33</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\components.c</PathWithFileName>
|
||||
<FilenameWithoutPath>components.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>34</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\device.c</PathWithFileName>
|
||||
<FilenameWithoutPath>device.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>35</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\idle.c</PathWithFileName>
|
||||
<FilenameWithoutPath>idle.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>36</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>ipc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>37</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\irq.c</PathWithFileName>
|
||||
<FilenameWithoutPath>irq.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>38</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\kservice.c</PathWithFileName>
|
||||
<FilenameWithoutPath>kservice.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>39</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\mem.c</PathWithFileName>
|
||||
<FilenameWithoutPath>mem.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>40</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\object.c</PathWithFileName>
|
||||
<FilenameWithoutPath>object.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>41</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\scheduler.c</PathWithFileName>
|
||||
<FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>42</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\thread.c</PathWithFileName>
|
||||
<FilenameWithoutPath>thread.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>43</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\src\timer.c</PathWithFileName>
|
||||
<FilenameWithoutPath>timer.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>44</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\src\hal_entry.c</PathWithFileName>
|
||||
<FilenameWithoutPath>hal_entry.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Flex Software</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
818
bsp/renesas/ra2l1-cpk/project.uvprojx
Normal file
818
bsp/renesas/ra2l1-cpk/project.uvprojx
Normal file
@ -0,0 +1,818 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>R7FA2L1AB2DFM</Device>
|
||||
<Vendor>Renesas</Vendor>
|
||||
<PackID>Renesas.RA_DFP.3.1.0</PackID>
|
||||
<PackURL>https://www2.renesas.eu/Keil_MDK_Packs/</PackURL>
|
||||
<Cpu>CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll></FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile></RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:R7FA2L1AB2DFM$SVD\R7FA2L1AB.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>0</UseTargetDll>
|
||||
<UseExternalTool>1</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2></Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M23"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>0</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>0</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
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<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Finsh</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>shell.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>msh.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>msh_parse.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>cmd.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>clock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\clock.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>components.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\components.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>device.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\device.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>idle.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\idle.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ipc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\ipc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>irq.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\irq.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>kservice.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\kservice.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\mem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>object.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\object.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>scheduler.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\scheduler.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>thread.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\thread.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>hal_entry.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\src\hal_entry.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Flex Software</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<gpdscs>
|
||||
<gpdsc name="buildinfo.gpdsc">
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</gpdsc>
|
||||
</gpdscs>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="Flex Software" Cgroup="RA Configuration" Cvendor="Renesas" Cversion="1.0.0" condition="RA Device" generator="Renesas RA Smart Configurator">
|
||||
<package name="RA_DFP" schemaVersion="1.6.0" url="https://www2.renesas.eu/Keil_MDK_Packs/" vendor="Renesas" version="3.1.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
34
bsp/renesas/ra2l1-cpk/ra/SConscript
Normal file
34
bsp/renesas/ra2l1-cpk/ra/SConscript
Normal file
@ -0,0 +1,34 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = []
|
||||
group = []
|
||||
CPPPATH = []
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
print("\nThe current project does not support iar build\n")
|
||||
Return('group')
|
||||
elif rtconfig.PLATFORM == 'gcc':
|
||||
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
|
||||
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
|
||||
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
|
||||
src += Glob(cwd + '/fsp/src/r_*/*.c')
|
||||
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
|
||||
cwd + '/fsp/inc',
|
||||
cwd + '/fsp/inc/api',
|
||||
cwd + '/fsp/inc/instances',]
|
||||
elif rtconfig.PLATFORM == 'armclang':
|
||||
if GetOption('target') != 'mdk5':
|
||||
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
|
||||
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
|
||||
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
|
||||
src += Glob(cwd + '/fsp/src/r_*/*.c')
|
||||
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
|
||||
cwd + '/fsp/inc',
|
||||
cwd + '/fsp/inc/api',
|
||||
cwd + '/fsp/inc/instances',]
|
||||
|
||||
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
|
||||
Return('group')
|
||||
@ -0,0 +1,411 @@
|
||||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.1
|
||||
* @date 19. April 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
@ -0,0 +1,888 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.3.2
|
||||
* @date 27. May 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
__ISB();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,283 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
2211
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
Normal file
2211
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,952 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.8
|
||||
* @date 21. August 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
|
||||
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,979 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.1
|
||||
* @date 12. November 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
2297
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
Normal file
2297
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1943
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
Normal file
1943
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
3265
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
Normal file
3265
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
3265
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
Normal file
3265
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
Normal file
File diff suppressed because it is too large
Load Diff
2129
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
Normal file
2129
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
4278
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
Normal file
4278
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
Normal file
File diff suppressed because it is too large
Load Diff
2366
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
Normal file
2366
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
1030
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
Normal file
1030
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h
Normal file
File diff suppressed because it is too large
Load Diff
1917
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
Normal file
1917
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,275 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 25. May 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,352 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.3
|
||||
* @date 03. February 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,337 @@
|
||||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.1
|
||||
* @date 15. April 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
201
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/LICENSE.txt
Normal file
201
bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/LICENSE.txt
Normal file
@ -0,0 +1,201 @@
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
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|
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||||
65
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board.h
Normal file
65
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board.h
Normal file
@ -0,0 +1,65 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||
*
|
||||
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||
*
|
||||
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||
*
|
||||
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
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||||
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||
* included in this file may be subject to different terms.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : board.h
|
||||
* Description : Includes and API function available for this board.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup BSP_Boards
|
||||
* @defgroup BOARD_RA2L1_CPK for the RA2L1_CPK Board
|
||||
* @brief BSP for the RA2L1_CPK Board
|
||||
*
|
||||
* The RA2L1_CPK is a development kit for the Renesas RA6M2 microcontroller.
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* BSP Board Specific Includes. */
|
||||
#include "../ra2l1_cpk/board_init.h"
|
||||
#include "../ra2l1_cpk/board_leds.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#define BOARD_RA2L1_CPK
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global functions (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @} (end defgroup BOARD_RA2L1_CPK) */
|
||||
|
||||
#endif
|
||||
66
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_init.c
Normal file
66
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_init.c
Normal file
@ -0,0 +1,66 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||
*
|
||||
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||
*
|
||||
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||
*
|
||||
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||
* included in this file may be subject to different terms.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : bsp_init.c
|
||||
* Description : This module calls any initialization code specific to this BSP.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup BOARD_RA2L1_CPK_INIT
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
|
||||
#if defined(BOARD_RA2L1_CPK)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Private global variables and functions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @brief Performs any initialization specific to this BSP.
|
||||
*
|
||||
* @param[in] p_args Pointer to arguments of the user's choice.
|
||||
**********************************************************************************************************************/
|
||||
void bsp_init (void * p_args)
|
||||
{
|
||||
FSP_PARAMETER_NOT_USED(p_args);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/** @} (end addtogroup BOARD_RA2L1_CPK_INIT) */
|
||||
63
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_init.h
Normal file
63
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_init.h
Normal file
@ -0,0 +1,63 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||
*
|
||||
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||
*
|
||||
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||
*
|
||||
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||
* included in this file may be subject to different terms.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : board_init.h
|
||||
* Description : This module calls any initialization code specific to this BSP.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup BOARD_RA2L1_CPK
|
||||
* @defgroup BOARD_RA2L1_CPK Board Specific Code
|
||||
* @brief Board specific code for the RA2L1_CPK Board
|
||||
*
|
||||
* This is code specific to the RA2L1_CPK board.
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef BOARD_INIT_H
|
||||
#define BOARD_INIT_H
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global functions (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
||||
/** @} (end defgroup BOARD_RA2L1_CPK_INIT) */
|
||||
75
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_leds.c
Normal file
75
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_leds.c
Normal file
@ -0,0 +1,75 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||
*
|
||||
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||
*
|
||||
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||
*
|
||||
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||
* included in this file may be subject to different terms.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : board_leds.c
|
||||
* Description : This module has information about the LEDs on this board.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup BSP_RA2L1_CPK_LEDS
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
|
||||
#if defined(BOARD_RA2L1_CPK)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Private global variables and functions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Array of LED IOPORT pins. */
|
||||
static const uint16_t g_bsp_prv_leds[] =
|
||||
{
|
||||
(uint16_t) BSP_IO_PORT_05_PIN_02, ///< USER LED1
|
||||
(uint16_t) BSP_IO_PORT_05_PIN_01, ///< USER LED2
|
||||
};
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Structure with LED information for this board. */
|
||||
|
||||
const bsp_leds_t g_bsp_leds =
|
||||
{
|
||||
.led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
|
||||
.p_leds = &g_bsp_prv_leds[0]
|
||||
};
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#endif
|
||||
|
||||
/** @} (end addtogroup BSP_RA2L1_CPK_LEDS) */
|
||||
75
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_leds.h
Normal file
75
bsp/renesas/ra2l1-cpk/ra/board/ra2l1_cpk/board_leds.h
Normal file
@ -0,0 +1,75 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||
*
|
||||
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||
*
|
||||
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||
*
|
||||
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||
* included in this file may be subject to different terms.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : board_leds.h
|
||||
* Description : This module has information about the LEDs on this board.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup BOARD_RA2L1_CPK
|
||||
* @defgroup BSP_RA2L1_CPK_LEDS Board LEDs
|
||||
* @brief LED information for this board.
|
||||
*
|
||||
* This is code specific to the RA2L1_CPK board.
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef BOARD_LEDS_H
|
||||
#define BOARD_LEDS_H
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Information on how many LEDs and what pins they are on. */
|
||||
typedef struct st_bsp_leds
|
||||
{
|
||||
uint16_t led_count; ///< The number of LEDs on this board
|
||||
uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs
|
||||
} bsp_leds_t;
|
||||
|
||||
/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
|
||||
* found in the bsp_leds_t structure. */
|
||||
typedef enum e_bsp_led
|
||||
{
|
||||
BSP_LED_LED3 = 0, ///< TB LED - Red
|
||||
} bsp_led_t;
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Public Functions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif /* BOARD_LEDS_H */
|
||||
|
||||
/** @} (end defgroup BSP_RA2L1_CPK_LEDS) */
|
||||
107
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/bsp_api.h
Normal file
107
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/bsp_api.h
Normal file
@ -0,0 +1,107 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef BSP_API_H
|
||||
#define BSP_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* FSP Common Includes. */
|
||||
#include "fsp_common_api.h"
|
||||
|
||||
/* Gets MCU configuration information. */
|
||||
#include "bsp_cfg.h"
|
||||
|
||||
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||
|
||||
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
|
||||
* We are not modifying these files so we will ignore these warnings temporarily. */
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#endif
|
||||
|
||||
/* Vector information for this project. This is generated by the tooling. */
|
||||
#include "../../src/bsp/mcu/all/bsp_arm_exceptions.h"
|
||||
#include "vector_data.h"
|
||||
|
||||
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
|
||||
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
|
||||
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
|
||||
|
||||
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||
|
||||
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/* BSP Common Includes. */
|
||||
#include "../../src/bsp/mcu/all/bsp_common.h"
|
||||
|
||||
/* BSP MCU Specific Includes. */
|
||||
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_irq.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_io.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_clocks.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_security.h"
|
||||
|
||||
/* Factory MCU information. */
|
||||
#include "../../inc/fsp_features.h"
|
||||
|
||||
/* BSP Common Includes (Other than bsp_common.h) */
|
||||
#include "../../src/bsp/mcu/all/bsp_delay.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
|
||||
|
||||
/* BSP TFU Includes. */
|
||||
#if BSP_FEATURE_TFU_SUPPORTED
|
||||
#include "../../src/bsp/mcu/all/bsp_tfu.h"
|
||||
#endif
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global functions (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup BSP_MCU
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
|
||||
|
||||
/** @} (end addtogroup BSP_MCU) */
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
177
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h
Normal file
177
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h
Normal file
@ -0,0 +1,177 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup EXTERNAL_IRQ_API External IRQ Interface
|
||||
* @brief Interface for detecting external interrupts.
|
||||
*
|
||||
* @section EXTERNAL_IRQ_API_Summary Summary
|
||||
* The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an
|
||||
* external IRQ pin.
|
||||
*
|
||||
* The External IRQ Interface can be implemented by:
|
||||
* - @ref ICU
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_EXTERNAL_IRQ_API_H
|
||||
#define R_EXTERNAL_IRQ_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/*********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/** Callback function parameter data */
|
||||
typedef struct st_external_irq_callback_args
|
||||
{
|
||||
/** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */
|
||||
void const * p_context;
|
||||
uint32_t channel; ///< The physical hardware channel that caused the interrupt.
|
||||
} external_irq_callback_args_t;
|
||||
|
||||
/** Condition that will trigger an interrupt when detected. */
|
||||
typedef enum e_external_irq_trigger
|
||||
{
|
||||
EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger
|
||||
EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger
|
||||
EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger
|
||||
EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger
|
||||
} external_irq_trigger_t;
|
||||
|
||||
/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger
|
||||
* conditions that are shorter than 3 periods of the filter clock.
|
||||
*/
|
||||
typedef enum e_external_irq_pclk_div
|
||||
{
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_1 = 0, ///< Filter using PCLK divided by 1
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_8 = 1, ///< Filter using PCLK divided by 8
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2, ///< Filter using PCLK divided by 32
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3, ///< Filter using PCLK divided by 64
|
||||
} external_irq_pclk_div_t;
|
||||
|
||||
/** User configuration structure, used in open function */
|
||||
typedef struct st_external_irq_cfg
|
||||
{
|
||||
uint8_t channel; ///< Hardware channel used.
|
||||
uint8_t ipl; ///< Interrupt priority
|
||||
IRQn_Type irq; ///< NVIC interrupt number assigned to this instance
|
||||
external_irq_trigger_t trigger; ///< Trigger setting.
|
||||
external_irq_pclk_div_t pclk_div; ///< Digital filter clock divisor setting.
|
||||
bool filter_enable; ///< Digital filter enable/disable setting.
|
||||
|
||||
/** Callback provided external input trigger occurs. */
|
||||
void (* p_callback)(external_irq_callback_args_t * p_args);
|
||||
|
||||
/** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */
|
||||
void const * p_context;
|
||||
void const * p_extend; ///< External IRQ hardware dependent configuration.
|
||||
} external_irq_cfg_t;
|
||||
|
||||
/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls.
|
||||
* @par Implemented as
|
||||
* - icu_instance_ctrl_t
|
||||
*/
|
||||
typedef void external_irq_ctrl_t;
|
||||
|
||||
/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */
|
||||
typedef struct st_external_irq_api
|
||||
{
|
||||
/** Initial configuration.
|
||||
* @par Implemented as
|
||||
* - @ref R_ICU_ExternalIrqOpen()
|
||||
*
|
||||
* @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here.
|
||||
* @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user.
|
||||
*/
|
||||
fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg);
|
||||
|
||||
/** Enable callback when an external trigger condition occurs.
|
||||
* @par Implemented as
|
||||
* - @ref R_ICU_ExternalIrqEnable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
|
||||
*/
|
||||
fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Disable callback when external trigger condition occurs.
|
||||
* @par Implemented as
|
||||
* - @ref R_ICU_ExternalIrqDisable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
|
||||
*/
|
||||
fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl);
|
||||
|
||||
/**
|
||||
* Specify callback function and optional context pointer and working memory pointer.
|
||||
* @par Implemented as
|
||||
* - R_ICU_ExternalIrqCallbackSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the Extneral IRQ control block.
|
||||
* @param[in] p_callback Callback function
|
||||
* @param[in] p_context Pointer to send to callback function
|
||||
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||
* Callback arguments allocated here are only valid during the callback.
|
||||
*/
|
||||
fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_api_ctrl,
|
||||
void ( * p_callback)(external_irq_callback_args_t *),
|
||||
void const * const p_context,
|
||||
external_irq_callback_args_t * const p_callback_memory);
|
||||
|
||||
/** Allow driver to be reconfigured. May reduce power consumption.
|
||||
* @par Implemented as
|
||||
* - @ref R_ICU_ExternalIrqClose()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
|
||||
*/
|
||||
fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl);
|
||||
} external_irq_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_external_irq_instance
|
||||
{
|
||||
external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} external_irq_instance_t;
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup EXTERNAL_IRQ_API)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#endif
|
||||
384
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_ioport_api.h
Normal file
384
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_ioport_api.h
Normal file
@ -0,0 +1,384 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup IOPORT_API I/O Port Interface
|
||||
* @brief Interface for accessing I/O ports and configuring I/O functionality.
|
||||
*
|
||||
* @section IOPORT_API_SUMMARY Summary
|
||||
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
|
||||
* Port and pin direction can be changed.
|
||||
*
|
||||
* IOPORT Interface description: @ref IOPORT
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_IOPORT_API_H
|
||||
#define R_IOPORT_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common error codes and definitions. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Private definition to set enumeration values. */
|
||||
#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** IO port type used with ports */
|
||||
typedef uint16_t ioport_size_t; ///< IO port size on this device
|
||||
|
||||
/** Superset of all peripheral functions. */
|
||||
typedef enum e_ioport_peripheral
|
||||
{
|
||||
/** Pin will functions as an IO pin */
|
||||
IOPORT_PERIPHERAL_IO = 0x00,
|
||||
|
||||
/** Pin will function as a DEBUG pin */
|
||||
IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an AGT peripheral pin */
|
||||
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a GPT peripheral pin */
|
||||
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a GPT peripheral pin */
|
||||
IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an SCI peripheral pin */
|
||||
IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an SCI peripheral pin */
|
||||
IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a SPI peripheral pin */
|
||||
IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a IIC peripheral pin */
|
||||
IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a KEY peripheral pin */
|
||||
IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a clock/comparator/RTC peripheral pin */
|
||||
IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a CAC/ADC peripheral pin */
|
||||
IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a BUS peripheral pin */
|
||||
IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a CTSU peripheral pin */
|
||||
IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a CMPHS peripheral pin */
|
||||
IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a segment LCD peripheral pin */
|
||||
IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an SCI peripheral DEn pin */
|
||||
IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a DALI peripheral pin */
|
||||
IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an SCI DEn peripheral pin */
|
||||
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a CAN peripheral pin */
|
||||
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a QSPI peripheral pin */
|
||||
IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an SSI peripheral pin */
|
||||
IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a USB full speed peripheral pin */
|
||||
IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a USB high speed peripheral pin */
|
||||
IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a GPT peripheral pin */
|
||||
IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an SD/MMC peripheral pin */
|
||||
IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a GPT peripheral pin */
|
||||
IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an Ethernet MMI peripheral pin */
|
||||
IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a GPT peripheral pin */
|
||||
IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as an Ethernet RMMI peripheral pin */
|
||||
IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a PDC peripheral pin */
|
||||
IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a graphics LCD peripheral pin */
|
||||
IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a CAC peripheral pin */
|
||||
IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a debug trace peripheral pin */
|
||||
IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a OSPI peripheral pin */
|
||||
IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a CEC peripheral pin */
|
||||
IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a PGAOUT peripheral pin */
|
||||
IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a PGAOUT peripheral pin */
|
||||
IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
} ioport_peripheral_t;
|
||||
|
||||
/* DEPRECATED Superset of Ethernet channels. */
|
||||
typedef enum e_ioport_eth_ch
|
||||
{
|
||||
IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
|
||||
IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1
|
||||
IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_ethernet_channel_t;
|
||||
|
||||
/* DEPRECATED Superset of Ethernet PHY modes. */
|
||||
typedef enum e_ioport_eth_mode
|
||||
{
|
||||
IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
|
||||
IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII
|
||||
IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_ethernet_mode_t;
|
||||
|
||||
/** Options to configure pin functions */
|
||||
typedef enum e_ioport_cfg_options
|
||||
{
|
||||
IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default)
|
||||
IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output
|
||||
IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low
|
||||
IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high
|
||||
IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up
|
||||
IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode
|
||||
IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output
|
||||
IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput
|
||||
IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium
|
||||
IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed
|
||||
IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port
|
||||
IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high
|
||||
IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge
|
||||
IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge
|
||||
IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges
|
||||
IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin
|
||||
IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin
|
||||
IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin
|
||||
} ioport_cfg_options_t;
|
||||
|
||||
/* PFS writing enable/disable. */
|
||||
typedef enum e_ioport_pwpr
|
||||
{
|
||||
IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access
|
||||
IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access
|
||||
} ioport_pwpr_t;
|
||||
|
||||
/** Pin identifier and pin PFS pin configuration value */
|
||||
typedef struct st_ioport_pin_cfg
|
||||
{
|
||||
uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure
|
||||
bsp_io_port_pin_t pin; ///< Pin identifier
|
||||
} ioport_pin_cfg_t;
|
||||
|
||||
/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */
|
||||
typedef struct st_ioport_cfg
|
||||
{
|
||||
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
|
||||
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
|
||||
} ioport_cfg_t;
|
||||
|
||||
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
|
||||
* @par Implemented as
|
||||
* - ioport_instance_ctrl_t
|
||||
*/
|
||||
typedef void ioport_ctrl_t;
|
||||
|
||||
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
|
||||
typedef struct st_ioport_api
|
||||
{
|
||||
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
|
||||
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
|
||||
* multiple pins.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_Open()
|
||||
* @param[in] p_cfg Pointer to pin configuration data array.
|
||||
*/
|
||||
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
|
||||
/** Close the API.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
**/
|
||||
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Configure multiple pins.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinsCfg()
|
||||
* @param[in] p_cfg Pointer to pin configuration data array.
|
||||
*/
|
||||
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
|
||||
/** Configure settings for an individual pin.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinCfg()
|
||||
* @param[in] pin Pin to be read.
|
||||
* @param[in] cfg Configuration options for the pin.
|
||||
*/
|
||||
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
|
||||
|
||||
/** Read the event input data of the specified pin and return the level.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinEventInputRead()
|
||||
* @param[in] pin Pin to be read.
|
||||
* @param[in] p_pin_event Pointer to return the event data.
|
||||
*/
|
||||
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
|
||||
|
||||
/** Write pin event data.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinEventOutputWrite()
|
||||
* @param[in] pin Pin event data is to be written to.
|
||||
* @param[in] pin_value Level to be written to pin output event.
|
||||
*/
|
||||
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
|
||||
|
||||
/* DEPRECATED Configure the PHY mode of the Ethernet channels.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_EthernetModeCfg()
|
||||
* @param[in] channel Channel configuration will be set for.
|
||||
* @param[in] mode PHY mode to set the channel to.
|
||||
*/
|
||||
fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
|
||||
ioport_ethernet_mode_t mode);
|
||||
|
||||
/** Read level of a pin.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinRead()
|
||||
* @param[in] pin Pin to be read.
|
||||
* @param[in] p_pin_value Pointer to return the pin level.
|
||||
*/
|
||||
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
|
||||
|
||||
/** Write specified level to a pin.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinWrite()
|
||||
* @param[in] pin Pin to be written to.
|
||||
* @param[in] level State to be written to the pin.
|
||||
*/
|
||||
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
|
||||
|
||||
/** Set the direction of one or more pins on a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortDirectionSet()
|
||||
* @param[in] port Port being configured.
|
||||
* @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input).
|
||||
* @param[in] mask Mask controlling which pins on the port are to be configured.
|
||||
*/
|
||||
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
|
||||
ioport_size_t mask);
|
||||
|
||||
/** Read captured event data for a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortEventInputRead()
|
||||
* @param[in] port Port to be read.
|
||||
* @param[in] p_event_data Pointer to return the event data.
|
||||
*/
|
||||
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
|
||||
|
||||
/** Write event output data for a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortEventOutputWrite()
|
||||
* @param[in] port Port event data will be written to.
|
||||
* @param[in] event_data Data to be written as event data to specified port.
|
||||
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
|
||||
* being written to port.
|
||||
*/
|
||||
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
|
||||
ioport_size_t mask_value);
|
||||
|
||||
/** Read states of pins on the specified port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortRead()
|
||||
* @param[in] port Port to be read.
|
||||
* @param[in] p_port_value Pointer to return the port value.
|
||||
*/
|
||||
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
|
||||
|
||||
/** Write to multiple pins on a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortWrite()
|
||||
* @param[in] port Port to be written to.
|
||||
* @param[in] value Value to be written to the port.
|
||||
* @param[in] mask Mask controlling which pins on the port are written to.
|
||||
*/
|
||||
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
|
||||
} ioport_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_ioport_instance
|
||||
{
|
||||
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} ioport_instance_t;
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup IOPORT_API)
|
||||
**********************************************************************************************************************/
|
||||
371
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_transfer_api.h
Normal file
371
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_transfer_api.h
Normal file
@ -0,0 +1,371 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup TRANSFER_API Transfer Interface
|
||||
*
|
||||
* @brief Interface for data transfer functions.
|
||||
*
|
||||
* @section TRANSFER_API_SUMMARY Summary
|
||||
* The transfer interface supports background data transfer (no CPU intervention).
|
||||
*
|
||||
* Implemented by:
|
||||
* - @ref DTC
|
||||
* - @ref DMAC
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_TRANSFER_API_H
|
||||
#define R_TRANSFER_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common error codes and definitions. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#define TRANSFER_SETTINGS_MODE_BITS (30U)
|
||||
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
|
||||
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
|
||||
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
|
||||
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
|
||||
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
|
||||
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
|
||||
* @par Implemented as
|
||||
* - dtc_instance_ctrl_t
|
||||
* - dmac_instance_ctrl_t
|
||||
*/
|
||||
typedef void transfer_ctrl_t;
|
||||
|
||||
/** Transfer mode describes what will happen when a transfer request occurs. */
|
||||
typedef enum e_transfer_mode
|
||||
{
|
||||
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
|
||||
* the destination pointer. The transfer length is decremented and the source and address pointers are
|
||||
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
|
||||
* will not cause any further transfers. */
|
||||
TRANSFER_MODE_NORMAL = 0,
|
||||
|
||||
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
|
||||
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
|
||||
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
|
||||
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
|
||||
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
|
||||
TRANSFER_MODE_REPEAT = 1,
|
||||
|
||||
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
|
||||
* After each individual transfer, the source and destination pointers are updated according to
|
||||
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
|
||||
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
|
||||
* further transfers. */
|
||||
TRANSFER_MODE_BLOCK = 2,
|
||||
|
||||
/** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
|
||||
* within a block (to split blocks into arrays of their first data, second data, etc.) */
|
||||
TRANSFER_MODE_REPEAT_BLOCK = 3
|
||||
} transfer_mode_t;
|
||||
|
||||
/** Transfer size specifies the size of each individual transfer.
|
||||
* Total transfer length = transfer_size_t * transfer_length_t
|
||||
*/
|
||||
typedef enum e_transfer_size
|
||||
{
|
||||
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
|
||||
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
|
||||
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
|
||||
} transfer_size_t;
|
||||
|
||||
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
|
||||
typedef enum e_transfer_addr_mode
|
||||
{
|
||||
/** Address pointer remains fixed after each transfer. */
|
||||
TRANSFER_ADDR_MODE_FIXED = 0,
|
||||
|
||||
/** Offset is added to the address pointer after each transfer. */
|
||||
TRANSFER_ADDR_MODE_OFFSET = 1,
|
||||
|
||||
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
|
||||
TRANSFER_ADDR_MODE_INCREMENTED = 2,
|
||||
|
||||
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
|
||||
TRANSFER_ADDR_MODE_DECREMENTED = 3
|
||||
} transfer_addr_mode_t;
|
||||
|
||||
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
|
||||
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
|
||||
* the selected pointer returns to its original value after each transfer. */
|
||||
typedef enum e_transfer_repeat_area
|
||||
{
|
||||
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
|
||||
TRANSFER_REPEAT_AREA_DESTINATION = 0,
|
||||
|
||||
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
|
||||
TRANSFER_REPEAT_AREA_SOURCE = 1
|
||||
} transfer_repeat_area_t;
|
||||
|
||||
/** Chain transfer mode options.
|
||||
* @note Only applies for DTC. */
|
||||
typedef enum e_transfer_chain_mode
|
||||
{
|
||||
/** Chain mode not used. */
|
||||
TRANSFER_CHAIN_MODE_DISABLED = 0,
|
||||
|
||||
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
|
||||
TRANSFER_CHAIN_MODE_EACH = 2,
|
||||
|
||||
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
|
||||
TRANSFER_CHAIN_MODE_END = 3
|
||||
} transfer_chain_mode_t;
|
||||
|
||||
/** Interrupt options. */
|
||||
typedef enum e_transfer_irq
|
||||
{
|
||||
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
|
||||
* the interrupt will occur only after subsequent chained transfer(s) are complete.
|
||||
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
|
||||
* prevent activation source interrupts until the transfer is complete. */
|
||||
TRANSFER_IRQ_END = 0,
|
||||
|
||||
/** Interrupt occurs after each transfer.
|
||||
* @note Not available in all HAL drivers. See HAL driver for details. */
|
||||
TRANSFER_IRQ_EACH = 1
|
||||
} transfer_irq_t;
|
||||
|
||||
/** Driver specific information. */
|
||||
typedef struct st_transfer_properties
|
||||
{
|
||||
uint32_t block_count_max; ///< Maximum number of blocks
|
||||
uint32_t block_count_remaining; ///< Number of blocks remaining
|
||||
uint32_t transfer_length_max; ///< Maximum number of transfers
|
||||
uint32_t transfer_length_remaining; ///< Number of transfers remaining
|
||||
} transfer_properties_t;
|
||||
|
||||
/** This structure specifies the properties of the transfer.
|
||||
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
|
||||
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
|
||||
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
|
||||
* have a unique transfer_info_t.
|
||||
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
|
||||
* structure must remain in scope until the transfer it is used for is closed.
|
||||
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
|
||||
typedef struct st_transfer_info
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t : 16;
|
||||
uint32_t : 2;
|
||||
|
||||
/** Select what happens to destination pointer after each transfer. */
|
||||
transfer_addr_mode_t dest_addr_mode : 2;
|
||||
|
||||
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
|
||||
transfer_repeat_area_t repeat_area : 1;
|
||||
|
||||
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
|
||||
* transfers. */
|
||||
transfer_irq_t irq : 1;
|
||||
|
||||
/** Select when the chain transfer ends. */
|
||||
transfer_chain_mode_t chain_mode : 2;
|
||||
|
||||
uint32_t : 2;
|
||||
|
||||
/** Select what happens to source pointer after each transfer. */
|
||||
transfer_addr_mode_t src_addr_mode : 2;
|
||||
|
||||
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
|
||||
transfer_size_t size : 2;
|
||||
|
||||
/** Select mode from @ref transfer_mode_t. */
|
||||
transfer_mode_t mode : 2;
|
||||
};
|
||||
uint32_t transfer_settings_word;
|
||||
};
|
||||
|
||||
void const * volatile p_src; ///< Source pointer
|
||||
void * volatile p_dest; ///< Destination pointer
|
||||
|
||||
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
|
||||
* @ref TRANSFER_MODE_REPEAT (DMAC only) or
|
||||
* @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
|
||||
volatile uint16_t num_blocks;
|
||||
|
||||
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
|
||||
* and @ref TRANSFER_MODE_REPEAT_BLOCK
|
||||
* see HAL driver for details. */
|
||||
volatile uint16_t length;
|
||||
} transfer_info_t;
|
||||
|
||||
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
|
||||
* initialized. */
|
||||
typedef struct st_transfer_cfg
|
||||
{
|
||||
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
|
||||
* an array of chained transfers that will be completed in order. */
|
||||
transfer_info_t * p_info;
|
||||
|
||||
void const * p_extend; ///< Extension parameter for hardware specific settings.
|
||||
} transfer_cfg_t;
|
||||
|
||||
/** Select whether to start single or repeated transfer with software start. */
|
||||
typedef enum e_transfer_start_mode
|
||||
{
|
||||
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
|
||||
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
|
||||
} transfer_start_mode_t;
|
||||
|
||||
/** Transfer functions implemented at the HAL layer will follow this API. */
|
||||
typedef struct st_transfer_api
|
||||
{
|
||||
/** Initial configuration.
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_Open()
|
||||
* - @ref R_DMAC_Open()
|
||||
*
|
||||
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
|
||||
* must be set by user.
|
||||
*/
|
||||
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
|
||||
|
||||
/** Reconfigure the transfer.
|
||||
* Enable the transfer if p_info is valid.
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_Reconfigure()
|
||||
* - @ref R_DMAC_Reconfigure()
|
||||
*
|
||||
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||
* @param[in] p_info Pointer to a new transfer info structure.
|
||||
*/
|
||||
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
|
||||
|
||||
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
|
||||
* Enable the transfer if p_src, p_dest, and length are valid.
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_Reset()
|
||||
* - @ref R_DMAC_Reset()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
|
||||
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
|
||||
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
|
||||
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
|
||||
* repeat mode. Not used in repeat mode for DTC.
|
||||
*/
|
||||
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
|
||||
uint16_t const num_transfers);
|
||||
|
||||
/** Enable transfer. Transfers occur after the activation source event (or when
|
||||
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source).
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_Enable()
|
||||
* - @ref R_DMAC_Enable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Disable transfer. Transfers do not occur after the activation source event (or when
|
||||
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source).
|
||||
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
|
||||
* transfer.
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_Disable()
|
||||
* - @ref R_DMAC_Disable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Start transfer in software.
|
||||
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
|
||||
* @note Not supported for DTC.
|
||||
* @par Implemented as
|
||||
* - @ref R_DMAC_SoftwareStart()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
* @param[in] mode Select mode from @ref transfer_start_mode_t.
|
||||
*/
|
||||
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
|
||||
|
||||
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
|
||||
* @note Not supported for DTC.
|
||||
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
|
||||
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
|
||||
* @par Implemented as
|
||||
* - @ref R_DMAC_SoftwareStop()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Provides information about this transfer.
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_InfoGet()
|
||||
* - @ref R_DMAC_InfoGet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
* @param[out] p_properties Driver specific information.
|
||||
*/
|
||||
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
|
||||
|
||||
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
|
||||
* @par Implemented as
|
||||
* - @ref R_DTC_Close()
|
||||
* - @ref R_DMAC_Close()
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
|
||||
} transfer_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_transfer_instance
|
||||
{
|
||||
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} transfer_instance_t;
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup TRANSFER_API)
|
||||
**********************************************************************************************************************/
|
||||
293
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_uart_api.h
Normal file
293
bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_uart_api.h
Normal file
@ -0,0 +1,293 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup UART_API UART Interface
|
||||
* @brief Interface for UART communications.
|
||||
*
|
||||
* @section UART_INTERFACE_SUMMARY Summary
|
||||
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
|
||||
* - Full-duplex UART communication
|
||||
* - Interrupt driven transmit/receive processing
|
||||
* - Callback function with returned event code
|
||||
* - Runtime baud-rate change
|
||||
* - Hardware resource locking during a transaction
|
||||
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
|
||||
*
|
||||
* Implemented by:
|
||||
* - @ref SCI_UART
|
||||
* - @ref SCI_B_UART
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_UART_API_H
|
||||
#define R_UART_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
#include "r_transfer_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** UART Event codes */
|
||||
typedef enum e_sf_event
|
||||
{
|
||||
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
|
||||
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
|
||||
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
|
||||
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
|
||||
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
|
||||
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
|
||||
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
|
||||
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
|
||||
} uart_event_t;
|
||||
|
||||
/** UART Data bit length definition */
|
||||
typedef enum e_uart_data_bits
|
||||
{
|
||||
UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit
|
||||
UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit
|
||||
UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit
|
||||
} uart_data_bits_t;
|
||||
|
||||
/** UART Parity definition */
|
||||
typedef enum e_uart_parity
|
||||
{
|
||||
UART_PARITY_OFF = 0U, ///< No parity
|
||||
UART_PARITY_EVEN = 2U, ///< Even parity
|
||||
UART_PARITY_ODD = 3U, ///< Odd parity
|
||||
} uart_parity_t;
|
||||
|
||||
/** UART Stop bits definition */
|
||||
typedef enum e_uart_stop_bits
|
||||
{
|
||||
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
|
||||
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
|
||||
} uart_stop_bits_t;
|
||||
|
||||
/** UART transaction definition */
|
||||
typedef enum e_uart_dir
|
||||
{
|
||||
UART_DIR_RX_TX = 3U, ///< Both RX and TX
|
||||
UART_DIR_RX = 1U, ///< Only RX
|
||||
UART_DIR_TX = 2U, ///< Only TX
|
||||
} uart_dir_t;
|
||||
|
||||
/** UART driver specific information */
|
||||
typedef struct st_uart_info
|
||||
{
|
||||
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
|
||||
uint32_t write_bytes_max;
|
||||
|
||||
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
|
||||
uint32_t read_bytes_max;
|
||||
} uart_info_t;
|
||||
|
||||
/** UART Callback parameter definition */
|
||||
typedef struct st_uart_callback_arg
|
||||
{
|
||||
uint32_t channel; ///< Device channel number
|
||||
uart_event_t event; ///< Event code
|
||||
|
||||
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
|
||||
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
|
||||
uint32_t data;
|
||||
void const * p_context; ///< Context provided to user during callback
|
||||
} uart_callback_args_t;
|
||||
|
||||
/** UART Configuration */
|
||||
typedef struct st_uart_cfg
|
||||
{
|
||||
/* UART generic configuration */
|
||||
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
|
||||
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
|
||||
uart_parity_t parity; ///< Parity type (none or odd or even)
|
||||
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
|
||||
uint8_t rxi_ipl; ///< Receive interrupt priority
|
||||
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
|
||||
uint8_t txi_ipl; ///< Transmit interrupt priority
|
||||
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
|
||||
uint8_t tei_ipl; ///< Transmit end interrupt priority
|
||||
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
|
||||
uint8_t eri_ipl; ///< Error interrupt priority
|
||||
IRQn_Type eri_irq; ///< Error interrupt IRQ number
|
||||
|
||||
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
|
||||
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
|
||||
transfer_instance_t const * p_transfer_rx;
|
||||
|
||||
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
|
||||
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
|
||||
transfer_instance_t const * p_transfer_tx;
|
||||
|
||||
/* Configuration for UART Event processing */
|
||||
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
|
||||
void const * p_context; ///< User defined context passed into callback function
|
||||
|
||||
/* Pointer to UART peripheral specific configuration */
|
||||
void const * p_extend; ///< UART hardware dependent configuration
|
||||
} uart_cfg_t;
|
||||
|
||||
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
|
||||
* @par Implemented as
|
||||
* - sci_uart_instance_ctrl_t
|
||||
*/
|
||||
typedef void uart_ctrl_t;
|
||||
|
||||
/** Shared Interface definition for UART */
|
||||
typedef struct st_uart_api
|
||||
{
|
||||
/** Open UART device.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_Open()
|
||||
* - @ref R_SCI_B_UART_Open()
|
||||
*
|
||||
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
|
||||
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
|
||||
* user.
|
||||
*/
|
||||
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
|
||||
|
||||
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
|
||||
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
|
||||
* the callback function with event UART_EVENT_RX_CHAR.
|
||||
* The maximum transfer size is reported by infoGet().
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_Read()
|
||||
* - @ref R_SCI_B_UART_Read()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block for the channel.
|
||||
* @param[in] p_dest Destination address to read data from.
|
||||
* @param[in] bytes Read data length.
|
||||
*/
|
||||
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
|
||||
|
||||
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
|
||||
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
|
||||
* the callback called with event UART_EVENT_TX_COMPLETE.
|
||||
* The maximum transfer size is reported by infoGet().
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_Write()
|
||||
* - @ref R_SCI_B_UART_Write()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] p_src Source address to write data to.
|
||||
* @param[in] bytes Write data length.
|
||||
*/
|
||||
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
|
||||
|
||||
/** Change baud rate.
|
||||
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
|
||||
* settings have been applied.
|
||||
*
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_BaudSet()
|
||||
* - @ref R_SCI_B_UART_BaudSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
|
||||
*/
|
||||
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
|
||||
|
||||
/** Get the driver specific information.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_InfoGet()
|
||||
* - @ref R_SCI_B_UART_InfoGet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] baudrate Baud rate in bps.
|
||||
*/
|
||||
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
|
||||
|
||||
/**
|
||||
* Abort ongoing transfer.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_Abort()
|
||||
* - @ref R_SCI_B_UART_Abort()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] communication_to_abort Type of abort request.
|
||||
*/
|
||||
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
|
||||
|
||||
/**
|
||||
* Specify callback function and optional context pointer and working memory pointer.
|
||||
* @par Implemented as
|
||||
* - R_SCI_Uart_CallbackSet()
|
||||
* - R_SCI_B_Uart_CallbackSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] p_callback Callback function
|
||||
* @param[in] p_context Pointer to send to callback function
|
||||
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||
* Callback arguments allocated here are only valid during the callback.
|
||||
*/
|
||||
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *),
|
||||
void const * const p_context, uart_callback_args_t * const p_callback_memory);
|
||||
|
||||
/** Close UART device.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_Close()
|
||||
* - @ref R_SCI_B_UART_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
*/
|
||||
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Stop ongoing read and return the number of bytes remaining in the read.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCI_UART_ReadStop()
|
||||
* - @ref R_SCI_B_UART_ReadStop()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
|
||||
*/
|
||||
fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
|
||||
} uart_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_uart_instance
|
||||
{
|
||||
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} uart_instance_t;
|
||||
|
||||
/** @} (end defgroup UART_API) */
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
364
bsp/renesas/ra2l1-cpk/ra/fsp/inc/fsp_common_api.h
Normal file
364
bsp/renesas/ra2l1-cpk/ra/fsp/inc/fsp_common_api.h
Normal file
@ -0,0 +1,364 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef FSP_COMMON_API_H
|
||||
#define FSP_COMMON_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* Includes FSP version macros. */
|
||||
#include "fsp_version.h"
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_COMMON
|
||||
* @defgroup RENESAS_ERROR_CODES Common Error Codes
|
||||
* All FSP modules share these common error codes.
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
|
||||
* about using this implementation is that it does not take any extra RAM or ROM. */
|
||||
|
||||
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
|
||||
|
||||
/** Determine if a C++ compiler is being used.
|
||||
* If so, ensure that standard C is used to process the API information. */
|
||||
#if defined(__cplusplus)
|
||||
#define FSP_CPP_HEADER extern "C" {
|
||||
#define FSP_CPP_FOOTER }
|
||||
#else
|
||||
#define FSP_CPP_HEADER
|
||||
#define FSP_CPP_FOOTER
|
||||
#endif
|
||||
|
||||
/** FSP Header and Footer definitions */
|
||||
#define FSP_HEADER FSP_CPP_HEADER
|
||||
#define FSP_FOOTER FSP_CPP_FOOTER
|
||||
|
||||
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
|
||||
* defined on the Secure side. */
|
||||
#define FSP_SECURE_ARGUMENT (NULL)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Common error codes */
|
||||
typedef enum e_fsp_err
|
||||
{
|
||||
FSP_SUCCESS = 0,
|
||||
|
||||
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
|
||||
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
|
||||
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
|
||||
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
|
||||
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
|
||||
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
|
||||
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
|
||||
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
|
||||
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
|
||||
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
|
||||
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
|
||||
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
|
||||
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
|
||||
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
|
||||
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
|
||||
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
|
||||
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
|
||||
FSP_ERR_ABORTED = 18, ///< An operation was aborted
|
||||
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
|
||||
FSP_ERR_TIMEOUT = 20, ///< Timeout error
|
||||
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
|
||||
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
|
||||
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
|
||||
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
|
||||
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
|
||||
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
|
||||
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
|
||||
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
|
||||
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
|
||||
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
|
||||
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
|
||||
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
|
||||
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
|
||||
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
|
||||
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
|
||||
FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed
|
||||
|
||||
/* Start of RTOS only error codes */
|
||||
FSP_ERR_INTERNAL = 100, ///< Internal error
|
||||
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
|
||||
|
||||
/* Start of UART specific */
|
||||
FSP_ERR_FRAMING = 200, ///< Framing error occurs
|
||||
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
|
||||
FSP_ERR_PARITY = 202, ///< Parity error occurs
|
||||
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
|
||||
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
|
||||
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
|
||||
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
|
||||
|
||||
/* Start of SPI specific */
|
||||
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
|
||||
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
|
||||
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
|
||||
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
|
||||
FSP_ERR_OVERRUN = 304, ///< Overrun error.
|
||||
|
||||
/* Start of CGC Specific */
|
||||
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
|
||||
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
|
||||
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
|
||||
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
|
||||
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
|
||||
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
|
||||
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
|
||||
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
|
||||
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
|
||||
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
|
||||
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
|
||||
|
||||
/* Start of FLASH Specific */
|
||||
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
|
||||
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
|
||||
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
|
||||
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
|
||||
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
|
||||
|
||||
/* Start of CAC Specific */
|
||||
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
|
||||
|
||||
/* Start of GLCD Specific */
|
||||
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
|
||||
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
|
||||
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
|
||||
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
|
||||
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
|
||||
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
|
||||
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
|
||||
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
|
||||
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
|
||||
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
|
||||
|
||||
/* Start of JPEG Specific */
|
||||
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
|
||||
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
|
||||
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
|
||||
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
|
||||
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
|
||||
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
|
||||
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
|
||||
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
|
||||
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
|
||||
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
|
||||
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
|
||||
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
|
||||
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
|
||||
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
|
||||
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
|
||||
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
|
||||
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
|
||||
|
||||
/* Start of touch panel framework specific */
|
||||
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
|
||||
|
||||
/* Start of IP specific */
|
||||
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
|
||||
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
|
||||
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
|
||||
|
||||
/* Start of USB specific */
|
||||
FSP_ERR_USB_FAILED = 1500,
|
||||
FSP_ERR_USB_BUSY = 1501,
|
||||
FSP_ERR_USB_SIZE_SHORT = 1502,
|
||||
FSP_ERR_USB_SIZE_OVER = 1503,
|
||||
FSP_ERR_USB_NOT_OPEN = 1504,
|
||||
FSP_ERR_USB_NOT_SUSPEND = 1505,
|
||||
FSP_ERR_USB_PARAMETER = 1506,
|
||||
|
||||
/* Start of Message framework specific */
|
||||
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
|
||||
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
|
||||
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
|
||||
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
|
||||
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
|
||||
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
|
||||
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
|
||||
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
|
||||
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
|
||||
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
|
||||
|
||||
/* Start of 2DG Driver specific */
|
||||
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
|
||||
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
|
||||
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
|
||||
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
|
||||
|
||||
/* Start of ETHER Driver specific */
|
||||
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
|
||||
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
|
||||
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
|
||||
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
|
||||
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
|
||||
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
|
||||
FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active.
|
||||
|
||||
/* Start of ETHER_PHY Driver specific */
|
||||
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
|
||||
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
|
||||
|
||||
/* Start of BYTEQ library specific */
|
||||
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
|
||||
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
|
||||
|
||||
/* Start of CTSU Driver specific */
|
||||
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
|
||||
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
|
||||
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
|
||||
FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet.
|
||||
FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed.
|
||||
FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed.
|
||||
FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed.
|
||||
FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed.
|
||||
FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed.
|
||||
FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed.
|
||||
FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed.
|
||||
FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed.
|
||||
FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed.
|
||||
FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed.
|
||||
FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed.
|
||||
FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed.
|
||||
FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed.
|
||||
FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed.
|
||||
|
||||
/* Start of SDMMC specific */
|
||||
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
|
||||
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
|
||||
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
|
||||
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
|
||||
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
|
||||
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
|
||||
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
|
||||
|
||||
/* Start of FX_IO specific */
|
||||
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
|
||||
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
|
||||
|
||||
/* Start of CAN specific */
|
||||
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
|
||||
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
|
||||
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
|
||||
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
|
||||
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
|
||||
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
|
||||
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
|
||||
FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full.
|
||||
|
||||
/* Start of SF_WIFI Specific */
|
||||
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
|
||||
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
|
||||
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
|
||||
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
|
||||
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
|
||||
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
|
||||
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
|
||||
|
||||
/* Start of SF_CELLULAR Specific */
|
||||
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
|
||||
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
|
||||
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
|
||||
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
|
||||
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
|
||||
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
|
||||
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
|
||||
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
|
||||
|
||||
/* Start of SF_BLE specific */
|
||||
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
|
||||
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
|
||||
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
|
||||
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
|
||||
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
|
||||
|
||||
/* Start of SF_BLE_ABS specific */
|
||||
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
|
||||
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
|
||||
|
||||
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
|
||||
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
|
||||
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
|
||||
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
|
||||
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
|
||||
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
|
||||
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
|
||||
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
|
||||
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
|
||||
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
|
||||
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
|
||||
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
|
||||
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
|
||||
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
|
||||
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
|
||||
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
|
||||
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
|
||||
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
|
||||
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
|
||||
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
|
||||
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed
|
||||
FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal.
|
||||
FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred.
|
||||
|
||||
/* Start of SF_CRYPTO specific */
|
||||
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
|
||||
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
|
||||
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
|
||||
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
|
||||
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
|
||||
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
|
||||
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
|
||||
|
||||
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
|
||||
* Refer to sf_cryoto_err.h for Crypto error codes.
|
||||
*/
|
||||
|
||||
/* Start of Sensor specific */
|
||||
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid.
|
||||
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing.
|
||||
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
|
||||
|
||||
/* Start of COMMS specific */
|
||||
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open.
|
||||
} fsp_err_t;
|
||||
|
||||
/** @} */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function prototypes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#endif
|
||||
294
bsp/renesas/ra2l1-cpk/ra/fsp/inc/fsp_features.h
Normal file
294
bsp/renesas/ra2l1-cpk/ra/fsp/inc/fsp_features.h
Normal file
@ -0,0 +1,294 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef FSP_FEATURES_H
|
||||
#define FSP_FEATURES_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* C99 includes. */
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
|
||||
/* Different compiler support. */
|
||||
#include "fsp_common_api.h"
|
||||
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup BSP_MCU
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Available modules. */
|
||||
typedef enum e_fsp_ip
|
||||
{
|
||||
FSP_IP_CFLASH = 0, ///< Code Flash
|
||||
FSP_IP_DFLASH = 1, ///< Data Flash
|
||||
FSP_IP_RAM = 2, ///< RAM
|
||||
FSP_IP_LVD = 3, ///< Low Voltage Detection
|
||||
FSP_IP_CGC = 3, ///< Clock Generation Circuit
|
||||
FSP_IP_LPM = 3, ///< Low Power Modes
|
||||
FSP_IP_FCU = 4, ///< Flash Control Unit
|
||||
FSP_IP_ICU = 6, ///< Interrupt Control Unit
|
||||
FSP_IP_DMAC = 7, ///< DMA Controller
|
||||
FSP_IP_DTC = 8, ///< Data Transfer Controller
|
||||
FSP_IP_IOPORT = 9, ///< I/O Ports
|
||||
FSP_IP_PFS = 10, ///< Pin Function Select
|
||||
FSP_IP_ELC = 11, ///< Event Link Controller
|
||||
FSP_IP_MPU = 13, ///< Memory Protection Unit
|
||||
FSP_IP_MSTP = 14, ///< Module Stop
|
||||
FSP_IP_MMF = 15, ///< Memory Mirror Function
|
||||
FSP_IP_KEY = 16, ///< Key Interrupt Function
|
||||
FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit
|
||||
FSP_IP_DOC = 18, ///< Data Operation Circuit
|
||||
FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator
|
||||
FSP_IP_SCI = 20, ///< Serial Communications Interface
|
||||
FSP_IP_IIC = 21, ///< I2C Bus Interface
|
||||
FSP_IP_SPI = 22, ///< Serial Peripheral Interface
|
||||
FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit
|
||||
FSP_IP_SCE = 24, ///< Secure Cryptographic Engine
|
||||
FSP_IP_SLCDC = 25, ///< Segment LCD Controller
|
||||
FSP_IP_AES = 26, ///< Advanced Encryption Standard
|
||||
FSP_IP_TRNG = 27, ///< True Random Number Generator
|
||||
FSP_IP_FCACHE = 30, ///< Flash Cache
|
||||
FSP_IP_SRAM = 31, ///< SRAM
|
||||
FSP_IP_ADC = 32, ///< A/D Converter
|
||||
FSP_IP_DAC = 33, ///< 12-Bit D/A Converter
|
||||
FSP_IP_TSN = 34, ///< Temperature Sensor
|
||||
FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit
|
||||
FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator
|
||||
FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator
|
||||
FSP_IP_OPAMP = 38, ///< Operational Amplifier
|
||||
FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter
|
||||
FSP_IP_RTC = 40, ///< Real Time Clock
|
||||
FSP_IP_WDT = 41, ///< Watch Dog Timer
|
||||
FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer
|
||||
FSP_IP_GPT = 43, ///< General PWM Timer
|
||||
FSP_IP_POEG = 44, ///< Port Output Enable for GPT
|
||||
FSP_IP_OPS = 45, ///< Output Phase Switch
|
||||
FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer
|
||||
FSP_IP_CAN = 48, ///< Controller Area Network
|
||||
FSP_IP_IRDA = 49, ///< Infrared Data Association
|
||||
FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface
|
||||
FSP_IP_USBFS = 51, ///< USB Full Speed
|
||||
FSP_IP_SDHI = 52, ///< SD/MMC Host Interface
|
||||
FSP_IP_SRC = 53, ///< Sampling Rate Converter
|
||||
FSP_IP_SSI = 54, ///< Serial Sound Interface
|
||||
FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface
|
||||
FSP_IP_ETHER = 64, ///< Ethernet MAC Controller
|
||||
FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller
|
||||
FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller
|
||||
FSP_IP_PDC = 66, ///< Parallel Data Capture Unit
|
||||
FSP_IP_GLCDC = 67, ///< Graphics LCD Controller
|
||||
FSP_IP_DRW = 68, ///< 2D Drawing Engine
|
||||
FSP_IP_JPEG = 69, ///< JPEG
|
||||
FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter
|
||||
FSP_IP_USBHS = 71, ///< USB High Speed
|
||||
FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface
|
||||
FSP_IP_CEC = 73, ///< HDMI CEC
|
||||
FSP_IP_TFU = 74, ///< Trigonometric Function Unit
|
||||
FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
|
||||
FSP_IP_CANFD = 76, ///< CAN-FD
|
||||
} fsp_ip_t;
|
||||
|
||||
/** Signals that can be mapped to an interrupt. */
|
||||
typedef enum e_fsp_signal
|
||||
{
|
||||
FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH
|
||||
FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH
|
||||
FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END
|
||||
FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B
|
||||
FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A
|
||||
FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B
|
||||
FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ
|
||||
FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ
|
||||
FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A
|
||||
FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B
|
||||
FSP_SIGNAL_AGT_INT, ///< AGT INT
|
||||
FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR
|
||||
FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END
|
||||
FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW
|
||||
FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR
|
||||
FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX
|
||||
FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX
|
||||
FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX
|
||||
FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX
|
||||
FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP
|
||||
FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST
|
||||
FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1
|
||||
FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2
|
||||
FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD
|
||||
FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT
|
||||
FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT
|
||||
FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT
|
||||
FSP_SIGNAL_CTSU_END = 0, ///< CTSU END
|
||||
FSP_SIGNAL_CTSU_READ, ///< CTSU READ
|
||||
FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE
|
||||
FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI
|
||||
FSP_SIGNAL_DALI_CLI, ///< DALI CLI
|
||||
FSP_SIGNAL_DALI_SDI, ///< DALI SDI
|
||||
FSP_SIGNAL_DALI_BPI, ///< DALI BPI
|
||||
FSP_SIGNAL_DALI_FEI, ///< DALI FEI
|
||||
FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI
|
||||
FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT
|
||||
FSP_SIGNAL_DOC_INT = 0, ///< DOC INT
|
||||
FSP_SIGNAL_DRW_INT = 0, ///< DRW INT
|
||||
FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE
|
||||
FSP_SIGNAL_DTC_END, ///< DTC END
|
||||
FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT
|
||||
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0
|
||||
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1
|
||||
FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS
|
||||
FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT
|
||||
FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT
|
||||
FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL
|
||||
FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE
|
||||
FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL
|
||||
FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE
|
||||
FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL
|
||||
FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE
|
||||
FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL
|
||||
FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE
|
||||
FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL
|
||||
FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE
|
||||
FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL
|
||||
FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE
|
||||
FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR
|
||||
FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI
|
||||
FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT
|
||||
FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1
|
||||
FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2
|
||||
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A
|
||||
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B
|
||||
FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C
|
||||
FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D
|
||||
FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E
|
||||
FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F
|
||||
FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW
|
||||
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW
|
||||
FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A
|
||||
FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B
|
||||
FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE
|
||||
FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0
|
||||
FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1
|
||||
FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2
|
||||
FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3
|
||||
FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4
|
||||
FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5
|
||||
FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6
|
||||
FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7
|
||||
FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8
|
||||
FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9
|
||||
FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10
|
||||
FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11
|
||||
FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12
|
||||
FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13
|
||||
FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14
|
||||
FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15
|
||||
FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL
|
||||
FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI
|
||||
FSP_SIGNAL_IIC_RXI, ///< IIC RXI
|
||||
FSP_SIGNAL_IIC_TEI, ///< IIC TEI
|
||||
FSP_SIGNAL_IIC_TXI, ///< IIC TXI
|
||||
FSP_SIGNAL_IIC_WUI, ///< IIC WUI
|
||||
FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1
|
||||
FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2
|
||||
FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3
|
||||
FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4
|
||||
FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B
|
||||
FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C
|
||||
FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D
|
||||
FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E
|
||||
FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW
|
||||
FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI
|
||||
FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI
|
||||
FSP_SIGNAL_KEY_INT = 0, ///< KEY INT
|
||||
FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END
|
||||
FSP_SIGNAL_PDC_INT, ///< PDC INT
|
||||
FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY
|
||||
FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT
|
||||
FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT
|
||||
FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM
|
||||
FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD
|
||||
FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY
|
||||
FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY
|
||||
FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY
|
||||
FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG
|
||||
FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY
|
||||
FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0
|
||||
FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1
|
||||
FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK
|
||||
FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY
|
||||
FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0
|
||||
FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1
|
||||
FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4
|
||||
FSP_SIGNAL_SCI_AM = 0, ///< SCI AM
|
||||
FSP_SIGNAL_SCI_ERI, ///< SCI ERI
|
||||
FSP_SIGNAL_SCI_RXI, ///< SCI RXI
|
||||
FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI
|
||||
FSP_SIGNAL_SCI_TEI, ///< SCI TEI
|
||||
FSP_SIGNAL_SCI_TXI, ///< SCI TXI
|
||||
FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI
|
||||
FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND
|
||||
FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND
|
||||
FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS
|
||||
FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD
|
||||
FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ
|
||||
FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO
|
||||
FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI
|
||||
FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE
|
||||
FSP_SIGNAL_SPI_RXI, ///< SPI RXI
|
||||
FSP_SIGNAL_SPI_TEI, ///< SPI TEI
|
||||
FSP_SIGNAL_SPI_TXI, ///< SPI TXI
|
||||
FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END
|
||||
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY
|
||||
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL
|
||||
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW
|
||||
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW
|
||||
FSP_SIGNAL_SSI_INT = 0, ///< SSI INT
|
||||
FSP_SIGNAL_SSI_RXI, ///< SSI RXI
|
||||
FSP_SIGNAL_SSI_TXI, ///< SSI TXI
|
||||
FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI
|
||||
FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ
|
||||
FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0
|
||||
FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1
|
||||
FSP_SIGNAL_USB_INT, ///< USB INT
|
||||
FSP_SIGNAL_USB_RESUME, ///< USB RESUME
|
||||
FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
|
||||
FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
|
||||
} fsp_signal_t;
|
||||
|
||||
typedef void (* fsp_vector_t)(void);
|
||||
|
||||
/** @} (end addtogroup BSP_MCU) */
|
||||
|
||||
#endif
|
||||
80
bsp/renesas/ra2l1-cpk/ra/fsp/inc/fsp_version.h
Normal file
80
bsp/renesas/ra2l1-cpk/ra/fsp/inc/fsp_version.h
Normal file
@ -0,0 +1,80 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef FSP_VERSION_H
|
||||
#define FSP_VERSION_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup RENESAS_COMMON
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** FSP pack major version. */
|
||||
#define FSP_VERSION_MAJOR (3U)
|
||||
|
||||
/** FSP pack minor version. */
|
||||
#define FSP_VERSION_MINOR (5U)
|
||||
|
||||
/** FSP pack patch version. */
|
||||
#define FSP_VERSION_PATCH (0U)
|
||||
|
||||
/** FSP pack version build number (currently unused). */
|
||||
#define FSP_VERSION_BUILD (0U)
|
||||
|
||||
/** Public FSP version name. */
|
||||
#define FSP_VERSION_STRING ("3.5.0")
|
||||
|
||||
/** Unique FSP version ID. */
|
||||
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.5.0")
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** FSP Pack version structure */
|
||||
typedef union st_fsp_pack_version
|
||||
{
|
||||
/** Version id */
|
||||
uint32_t version_id;
|
||||
|
||||
/** Code version parameters, little endian order. */
|
||||
struct
|
||||
{
|
||||
uint8_t build; ///< Build version of FSP Pack
|
||||
uint8_t patch; ///< Patch version of FSP Pack
|
||||
uint8_t minor; ///< Minor version of FSP Pack
|
||||
uint8_t major; ///< Major version of FSP Pack
|
||||
};
|
||||
} fsp_pack_version_t;
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
95
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h
Normal file
95
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h
Normal file
@ -0,0 +1,95 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup ICU
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_ICU_H
|
||||
#define R_ICU_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
#include "r_external_irq_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */
|
||||
typedef struct st_icu_instance_ctrl
|
||||
{
|
||||
uint32_t open; ///< Used to determine if channel control block is in use
|
||||
IRQn_Type irq; ///< NVIC interrupt number
|
||||
uint8_t channel; ///< Channel
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
|
||||
#endif
|
||||
void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin.
|
||||
|
||||
/** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */
|
||||
void const * p_context;
|
||||
} icu_instance_ctrl_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const external_irq_api_t g_external_irq_on_icu;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Public APIs
|
||||
**********************************************************************************************************************/
|
||||
fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg);
|
||||
|
||||
fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl);
|
||||
|
||||
fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl);
|
||||
|
||||
fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl,
|
||||
void ( * p_callback)(external_irq_callback_args_t *),
|
||||
void const * const p_context,
|
||||
external_irq_callback_args_t * const p_callback_memory);
|
||||
|
||||
fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup ICU)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif // R_ICU_H
|
||||
359
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_ioport.h
Normal file
359
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_ioport.h
Normal file
@ -0,0 +1,359 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup IOPORT
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_IOPORT_H
|
||||
#define R_IOPORT_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#include "r_ioport_api.h"
|
||||
#include "r_ioport_cfg.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
|
||||
typedef struct st_ioport_instance_ctrl
|
||||
{
|
||||
uint32_t open;
|
||||
void const * p_context;
|
||||
} ioport_instance_ctrl_t;
|
||||
|
||||
/* This typedef is here temporarily. See SWFLEX-144 for details. */
|
||||
/** Superset list of all possible IO port pins. */
|
||||
typedef enum e_ioport_port_pin_t
|
||||
{
|
||||
IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
|
||||
IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
|
||||
IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2
|
||||
IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3
|
||||
IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4
|
||||
IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5
|
||||
IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6
|
||||
IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7
|
||||
IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8
|
||||
IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9
|
||||
IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10
|
||||
IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11
|
||||
IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12
|
||||
IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13
|
||||
IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14
|
||||
IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15
|
||||
|
||||
IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
|
||||
IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
|
||||
IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2
|
||||
IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3
|
||||
IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4
|
||||
IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5
|
||||
IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6
|
||||
IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7
|
||||
IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8
|
||||
IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9
|
||||
IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10
|
||||
IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11
|
||||
IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12
|
||||
IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13
|
||||
IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14
|
||||
IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15
|
||||
|
||||
IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
|
||||
IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
|
||||
IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2
|
||||
IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3
|
||||
IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4
|
||||
IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5
|
||||
IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6
|
||||
IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7
|
||||
IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8
|
||||
IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9
|
||||
IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10
|
||||
IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11
|
||||
IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12
|
||||
IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13
|
||||
IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14
|
||||
IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15
|
||||
|
||||
IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
|
||||
IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
|
||||
IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2
|
||||
IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3
|
||||
IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4
|
||||
IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5
|
||||
IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6
|
||||
IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7
|
||||
IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8
|
||||
IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9
|
||||
IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10
|
||||
IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11
|
||||
IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12
|
||||
IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13
|
||||
IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14
|
||||
IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15
|
||||
|
||||
IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
|
||||
IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
|
||||
IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2
|
||||
IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3
|
||||
IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4
|
||||
IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5
|
||||
IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6
|
||||
IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7
|
||||
IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8
|
||||
IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9
|
||||
IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10
|
||||
IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11
|
||||
IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12
|
||||
IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13
|
||||
IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14
|
||||
IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15
|
||||
|
||||
IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
|
||||
IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
|
||||
IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
|
||||
IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3
|
||||
IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4
|
||||
IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5
|
||||
IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6
|
||||
IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7
|
||||
IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8
|
||||
IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9
|
||||
IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10
|
||||
IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11
|
||||
IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12
|
||||
IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13
|
||||
IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14
|
||||
IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15
|
||||
|
||||
IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
|
||||
IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
|
||||
IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2
|
||||
IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3
|
||||
IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4
|
||||
IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5
|
||||
IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6
|
||||
IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7
|
||||
IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8
|
||||
IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9
|
||||
IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10
|
||||
IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11
|
||||
IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12
|
||||
IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13
|
||||
IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14
|
||||
IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15
|
||||
|
||||
IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
|
||||
IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
|
||||
IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
|
||||
IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3
|
||||
IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4
|
||||
IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5
|
||||
IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6
|
||||
IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7
|
||||
IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8
|
||||
IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9
|
||||
IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10
|
||||
IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11
|
||||
IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12
|
||||
IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13
|
||||
IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14
|
||||
IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15
|
||||
|
||||
IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
|
||||
IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
|
||||
IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
|
||||
IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3
|
||||
IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4
|
||||
IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5
|
||||
IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6
|
||||
IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7
|
||||
IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8
|
||||
IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9
|
||||
IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10
|
||||
IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11
|
||||
IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12
|
||||
IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13
|
||||
IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14
|
||||
IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15
|
||||
|
||||
IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
|
||||
IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
|
||||
IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2
|
||||
IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3
|
||||
IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4
|
||||
IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5
|
||||
IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6
|
||||
IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7
|
||||
IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8
|
||||
IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9
|
||||
IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10
|
||||
IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11
|
||||
IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12
|
||||
IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13
|
||||
IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14
|
||||
IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15
|
||||
|
||||
IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
|
||||
IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
|
||||
IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2
|
||||
IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3
|
||||
IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4
|
||||
IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5
|
||||
IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6
|
||||
IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7
|
||||
IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8
|
||||
IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9
|
||||
IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10
|
||||
IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11
|
||||
IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12
|
||||
IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13
|
||||
IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14
|
||||
IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15
|
||||
|
||||
IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
|
||||
IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
|
||||
IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2
|
||||
IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3
|
||||
IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4
|
||||
IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5
|
||||
IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6
|
||||
IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7
|
||||
IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8
|
||||
IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9
|
||||
IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10
|
||||
IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11
|
||||
IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12
|
||||
IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
|
||||
IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
|
||||
IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
|
||||
|
||||
IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
|
||||
IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
|
||||
IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2
|
||||
IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3
|
||||
IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4
|
||||
IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5
|
||||
IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6
|
||||
IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7
|
||||
IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8
|
||||
IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9
|
||||
IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10
|
||||
IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11
|
||||
IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12
|
||||
IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13
|
||||
IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14
|
||||
IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15
|
||||
|
||||
IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
|
||||
IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
|
||||
IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
|
||||
IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3
|
||||
IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4
|
||||
IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5
|
||||
IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6
|
||||
IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7
|
||||
IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8
|
||||
IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9
|
||||
IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10
|
||||
IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11
|
||||
IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12
|
||||
IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13
|
||||
IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14
|
||||
IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15
|
||||
|
||||
IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
|
||||
IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
|
||||
IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2
|
||||
IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3
|
||||
IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4
|
||||
IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5
|
||||
IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6
|
||||
IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7
|
||||
IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8
|
||||
IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9
|
||||
IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10
|
||||
IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11
|
||||
IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12
|
||||
IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13
|
||||
IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14
|
||||
IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15
|
||||
} ioport_port_pin_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const ioport_api_t g_ioport_on_ioport;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Public APIs
|
||||
**********************************************************************************************************************/
|
||||
|
||||
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
|
||||
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
|
||||
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
|
||||
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
|
||||
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
|
||||
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
|
||||
bsp_io_port_t port,
|
||||
ioport_size_t direction_values,
|
||||
ioport_size_t mask);
|
||||
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
|
||||
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
|
||||
bsp_io_port_t port,
|
||||
ioport_size_t event_data,
|
||||
ioport_size_t mask_value);
|
||||
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
|
||||
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
|
||||
fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl,
|
||||
ioport_ethernet_channel_t channel,
|
||||
ioport_ethernet_mode_t mode);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup IOPORT)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif // R_IOPORT_H
|
||||
192
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_sci_uart.h
Normal file
192
bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_sci_uart.h
Normal file
@ -0,0 +1,192 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_SCI_UART_H
|
||||
#define R_SCI_UART_H
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup SCI_UART
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
#include "r_uart_api.h"
|
||||
#include "r_sci_uart_cfg.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Enumeration for SCI clock source */
|
||||
typedef enum e_sci_clk_src
|
||||
{
|
||||
SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation
|
||||
SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
|
||||
SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
|
||||
SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
|
||||
} sci_clk_src_t;
|
||||
|
||||
/** UART flow control mode definition */
|
||||
typedef enum e_sci_uart_flow_control
|
||||
{
|
||||
SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use SCI pin for RTS
|
||||
SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use SCI pin for CTS
|
||||
SCI_UART_FLOW_CONTROL_CTSRTS = 3U, ///< Use SCI pin for CTS, external pin for RTS
|
||||
SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 8U, ///< Use CTSn_RTSn pin for RTS and CTSn pin for CTS. Available only for some channels on selected MCUs. See hardware manual for channel specific options
|
||||
} sci_uart_flow_control_t;
|
||||
|
||||
/** UART instance control block. */
|
||||
typedef struct st_sci_uart_instance_ctrl
|
||||
{
|
||||
/* Parameters to control UART peripheral device */
|
||||
uint8_t fifo_depth; // FIFO depth of the UART channel
|
||||
uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise
|
||||
uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
|
||||
uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise
|
||||
uint32_t open; // Used to determine if the channel is configured
|
||||
|
||||
bsp_io_port_pin_t flow_pin;
|
||||
|
||||
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
|
||||
uint8_t const * p_tx_src;
|
||||
|
||||
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
|
||||
uint32_t tx_src_bytes;
|
||||
|
||||
/* Destination buffer pointer used for receiving data. */
|
||||
uint8_t const * p_rx_dest;
|
||||
|
||||
/* Size of destination buffer pointer used for receiving data. */
|
||||
uint32_t rx_dest_bytes;
|
||||
|
||||
/* Pointer to the configuration block. */
|
||||
uart_cfg_t const * p_cfg;
|
||||
|
||||
/* Base register for this channel */
|
||||
R_SCI0_Type * p_reg;
|
||||
|
||||
void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
|
||||
uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
|
||||
|
||||
/* Pointer to context to be passed into callback function */
|
||||
void const * p_context;
|
||||
} sci_uart_instance_ctrl_t;
|
||||
|
||||
/** Receive FIFO trigger configuration. */
|
||||
typedef enum e_sci_uart_rx_fifo_trigger
|
||||
{
|
||||
SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering
|
||||
SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
|
||||
} sci_uart_rx_fifo_trigger_t;
|
||||
|
||||
/** Asynchronous Start Bit Edge Detection configuration. */
|
||||
typedef enum e_sci_uart_start_bit_detect
|
||||
{
|
||||
SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
|
||||
SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
|
||||
} sci_uart_start_bit_detect_t;
|
||||
|
||||
/** Noise cancellation configuration. */
|
||||
typedef enum e_sci_uart_noise_cancellation
|
||||
{
|
||||
SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation
|
||||
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation
|
||||
} sci_uart_noise_cancellation_t;
|
||||
|
||||
/** Register settings to acheive a desired baud rate and modulation duty. */
|
||||
typedef struct st_baud_setting_t
|
||||
{
|
||||
union
|
||||
{
|
||||
uint8_t semr_baudrate_bits;
|
||||
|
||||
struct
|
||||
{
|
||||
uint8_t : 2;
|
||||
uint8_t brme : 1; ///< Bit Rate Modulation Enable
|
||||
uint8_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1
|
||||
uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select
|
||||
uint8_t : 1;
|
||||
uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
|
||||
uint8_t : 1;
|
||||
};
|
||||
};
|
||||
uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
|
||||
uint8_t brr; ///< Bit Rate Register setting
|
||||
uint8_t mddr; ///< Modulation Duty Register setting
|
||||
} baud_setting_t;
|
||||
|
||||
/** UART on SCI device Configuration */
|
||||
typedef struct st_sci_uart_extended_cfg
|
||||
{
|
||||
sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
|
||||
sci_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge
|
||||
sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
|
||||
baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
|
||||
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used.
|
||||
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
|
||||
sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin
|
||||
} sci_uart_extended_cfg_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const uart_api_t g_uart_on_sci;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
|
||||
fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
|
||||
fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
|
||||
fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
|
||||
fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
|
||||
fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl);
|
||||
fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
|
||||
fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate,
|
||||
bool bitrate_modulation,
|
||||
uint32_t baud_rate_error_x_1000,
|
||||
baud_setting_t * const p_baud_setting);
|
||||
fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
|
||||
void ( * p_callback)(uart_callback_args_t *),
|
||||
void const * const p_context,
|
||||
uart_callback_args_t * const p_callback_memory);
|
||||
fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end addtogroup SCI_UART)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,623 @@
|
||||
#ifndef __BASE_ADDRESSES_H
|
||||
#define __BASE_ADDRESSES_H
|
||||
|
||||
#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers)
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ Device Specific Peripheral Address Map ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/** @addtogroup Device_Peripheral_peripheralAddr
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define R_ACMPHS0_BASE 0x400F4000
|
||||
#define R_ACMPHS1_BASE 0x400F4100
|
||||
#define R_ACMPHS2_BASE 0x400F4200
|
||||
#define R_ACMPHS3_BASE 0x400F4300
|
||||
#define R_MPU_BASE 0x40000000
|
||||
#define R_TZF_BASE 0x40000E00
|
||||
#define R_SRAM_BASE 0x40002000
|
||||
#define R_BUS_BASE 0x40003000
|
||||
#define R_DMAC0_BASE 0x40005000
|
||||
#define R_DMAC1_BASE 0x40005040
|
||||
#define R_DMAC2_BASE 0x40005080
|
||||
#define R_DMAC3_BASE 0x400050C0
|
||||
#define R_DMAC4_BASE 0x40005100
|
||||
#define R_DMAC5_BASE 0x40005140
|
||||
#define R_DMAC6_BASE 0x40005180
|
||||
#define R_DMAC7_BASE 0x400051C0
|
||||
#define R_DMA_BASE 0x40005200
|
||||
#define R_DTC_BASE 0x40005400
|
||||
#define R_ICU_BASE 0x40006000
|
||||
#define R_CACHE_BASE 0x40007000
|
||||
#define R_CPSCU_BASE 0x40008000
|
||||
#define R_DBG_BASE 0x4001B000
|
||||
#define R_FCACHE_BASE 0x4001C000
|
||||
#define R_SYSC_BASE 0x4001E000
|
||||
#define R_TSN_CAL_BASE 0x407FB17C
|
||||
#define R_TSN_CTRL_BASE 0x400F3000
|
||||
#define R_ELC_BASE 0x40082000
|
||||
#define R_TC_BASE 0x40083000
|
||||
#define R_IWDT_BASE 0x40083200
|
||||
#define R_WDT_BASE 0x40083400
|
||||
#define R_CAC_BASE 0x40083600
|
||||
#define R_MSTP_BASE 0x40084000
|
||||
#define R_KINT_BASE 0x40085000
|
||||
#define R_POEG_BASE 0x4008A000
|
||||
#define R_USB_FS0_BASE 0x40090000
|
||||
#define R_USB_HS0_BASE 0x40111000
|
||||
#define R_SDHI0_BASE 0x40092000
|
||||
#define R_SSI0_BASE 0x4009D000
|
||||
#define R_IIC0_BASE 0x4009F000
|
||||
#define R_IIC0WU_BASE 0x4009F014
|
||||
#define R_IIC1_BASE 0x4009F100
|
||||
#define R_OSPI_BASE 0x400A6000
|
||||
#define R_CAN0_BASE 0x400A8000
|
||||
#define R_CAN1_BASE 0x400A9000
|
||||
#define R_CEC_BASE 0x400AC000
|
||||
#define R_CANFD_BASE 0x400B0000
|
||||
#define R_CTSU_BASE 0x400D0000
|
||||
#define R_PSCU_BASE 0x400E0000
|
||||
#define R_AGT0_BASE 0x400E8000
|
||||
#define R_AGT1_BASE 0x400E8100
|
||||
#define R_AGT2_BASE 0x400E8200
|
||||
#define R_AGT3_BASE 0x400E8300
|
||||
#define R_AGT4_BASE 0x400E8400
|
||||
#define R_AGT5_BASE 0x400E8500
|
||||
#define R_AGTW0_BASE 0x400E8000
|
||||
#define R_AGTW1_BASE 0x400E8100
|
||||
#define R_TSN_CTRL_BASE 0x400F3000
|
||||
#define R_CRC_BASE 0x40108000
|
||||
#define R_DOC_BASE 0x40109000
|
||||
#define R_ETHERC_EDMAC_BASE 0x40114000
|
||||
#define R_ETHERC0_BASE 0x40114100
|
||||
#define R_SCI0_BASE 0x40118000
|
||||
#define R_SCI1_BASE 0x40118100
|
||||
#define R_SCI2_BASE 0x40118200
|
||||
#define R_SCI3_BASE 0x40118300
|
||||
#define R_SCI4_BASE 0x40118400
|
||||
#define R_SCI5_BASE 0x40118500
|
||||
#define R_SCI6_BASE 0x40118600
|
||||
#define R_SCI7_BASE 0x40118700
|
||||
#define R_SCI8_BASE 0x40118800
|
||||
#define R_SCI9_BASE 0x40118900
|
||||
#define R_SPI0_BASE 0x4011A000
|
||||
#define R_SPI1_BASE 0x4011A100
|
||||
#define R_SPI_B0_BASE 0x4011A000
|
||||
#define R_SPI_B1_BASE 0x4011A100
|
||||
#define R_GPT320_BASE 0x40169000
|
||||
#define R_GPT321_BASE 0x40169100
|
||||
#define R_GPT322_BASE 0x40169200
|
||||
#define R_GPT323_BASE 0x40169300
|
||||
#define R_GPT164_BASE 0x40169400
|
||||
#define R_GPT165_BASE 0x40169500
|
||||
#define R_GPT166_BASE 0x40169600
|
||||
#define R_GPT167_BASE 0x40169700
|
||||
#define R_GPT168_BASE 0x40169800
|
||||
#define R_GPT169_BASE 0x40169900
|
||||
#define R_GPT_OPS_BASE 0x40169A00
|
||||
#define R_GPT_ODC_BASE 0x4016A000
|
||||
#define R_GPT_GTCLK_BASE 0x40169B00
|
||||
#define R_ADC120_BASE 0x40170000
|
||||
#define R_ADC121_BASE 0x40170200
|
||||
|
||||
/* Not included in SVD */
|
||||
#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
|
||||
#define R_DAC120_BASE 0x40172000
|
||||
#define R_DAC121_BASE 0x40172100
|
||||
#else
|
||||
#define R_DAC12_BASE 0x40171000
|
||||
#endif
|
||||
#define R_FLAD_BASE 0x407FC000
|
||||
#define R_FACI_HP_CMD_BASE 0x407E0000
|
||||
#define R_FACI_HP_BASE 0x407FE000
|
||||
#define R_QSPI_BASE 0x64000000
|
||||
#define R_TFU_BASE 0x40021000
|
||||
|
||||
/* Not included in SVD */
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
#define R_PORT0_BASE 0x4001F000
|
||||
#define R_PORT1_BASE 0x4001F020
|
||||
#define R_PORT2_BASE 0x4001F040
|
||||
#define R_PORT10_BASE 0x4001F140
|
||||
#define R_PORT11_BASE 0x4001F160
|
||||
#define R_PORT12_BASE 0x4001F180
|
||||
#define R_PORT13_BASE 0x4001F1A0
|
||||
#define R_PORT14_BASE 0x4001F1C0
|
||||
#define R_PFS_BASE 0x4001F800
|
||||
#define R_PMISC_BASE 0x4001FD00
|
||||
#else
|
||||
#define R_PORT0_BASE 0x40080000
|
||||
#define R_PORT1_BASE 0x40080020
|
||||
#define R_PORT2_BASE 0x40080040
|
||||
#define R_PORT3_BASE 0x40080060
|
||||
#define R_PORT4_BASE 0x40080080
|
||||
#define R_PORT5_BASE 0x400800A0
|
||||
#define R_PORT6_BASE 0x400800C0
|
||||
#define R_PORT7_BASE 0x400800E0
|
||||
#define R_PORT8_BASE 0x40080100
|
||||
#define R_PORT9_BASE 0x40080120
|
||||
#define R_PORT10_BASE 0x40080140
|
||||
#define R_PORT11_BASE 0x40080160
|
||||
#define R_PFS_BASE 0x40080800
|
||||
#define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this
|
||||
#endif
|
||||
#define R_GPT_POEG0_BASE 0x4008A000
|
||||
#define R_GPT_POEG1_BASE 0x4008A100
|
||||
#define R_GPT_POEG2_BASE 0x4008A200
|
||||
#define R_GPT_POEG3_BASE 0x4008A300
|
||||
|
||||
#define R_RTC_BASE 0x40083000
|
||||
|
||||
#define R_I3C0_BASE 0x4011F000
|
||||
#define R_I3C1_BASE 0x4011F400
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/** @addtogroup Device_Peripheral_declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
// #define R_MPU ((R_MPU_Type *) R_MPU_BASE)
|
||||
#define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
|
||||
#define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
|
||||
#define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
|
||||
#define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
|
||||
#define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
|
||||
#define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
|
||||
#define R_TZF ((R_TZF_Type *) R_TZF_BASE)
|
||||
#define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
|
||||
#define R_BUS ((R_BUS_B_Type *) R_BUS_BASE)
|
||||
#define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
|
||||
#define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
|
||||
#define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
|
||||
#define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
|
||||
#define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
|
||||
#define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
|
||||
#define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
|
||||
#define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
|
||||
#define R_DMA ((R_DMA_Type *) R_DMA_BASE)
|
||||
#define R_DTC ((R_DTC_Type *) R_DTC_BASE)
|
||||
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
|
||||
#define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
|
||||
#define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
|
||||
#define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE)
|
||||
#define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
|
||||
#define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE)
|
||||
#define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
|
||||
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
|
||||
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
|
||||
#define R_ELC ((R_ELC_Type *) R_ELC_BASE)
|
||||
#define R_TC ((R_TC_Type *) R_TC_BASE)
|
||||
#define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
|
||||
#define R_KINT ((R_KINT_Type *) R_KINT_BASE)
|
||||
#define R_WDT ((R_WDT_Type *) R_WDT_BASE)
|
||||
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
|
||||
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
|
||||
#define R_POEG ((R_POEG_Type *) R_POEG_BASE)
|
||||
#define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
|
||||
#define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
|
||||
#define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
|
||||
#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
|
||||
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
|
||||
#define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE)
|
||||
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
|
||||
#define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
|
||||
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
|
||||
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
|
||||
#define R_CEC ((R_CEC_Type *) R_CEC_BASE)
|
||||
#if BSP_FEATURE_CANFD_LITE
|
||||
#define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE)
|
||||
#else
|
||||
#define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
|
||||
#endif
|
||||
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
|
||||
#define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
|
||||
#if BSP_FEATURE_AGT_HAS_AGTW
|
||||
#define R_AGT0 ((R_AGTW0_Type *) R_AGT0_BASE)
|
||||
#define R_AGT1 ((R_AGTW0_Type *) R_AGT1_BASE)
|
||||
#define R_AGT2 ((R_AGTW0_Type *) R_AGT2_BASE)
|
||||
#define R_AGT3 ((R_AGTW0_Type *) R_AGT3_BASE)
|
||||
#define R_AGT4 ((R_AGTW0_Type *) R_AGT4_BASE)
|
||||
#define R_AGT5 ((R_AGTW0_Type *) R_AGT5_BASE)
|
||||
#else
|
||||
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
|
||||
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
|
||||
#define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE)
|
||||
#define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE)
|
||||
#define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE)
|
||||
#define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE)
|
||||
#endif
|
||||
#define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
|
||||
#define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
|
||||
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
|
||||
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
|
||||
#if (2U == BSP_FEATURE_DOC_VERSION)
|
||||
#define R_DOC_B ((R_DOC_B_Type *) R_DOC_BASE)
|
||||
#else
|
||||
#define R_DOC ((R_DOC_Type *) R_DOC_BASE)
|
||||
#endif
|
||||
#define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
|
||||
#define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
|
||||
#if (2U == BSP_FEATURE_SCI_VERSION)
|
||||
#define R_SCI0 ((R_SCI_B0_Type *) R_SCI0_BASE)
|
||||
#define R_SCI1 ((R_SCI_B0_Type *) R_SCI1_BASE)
|
||||
#define R_SCI2 ((R_SCI_B0_Type *) R_SCI2_BASE)
|
||||
#define R_SCI3 ((R_SCI_B0_Type *) R_SCI3_BASE)
|
||||
#define R_SCI4 ((R_SCI_B0_Type *) R_SCI4_BASE)
|
||||
#define R_SCI9 ((R_SCI_B0_Type *) R_SCI9_BASE)
|
||||
#else
|
||||
#define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
|
||||
#define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
|
||||
#define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
|
||||
#define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
|
||||
#define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
|
||||
#define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
|
||||
#define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
|
||||
#define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
|
||||
#define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
|
||||
#define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
|
||||
#endif
|
||||
#define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
|
||||
#define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
|
||||
#define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE)
|
||||
#define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE)
|
||||
#define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE)
|
||||
#define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE)
|
||||
#define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE)
|
||||
#define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE)
|
||||
#define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE)
|
||||
#define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE)
|
||||
#define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE)
|
||||
#define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE)
|
||||
#define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE)
|
||||
#define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE)
|
||||
#define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
|
||||
#define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
|
||||
#define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE)
|
||||
#define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE)
|
||||
#define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE)
|
||||
#define R_ADC_B ((R_ADC_B0_Type *) R_ADC120_BASE)
|
||||
#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
|
||||
#define R_DAC0 ((R_DAC_Type *) R_DAC120_BASE)
|
||||
#define R_DAC1 ((R_DAC_Type *) R_DAC121_BASE)
|
||||
#else
|
||||
#define R_DAC ((R_DAC_Type *) R_DAC12_BASE)
|
||||
#endif
|
||||
#define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
|
||||
#define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
|
||||
#define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
|
||||
#define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
|
||||
#define R_TFU ((R_TFU_Type *) R_TFU_BASE)
|
||||
#define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
|
||||
#define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE)
|
||||
|
||||
/* Not in SVD. */
|
||||
|
||||
#define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
|
||||
#define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
|
||||
#define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
|
||||
#define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
|
||||
#define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
|
||||
#define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
|
||||
#define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
|
||||
#define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
|
||||
#define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
|
||||
#define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
|
||||
#define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
#define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
|
||||
#define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE)
|
||||
#define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE)
|
||||
#define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE)
|
||||
#endif
|
||||
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
|
||||
#define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
|
||||
|
||||
#define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
|
||||
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
|
||||
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
|
||||
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
|
||||
|
||||
#define R_RTC ((R_RTC_Type *) R_RTC_BASE)
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_declaration */
|
||||
|
||||
#else
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ Device Specific Peripheral Address Map ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/** @addtogroup Device_Peripheral_peripheralAddr
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define R_ACMPHS0_BASE 0x40085000
|
||||
#define R_ACMPHS1_BASE 0x40085100
|
||||
#define R_ACMPHS2_BASE 0x40085200
|
||||
#define R_ACMPHS3_BASE 0x40085300
|
||||
#define R_ACMPHS4_BASE 0x40085400
|
||||
#define R_ACMPHS5_BASE 0x40085500
|
||||
#define R_ACMPLP_BASE 0x40085E00
|
||||
#define R_ADC0_BASE 0x4005C000
|
||||
#define R_ADC1_BASE 0x4005C200
|
||||
#define R_AGT0_BASE 0x40084000
|
||||
#define R_AGT1_BASE 0x40084100
|
||||
#define R_AGTW0_BASE 0x40084000
|
||||
#define R_AGTW1_BASE 0x40084100
|
||||
#define R_BUS_BASE 0x40003000
|
||||
#define R_CAC_BASE 0x40044600
|
||||
#define R_CAN0_BASE 0x40050000
|
||||
#define R_CAN1_BASE 0x40051000
|
||||
#define R_CRC_BASE 0x40074000
|
||||
#define R_CTSU_BASE 0x40081000
|
||||
#define R_CTSU2_BASE 0x40082000
|
||||
#define R_DAC_BASE 0x4005E000
|
||||
#define R_DAC8_BASE 0x4009E000
|
||||
#define R_DALI0_BASE 0x4008F000
|
||||
#define R_DEBUG_BASE 0x4001B000
|
||||
#define R_DMA_BASE 0x40005200
|
||||
#define R_DMAC0_BASE 0x40005000
|
||||
#define R_DMAC1_BASE 0x40005040
|
||||
#define R_DMAC2_BASE 0x40005080
|
||||
#define R_DMAC3_BASE 0x400050C0
|
||||
#define R_DMAC4_BASE 0x40005100
|
||||
#define R_DMAC5_BASE 0x40005140
|
||||
#define R_DMAC6_BASE 0x40005180
|
||||
#define R_DMAC7_BASE 0x400051C0
|
||||
#define R_DOC_BASE 0x40054100
|
||||
#define R_DRW_BASE 0x400E4000
|
||||
#define R_DTC_BASE 0x40005400
|
||||
#define R_ELC_BASE 0x40041000
|
||||
#define R_ETHERC0_BASE 0x40064100
|
||||
#define R_ETHERC_EDMAC_BASE 0x40064000
|
||||
#define R_PTP_EDMAC_BASE 0x40064400
|
||||
#define R_ETHERC_EPTPC_BASE 0x40065800
|
||||
#define R_ETHERC_EPTPC1_BASE 0x40065C00
|
||||
#define R_ETHERC_EPTPC_CFG_BASE 0x40064500
|
||||
#define R_ETHERC_EPTPC_COMMON_BASE 0x40065000
|
||||
#define R_FACI_HP_CMD_BASE 0x407E0000
|
||||
#define R_FACI_HP_BASE 0x407FE000
|
||||
#define R_FACI_LP_BASE 0x407EC000
|
||||
#define R_CTSUTRIM_BASE 0x407EC000
|
||||
#define R_FCACHE_BASE 0x4001C000
|
||||
#define R_GLCDC_BASE 0x400E0000
|
||||
#define R_GPT0_BASE 0x40078000
|
||||
#define R_GPT1_BASE 0x40078100
|
||||
#define R_GPT2_BASE 0x40078200
|
||||
#define R_GPT3_BASE 0x40078300
|
||||
#define R_GPT4_BASE 0x40078400
|
||||
#define R_GPT5_BASE 0x40078500
|
||||
#define R_GPT6_BASE 0x40078600
|
||||
#define R_GPT7_BASE 0x40078700
|
||||
#define R_GPT8_BASE 0x40078800
|
||||
#define R_GPT9_BASE 0x40078900
|
||||
#define R_GPT10_BASE 0x40078A00
|
||||
#define R_GPT11_BASE 0x40078B00
|
||||
#define R_GPT12_BASE 0x40078C00
|
||||
#define R_GPT13_BASE 0x40078D00
|
||||
#define R_GPT_ODC_BASE 0x4007B000
|
||||
#define R_GPT_OPS_BASE 0x40078FF0
|
||||
#define R_GPT_POEG0_BASE 0x40042000
|
||||
#define R_GPT_POEG1_BASE 0x40042100
|
||||
#define R_GPT_POEG2_BASE 0x40042200
|
||||
#define R_GPT_POEG3_BASE 0x40042300
|
||||
#define R_I3C0_BASE 0x40083000
|
||||
#define R_ICU_BASE 0x40006000
|
||||
#define R_IIC0_BASE 0x40053000
|
||||
#define R_IIC1_BASE 0x40053100
|
||||
#define R_IIC2_BASE 0x40053200
|
||||
#define R_IRDA_BASE 0x40070F00
|
||||
#define R_IWDT_BASE 0x40044400
|
||||
#define R_JPEG_BASE 0x400E6000
|
||||
#define R_KINT_BASE 0x40080000
|
||||
#define R_MMF_BASE 0x40001000
|
||||
#define R_MPU_MMPU_BASE 0x40000000
|
||||
#define R_MPU_SMPU_BASE 0x40000C00
|
||||
#define R_MPU_SPMON_BASE 0x40000D00
|
||||
#define R_MSTP_BASE (0x40047000 - 4U) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */
|
||||
#define R_OPAMP_BASE 0x40086000
|
||||
#define R_OPAMP2_BASE 0x400867F8
|
||||
#define R_PDC_BASE 0x40094000
|
||||
#define R_PORT0_BASE 0x40040000
|
||||
#define R_PORT1_BASE 0x40040020
|
||||
#define R_PORT2_BASE 0x40040040
|
||||
#define R_PORT3_BASE 0x40040060
|
||||
#define R_PORT4_BASE 0x40040080
|
||||
#define R_PORT5_BASE 0x400400A0
|
||||
#define R_PORT6_BASE 0x400400C0
|
||||
#define R_PORT7_BASE 0x400400E0
|
||||
#define R_PORT8_BASE 0x40040100
|
||||
#define R_PORT9_BASE 0x40040120
|
||||
#define R_PORT10_BASE 0x40040140
|
||||
#define R_PORT11_BASE 0x40040160
|
||||
#define R_PFS_BASE 0x40040800
|
||||
#define R_PMISC_BASE 0x40040D00
|
||||
#define R_QSPI_BASE 0x64000000
|
||||
#define R_RTC_BASE 0x40044000
|
||||
#define R_SCI0_BASE 0x40070000
|
||||
#define R_SCI1_BASE 0x40070020
|
||||
#define R_SCI2_BASE 0x40070040
|
||||
#define R_SCI3_BASE 0x40070060
|
||||
#define R_SCI4_BASE 0x40070080
|
||||
#define R_SCI5_BASE 0x400700A0
|
||||
#define R_SCI6_BASE 0x400700C0
|
||||
#define R_SCI7_BASE 0x400700E0
|
||||
#define R_SCI8_BASE 0x40070100
|
||||
#define R_SCI9_BASE 0x40070120
|
||||
#define R_SDADC0_BASE 0x4009C000
|
||||
#define R_SDHI0_BASE 0x40062000
|
||||
#define R_SDHI1_BASE 0x40062400
|
||||
#define R_SLCDC_BASE 0x40082000
|
||||
#define R_SPI0_BASE 0x40072000
|
||||
#define R_SPI1_BASE 0x40072100
|
||||
#define R_SRAM_BASE 0x40002000
|
||||
#define R_SRC_BASE 0x40048000
|
||||
#define R_SSI0_BASE 0x4004E000
|
||||
#define R_SSI1_BASE 0x4004E100
|
||||
#define R_SYSTEM_BASE 0x4001E000
|
||||
#define R_TSN_BASE 0x407EC000
|
||||
#define R_TSN_CAL_BASE 0x407FB17C
|
||||
#define R_TSN_CTRL_BASE 0x4005D000
|
||||
#define R_USB_FS0_BASE 0x40090000
|
||||
#define R_USB_HS0_BASE 0x40060000
|
||||
#define R_WDT_BASE 0x40044200
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/** @addtogroup Device_Peripheral_declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
|
||||
#define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
|
||||
#define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
|
||||
#define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
|
||||
#define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
|
||||
#define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
|
||||
#define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE)
|
||||
#define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE)
|
||||
#define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
|
||||
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
|
||||
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
|
||||
#define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
|
||||
#define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
|
||||
#define R_BUS ((R_BUS_Type *) R_BUS_BASE)
|
||||
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
|
||||
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
|
||||
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
|
||||
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
|
||||
#if (2U == BSP_FEATURE_CTSU_VERSION)
|
||||
#define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE)
|
||||
#else
|
||||
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
|
||||
#endif
|
||||
#define R_DAC ((R_DAC_Type *) R_DAC_BASE)
|
||||
#define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE)
|
||||
#define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE)
|
||||
#define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE)
|
||||
#define R_DMA ((R_DMA_Type *) R_DMA_BASE)
|
||||
#define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
|
||||
#define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
|
||||
#define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
|
||||
#define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
|
||||
#define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
|
||||
#define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
|
||||
#define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
|
||||
#define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
|
||||
#define R_DOC ((R_DOC_Type *) R_DOC_BASE)
|
||||
#define R_DRW ((R_DRW_Type *) R_DRW_BASE)
|
||||
#define R_DTC ((R_DTC_Type *) R_DTC_BASE)
|
||||
#define R_ELC ((R_ELC_Type *) R_ELC_BASE)
|
||||
#define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
|
||||
#define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
|
||||
#define R_PTP_EDMAC ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE)
|
||||
#define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE)
|
||||
#define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC0_Type *) R_ETHERC_EPTPC1_BASE)
|
||||
#define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE)
|
||||
#define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE)
|
||||
#define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
|
||||
#define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
|
||||
#define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE)
|
||||
#define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE)
|
||||
#define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
|
||||
#define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE)
|
||||
#define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE)
|
||||
#define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE)
|
||||
#define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE)
|
||||
#define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE)
|
||||
#define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE)
|
||||
#define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE)
|
||||
#define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE)
|
||||
#define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE)
|
||||
#define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE)
|
||||
#define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE)
|
||||
#define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE)
|
||||
#define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE)
|
||||
#define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE)
|
||||
#define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE)
|
||||
#define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
|
||||
#define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
|
||||
#define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
|
||||
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
|
||||
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
|
||||
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
|
||||
#define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
|
||||
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
|
||||
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
|
||||
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
|
||||
#define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE)
|
||||
#define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE)
|
||||
#define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
|
||||
#define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE)
|
||||
#define R_KINT ((R_KINT_Type *) R_KINT_BASE)
|
||||
#define R_MMF ((R_MMF_Type *) R_MMF_BASE)
|
||||
#define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
|
||||
#define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
|
||||
#define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
|
||||
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
|
||||
#if (2U == BSP_FEATURE_OPAMP_BASE_ADDRESS)
|
||||
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE)
|
||||
#else
|
||||
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE)
|
||||
#endif
|
||||
#define R_PDC ((R_PDC_Type *) R_PDC_BASE)
|
||||
#define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
|
||||
#define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
|
||||
#define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
|
||||
#define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
|
||||
#define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
|
||||
#define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
|
||||
#define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
|
||||
#define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
|
||||
#define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
|
||||
#define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
|
||||
#define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
|
||||
#define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
|
||||
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
|
||||
#define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
|
||||
#define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
|
||||
#define R_RTC ((R_RTC_Type *) R_RTC_BASE)
|
||||
#define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
|
||||
#define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
|
||||
#define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
|
||||
#define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
|
||||
#define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
|
||||
#define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
|
||||
#define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
|
||||
#define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
|
||||
#define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
|
||||
#define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
|
||||
#define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE)
|
||||
#define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
|
||||
#define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE)
|
||||
#define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE)
|
||||
#define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
|
||||
#define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
|
||||
#define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
|
||||
#define R_SRC ((R_SRC_Type *) R_SRC_BASE)
|
||||
#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
|
||||
#define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE)
|
||||
#define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE)
|
||||
#define R_TSN ((R_TSN_Type *) R_TSN_BASE)
|
||||
#define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
|
||||
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
|
||||
#define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
|
||||
#define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
|
||||
#define R_WDT ((R_WDT_Type *) R_WDT_BASE)
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_declaration */
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
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Reference in New Issue
Block a user