[bsp][renesas]add hwtimer device for renesas
This commit is contained in:
Rbb666
guo
parent
722a5fc29d
commit
594db2b516
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@ -192,6 +192,35 @@ RA系列已更新 **FSP 3.5.0** 版本的支持，请使用 **FSP 3.5.0** 版本
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4. 在 menuconfig 中打开对应的通道
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### Timer（GPT）
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GPT 定时器在该芯片中可作为通用定时器，可以用于计时功能。
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1、添加 GPT 设备
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2、对 GPT 较为关键的配置如图所示，具体解释如下：
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1. 设置开启的定时器名称，比如 timer0/1...
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2. 设置定时器通道，需要和定时器名称后缀名相同，比如 0/1...
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3. 设置定时器中断回调函数，比如 timer0—>**timer0_callback**，timer1—>**timer1_callback**
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4. 设置定时器中断优先级
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3、在 env 中配置 timer 外设：
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* 使能 timer 外设
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* 选择需要打开的某个定时器
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* 最后使用 scons --target=mdk5 等方式生成工程
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### PWM（GPT）
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GPT 定时器在该芯片中可作为通用定时器，也可以用于产生 PWM 信号。在将其用于产生 PWM 信号时，GPT 定时器提供了 gpt0 - gpt9 总共 10 个通道，每个通道可以设定两个输出端口。当前版本的 PWM 驱动将每个通道都看做一个单独的 PWM 设备，每个设备都只有一个通道。用户可以选择开启一个通道的任意一个输出端口，或将两个端口均开启，但在同时开启两个端口的情况下，它们输出的波形将完全一致。
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@ -53,6 +53,9 @@ if GetDepend(['BSP_USING_ONCHIP_FLASH']):
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if GetDepend(['BSP_USING_PWM']):
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src += ['drv_pwm.c']
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if GetDepend(['BSP_USING_TIM']):
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src += ['drv_hwtimer.c']
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if GetDepend(['BSP_USING_ETH']):
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src += ['drv_eth.c']
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -40,7 +40,31 @@ extern "C"
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#endif
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#endif /* SOC_SERIES_R7FA6M5 */
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#if (defined(SOC_SERIES_R7FA6M3)) || (defined(SOC_SERIES_R7FA6M4))
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#if defined(SOC_SERIES_R7FA6M3)
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#include "ra6m3/uart_config.h"
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#ifdef BSP_USING_ADC
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#include "ra6m3/adc_config.h"
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#endif
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#ifdef BSP_USING_DAC
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#include "ra6m3/dac_config.h"
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#endif
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#ifdef BSP_USING_PWM
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#include "ra6m3/pwm_config.h"
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#endif
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#ifdef BSP_USING_TIM
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#include "ra6m3/timer_config.h"
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#endif
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#ifdef BSP_USING_CAN
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#include "ra6m3/can_config.h"
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#endif
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#endif /* SOC_SERIES_R7FA6M3 */
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#if defined(SOC_SERIES_R7FA6M4)
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#include "ra6m4/uart_config.h"
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#ifdef BSP_USING_ADC
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@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-19 Mr.Tiger first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
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struct ra_adc_map
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{
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char name;
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const adc_cfg_t *g_cfg;
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const adc_instance_ctrl_t *g_ctrl;
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const adc_channel_cfg_t *g_channel_cfg;
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};
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struct ra_dev
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{
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rt_adc_device_t ra_adc_device_t;
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struct ra_adc_map *ra_adc_dev;
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};
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-29 mazhiyuan first version
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*/
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#ifndef __CAN_CONFIG_H__
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#define __CAN_CONFIG_H__
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#include <rtthread.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_CAN0)
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#ifndef CAN0_CONFIG
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#define CAN0_CONFIG \
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{ \
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.name = "can0", \
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.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0, \
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.p_api_ctrl = &g_can0_ctrl, \
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.p_cfg = &g_can0_cfg, \
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}
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#endif /* CAN0_CONFIG */
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#endif /* BSP_USING_CAN0 */
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#if defined(BSP_USING_CAN1)
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#ifndef CAN1_CONFIG
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#define CAN1_CONFIG \
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{ \
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.name = "can1", \
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.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1, \
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.p_api_ctrl = &g_can1_ctrl, \
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.p_cfg = &g_can1_cfg, \
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}
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#endif /* CAN1_CONFIG */
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#endif /* BSP_USING_CAN1 */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-19 Mr.Tiger first version
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*/
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#ifndef __DAC_CONFIG_H__
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#define __DAC_CONFIG_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_DAC
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struct ra_dac_map
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{
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char name;
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const struct st_dac_cfg *g_cfg;
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const struct st_dac_instance_ctrl *g_ctrl;
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};
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struct ra_dac_dev
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{
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rt_dac_device_t ra_dac_device_t;
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struct ra_dac_map *ra_dac_map_dev;
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};
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-26 KevinXu first version
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#include <drv_config.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum
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{
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#ifdef BSP_USING_PWM0
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BSP_PWM0_INDEX,
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#endif
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#ifdef BSP_USING_PWM1
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BSP_PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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BSP_PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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BSP_PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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BSP_PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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BSP_PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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BSP_PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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BSP_PWM7_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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BSP_PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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BSP_PWM9_INDEX,
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#endif
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BSP_PWMS_NUM
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};
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#define PWM_DRV_INITIALIZER(num) \
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{ \
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.name = "pwm"#num , \
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.g_cfg = &g_timer##num##_cfg, \
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.g_ctrl = &g_timer##num##_ctrl, \
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.g_timer = &g_timer##num, \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PWM_CONFIG_H__ */
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-09-04 Rbb666 first version
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*/
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#ifndef __TIMER_CONFIG_H__
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#define __TIMER_CONFIG_H__
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#include <rtthread.h>
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#include <drv_config.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define PLCKD_PRESCALER_MAX_SELECT 7
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/* RA6M3: Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64) */
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#define PLCKD_PRESCALER_120M (BSP_FEATURE_GPT_ODC_FREQ_MAX)
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#define PLCKD_PRESCALER_60M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 2)
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#define PLCKD_PRESCALER_30M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 4)
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#define PLCKD_PRESCALER_15M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 8)
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#define PLCKD_PRESCALER_7_5M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 16)
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#define PLCKD_PRESCALER_3_75M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 32)
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#define PLCKD_PRESCALER_1_875M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 64)
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#ifndef TMR_DEV_INFO_CONFIG
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#define TMR_DEV_INFO_CONFIG \
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{ \
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.maxfreq = 120000000, \
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.minfreq = 1875000, \
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.maxcnt = 0XFFFFFFFF, \
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.cntmode = HWTIMER_CNTMODE_UP, \
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}
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#endif /* TIM_DEV_INFO_CONFIG */
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enum
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{
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#ifdef BSP_USING_TIM0
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BSP_TIMER0_INDEX,
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#endif
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#ifdef BSP_USING_TIM1
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BSP_TIMER1_INDEX,
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#endif
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BSP_TIMERS_NUM
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};
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#define TIMER_DRV_INITIALIZER(num) \
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{ \
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.name = "timer" #num, \
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.g_cfg = &g_timer##num##_cfg, \
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.g_ctrl = &g_timer##num##_ctrl, \
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.g_timer = &g_timer##num, \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __TIMER_CONFIG_H__ */
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@ -0,0 +1,136 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-07-29 KyleChan first version
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*/
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#ifndef __UART_CONFIG_H__
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#define __UART_CONFIG_H__
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#include <rtthread.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_UART0)
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#ifndef UART0_CONFIG
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#define UART0_CONFIG \
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{ \
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.name = "uart0", \
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.p_api_ctrl = &g_uart0_ctrl, \
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.p_cfg = &g_uart0_cfg, \
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}
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#endif /* UART0_CONFIG */
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#endif /* BSP_USING_UART0 */
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#if defined(BSP_USING_UART1)
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#ifndef UART1_CONFIG
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#define UART1_CONFIG \
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{ \
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.name = "uart1", \
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.p_api_ctrl = &g_uart1_ctrl, \
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.p_cfg = &g_uart1_cfg, \
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}
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#endif /* UART1_CONFIG */
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#endif /* BSP_USING_UART1 */
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#if defined(BSP_USING_UART2)
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#ifndef UART2_CONFIG
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#define UART2_CONFIG \
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{ \
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.name = "uart2", \
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.p_api_ctrl = &g_uart2_ctrl, \
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.p_cfg = &g_uart2_cfg, \
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}
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#endif /* UART2_CONFIG */
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#endif /* BSP_USING_UART2 */
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#if defined(BSP_USING_UART3)
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#ifndef UART3_CONFIG
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#define UART3_CONFIG \
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{ \
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.name = "uart3", \
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.p_api_ctrl = &g_uart3_ctrl, \
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.p_cfg = &g_uart3_cfg, \
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}
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#endif /* UART3_CONFIG */
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#endif /* BSP_USING_UART3 */
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#if defined(BSP_USING_UART4)
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#ifndef UART4_CONFIG
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#define UART4_CONFIG \
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{ \
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.name = "uart4", \
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.p_api_ctrl = &g_uart4_ctrl, \
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.p_cfg = &g_uart4_cfg, \
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}
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#endif /* UART4_CONFIG */
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#endif /* BSP_USING_UART4 */
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#if defined(BSP_USING_UART5)
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#ifndef UART5_CONFIG
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#define UART5_CONFIG \
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{ \
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.name = "uart5", \
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.p_api_ctrl = &g_uart5_ctrl, \
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.p_cfg = &g_uart5_cfg, \
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}
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#endif /* UART5_CONFIG */
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#endif /* BSP_USING_UART5 */
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#if defined(BSP_USING_UART6)
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#ifndef UART6_CONFIG
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#define UART6_CONFIG \
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{ \
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.name = "uart6", \
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.p_api_ctrl = &g_uart6_ctrl, \
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.p_cfg = &g_uart6_cfg, \
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}
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#endif /* UART6_CONFIG */
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#endif /* BSP_USING_UART6 */
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#if defined(BSP_USING_UART7)
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#ifndef UART7_CONFIG
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#define UART7_CONFIG \
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{ \
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.name = "uart7", \
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.p_api_ctrl = &g_uart7_ctrl, \
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.p_cfg = &g_uart7_cfg, \
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}
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#endif /* UART7_CONFIG */
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#endif /* BSP_USING_UART7 */
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#if defined(BSP_USING_UART8)
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#ifndef UART8_CONFIG
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#define UART8_CONFIG \
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{ \
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.name = "uart8", \
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.p_api_ctrl = &g_uart8_ctrl, \
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.p_cfg = &g_uart8_cfg, \
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}
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#endif /* UART8_CONFIG */
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#endif /* BSP_USING_UART8 */
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||||
#if defined(BSP_USING_UART9)
|
||||
#ifndef UART9_CONFIG
|
||||
#define UART9_CONFIG \
|
||||
{ \
|
||||
.name = "uart9", \
|
||||
.p_api_ctrl = &g_uart9_ctrl, \
|
||||
.p_cfg = &g_uart9_cfg, \
|
||||
}
|
||||
#endif /* UART9_CONFIG */
|
||||
#endif /* BSP_USING_UART9 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,308 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-09-04 Rbb666 first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_hwtimer.h"
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.timer"
|
||||
#include <rtdbg.h>
|
||||
|
||||
#ifdef RT_USING_HWTIMER
|
||||
|
||||
static struct ra_hwtimer ra_hwtimer_obj[BSP_TIMERS_NUM] =
|
||||
{
|
||||
#ifdef BSP_USING_TIM0
|
||||
[BSP_TIMER0_INDEX] = TIMER_DRV_INITIALIZER(0),
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM1
|
||||
[BSP_TIMER1_INDEX] = TIMER_DRV_INITIALIZER(1),
|
||||
#endif
|
||||
};
|
||||
|
||||
const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] =
|
||||
{
|
||||
#ifdef SOC_SERIES_R7FA6M3
|
||||
PLCKD_PRESCALER_120M,
|
||||
PLCKD_PRESCALER_60M,
|
||||
PLCKD_PRESCALER_30M,
|
||||
PLCKD_PRESCALER_15M,
|
||||
PLCKD_PRESCALER_7_5M,
|
||||
PLCKD_PRESCALER_3_75M,
|
||||
PLCKD_PRESCALER_1_875M,
|
||||
#endif
|
||||
};
|
||||
|
||||
static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
|
||||
{
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
|
||||
struct ra_hwtimer *tim;
|
||||
tim = (struct ra_hwtimer *)timer->parent.user_data;
|
||||
|
||||
if (state)
|
||||
{
|
||||
fsp_err_t fsp_err = FSP_SUCCESS;
|
||||
|
||||
fsp_err = R_GPT_Open(tim->g_ctrl, tim->g_cfg);
|
||||
|
||||
if (fsp_err != FSP_SUCCESS)
|
||||
{
|
||||
LOG_E("%s init fail", tim->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode_t opmode)
|
||||
{
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
RT_ASSERT(opmode != RT_NULL);
|
||||
|
||||
struct ra_hwtimer *tim;
|
||||
tim = (struct ra_hwtimer *)timer->parent.user_data;
|
||||
fsp_err_t err = FSP_SUCCESS;
|
||||
|
||||
/* set timer count */
|
||||
R_GPT_CounterSet(tim->g_ctrl, 0);
|
||||
/* set timer period register */
|
||||
err = R_GPT_PeriodSet(tim->g_ctrl, pr);
|
||||
|
||||
if (err != FSP_SUCCESS)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
/* set timer to one cycle mode */
|
||||
err = R_GPT_Start(tim->g_ctrl);
|
||||
|
||||
return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
|
||||
}
|
||||
|
||||
static void timer_stop(rt_hwtimer_t *timer)
|
||||
{
|
||||
struct ra_hwtimer *tim = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
tim = (struct ra_hwtimer *)timer->parent.user_data;
|
||||
|
||||
/* stop timer */
|
||||
R_GPT_Stop(tim->g_ctrl);
|
||||
|
||||
/* set timer count */
|
||||
R_GPT_CounterSet(tim->g_ctrl, 0);
|
||||
}
|
||||
|
||||
static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
|
||||
{
|
||||
struct ra_hwtimer *tim = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
|
||||
tim = (struct ra_hwtimer *)timer->parent.user_data;
|
||||
|
||||
timer_info_t info;
|
||||
if (R_GPT_InfoGet(tim->g_ctrl, &info) != FSP_SUCCESS)
|
||||
return -RT_ERROR;
|
||||
|
||||
return info.period_counts;
|
||||
}
|
||||
|
||||
static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
struct ra_hwtimer *tim = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
RT_ASSERT(arg != RT_NULL);
|
||||
|
||||
tim = (struct ra_hwtimer *)timer->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case HWTIMER_CTRL_FREQ_SET:
|
||||
{
|
||||
rt_uint8_t index = 0;
|
||||
rt_uint32_t freq = *((rt_uint32_t *)arg);
|
||||
|
||||
for (rt_uint8_t i = 0; i < PLCKD_PRESCALER_MAX_SELECT; i++)
|
||||
{
|
||||
if (freq <= PLCKD_FREQ_PRESCALER[i])
|
||||
{
|
||||
index = i;
|
||||
}
|
||||
}
|
||||
tim->g_ctrl->p_reg->GTCR_b.TPCS = index;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
{
|
||||
result = -RT_ENOSYS;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void timer_one_shot_check(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
|
||||
/* Recover ISR context saved in open. */
|
||||
gpt_instance_ctrl_t *p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
|
||||
|
||||
/* If one-shot mode is selected, stop the timer since period has expired. */
|
||||
if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
|
||||
{
|
||||
p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
|
||||
|
||||
/* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
|
||||
p_instance_ctrl->p_reg->GTCNT = 0;
|
||||
p_instance_ctrl->p_reg->GTCCR[0U] = 0;
|
||||
p_instance_ctrl->p_reg->GTCCR[1U] = 0;
|
||||
|
||||
/* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
|
||||
R_BSP_IrqClearPending(irq);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_TIM0
|
||||
void timer0_callback(timer_callback_args_t *p_args)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if (TIMER_EVENT_CYCLE_END == p_args->event)
|
||||
{
|
||||
rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER0_INDEX].tmr_device);
|
||||
|
||||
timer_one_shot_check();
|
||||
}
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM1
|
||||
void timer1_callback(timer_callback_args_t *p_args)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if (TIMER_EVENT_CYCLE_END == p_args->event)
|
||||
{
|
||||
rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER1_INDEX].tmr_device);
|
||||
|
||||
timer_one_shot_check();
|
||||
}
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct rt_hwtimer_ops _ops =
|
||||
{
|
||||
.init = timer_init,
|
||||
.start = timer_start,
|
||||
.stop = timer_stop,
|
||||
.count_get = timer_counter_get,
|
||||
.control = timer_ctrl,
|
||||
};
|
||||
|
||||
static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG;
|
||||
|
||||
static int rt_hw_hwtimer_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
|
||||
for (int i = 0; i < sizeof(ra_hwtimer_obj) / sizeof(ra_hwtimer_obj[0]); i++)
|
||||
{
|
||||
ra_hwtimer_obj[i].tmr_device.info = &_info;
|
||||
ra_hwtimer_obj[i].tmr_device.ops = &_ops;
|
||||
if (rt_device_hwtimer_register(&ra_hwtimer_obj[i].tmr_device, ra_hwtimer_obj[i].name, &ra_hwtimer_obj[i]) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s register success", ra_hwtimer_obj[i].name);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("%s register failed", ra_hwtimer_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
|
||||
|
||||
/* This is a hwtimer example */
|
||||
#define HWTIMER_DEV_NAME "timer0" /* device name */
|
||||
|
||||
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
|
||||
{
|
||||
rt_kprintf("this is hwtimer timeout callback fucntion!\n");
|
||||
rt_kprintf("tick is :%d !\n", rt_tick_get());
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int hwtimer_sample(void)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
rt_hwtimerval_t timeout_s;
|
||||
rt_device_t hw_dev = RT_NULL;
|
||||
rt_hwtimer_mode_t mode;
|
||||
rt_uint32_t freq = 1875000; /* 1Mhz */
|
||||
|
||||
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
|
||||
if (hw_dev == RT_NULL)
|
||||
{
|
||||
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
|
||||
if (ret != RT_EOK)
|
||||
{
|
||||
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
|
||||
return ret;
|
||||
}
|
||||
|
||||
rt_device_set_rx_indicate(hw_dev, timeout_cb);
|
||||
|
||||
rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq);
|
||||
|
||||
mode = HWTIMER_MODE_PERIOD;
|
||||
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
|
||||
if (ret != RT_EOK)
|
||||
{
|
||||
rt_kprintf("set mode failed! ret is :%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Example Set the timeout period of the timer */
|
||||
timeout_s.sec = 1; /* secend */
|
||||
timeout_s.usec = 0; /* microsecend */
|
||||
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
|
||||
{
|
||||
rt_kprintf("set timeout value failed\n");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
/* read hwtimer value */
|
||||
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
|
||||
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
|
||||
|
||||
return ret;
|
||||
}
|
||||
MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
|
||||
|
||||
#endif /* BSP_USING_HWTIMER */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-09-04 Rbb666 first version
|
||||
*/
|
||||
|
||||
#ifndef __TMR_CONFIG_H__
|
||||
#define __TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/hwtimer.h>
|
||||
#include <drv_config.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
struct ra_hwtimer
|
||||
{
|
||||
rt_hwtimer_t tmr_device;
|
||||
gpt_instance_ctrl_t *g_ctrl;
|
||||
timer_instance_t const *const g_timer;
|
||||
timer_cfg_t const *const g_cfg;
|
||||
char *name;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TMR_CONFIG_H__ */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -59,10 +59,10 @@ static time_t get_rtc_timestamp(void)
|
|||
return timegm(&tm_new);
|
||||
}
|
||||
|
||||
static rt_err_t ra_get_secs(void *args)
|
||||
static rt_err_t ra_get_secs(time_t *sec)
|
||||
{
|
||||
*(rt_uint32_t *)args = get_rtc_timestamp();
|
||||
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
|
||||
*(rt_uint32_t *)sec = get_rtc_timestamp();
|
||||
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)sec);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
|
@ -95,25 +95,25 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
|
|||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t ra_set_secs(void *args)
|
||||
static rt_err_t ra_set_secs(time_t *sec)
|
||||
{
|
||||
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
if (set_rtc_time_stamp(*(rt_uint32_t *)args))
|
||||
if (set_rtc_time_stamp(*(rt_uint32_t *)sec))
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
|
||||
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)sec);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_ALARM
|
||||
static rt_err_t ra_get_alarm(void *arg)
|
||||
static rt_err_t ra_get_alarm(struct rt_rtc_wkalarm *alarm)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
|
||||
struct rt_rtc_wkalarm *wkalarm = alarm;
|
||||
rtc_alarm_time_t alarm_time_get =
|
||||
{
|
||||
.sec_match = RT_FALSE,
|
||||
|
|
@ -139,10 +139,10 @@ static rt_err_t ra_get_alarm(void *arg)
|
|||
return result;
|
||||
}
|
||||
|
||||
static rt_err_t ra_set_alarm(void *arg)
|
||||
static rt_err_t ra_set_alarm(struct rt_rtc_wkalarm *alarm)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
|
||||
struct rt_rtc_wkalarm *wkalarm = alarm;
|
||||
rtc_alarm_time_t alarm_time_set =
|
||||
{
|
||||
.sec_match = RT_TRUE,
|
||||
|
|
|
|||
|
|
@ -50,6 +50,38 @@ menu "Hardware Drivers Config"
|
|||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Enable I2C BUS"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_HW_I2C
|
||||
bool "Enable Hardware I2C BUS"
|
||||
default n
|
||||
if BSP_USING_HW_I2C
|
||||
config BSP_USING_HW_I2C0
|
||||
bool "Enable Hardware I2C0 BUS"
|
||||
default n
|
||||
endif
|
||||
if !BSP_USING_HW_I2C
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default y
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
hex "i2c1 scl pin number"
|
||||
range 0x0000 0x0B0F
|
||||
default 0x050C
|
||||
config BSP_I2C1_SDA_PIN
|
||||
hex "I2C1 sda pin number"
|
||||
range 0x0000 0x0B0F
|
||||
default 0x050B
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_FS
|
||||
bool "Enable File System"
|
||||
select RT_USING_DFS
|
||||
|
|
@ -75,6 +107,19 @@ menu "Hardware Drivers Config"
|
|||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_TIM
|
||||
bool "Enable timer"
|
||||
default n
|
||||
select RT_USING_HWTIMER
|
||||
if BSP_USING_TIM
|
||||
config BSP_USING_TIM0
|
||||
bool "Enable TIM0"
|
||||
default n
|
||||
config BSP_USING_TIM1
|
||||
bool "Enable TIM1"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_LCD
|
||||
bool "Enable LCD"
|
||||
select BSP_USING_GPIO
|
||||
|
|
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Reference in New Issue