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Merge pull request #1395 from TanekLiang/imxrt-update 

i.mx rt update
This commit is contained in:
Bernard Xiong 2018-05-03 09:14:57 +08:00 committed by GitHub
parent a901693fb5 418c9dfc80
commit 578067a64a
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 206 additions and 17 deletions
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7
bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c
View File

@ -1346,12 +1346,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
{
// Change SDK to reduce memory copy
extern void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len);
pbuf2mem(data, (void *)address, length);
}
//memcpy((void *)address, data, length);
memcpy((void *)address, data, length);
/* Set data length. */
curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE

24
bsp/imxrt1052-evk/README.md
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@ -27,7 +27,7 @@ i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具
### 3.1 配置工程
i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野火的i.MX RT1052开发板。如果不是基于官方开发板，那么重新配置并生成工程：
i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野火的i.MX RT1052开发板等。如果不是基于官方开发板，那么需要重新配置并生成工程：
- 在bsp下打开env工具
- 输入`menuconfig`命令，`RT1052 Board select (***)-->`选择正确的开发板。
@ -37,15 +37,31 @@ i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野
#### 3.2.1 MIMXRT1050-EVK
EVK开发板有板载OpenSDA仿真器，仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28)，就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口就可以看到shell输出
EVK开发板有板载OpenSDA仿真器，仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28)，就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口。
#### 3.2.2 野火开发板
连接外置仿真器（野火DAP仿真器或者Jlink）后，就可以进行下载和下载。使用USB线连接开发板底板的USB转串口，在终端工具里打开相应的串口。
### 3.3 运行结果
如果编译 & 烧写无误，当复位设备后，会在串口上（PuTTY）看到RT-Thread的启动logo信息：
如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
TODO
```
\ | /
- RT - Thread Operating System
/ | \ 3.0.4 build May 2 2018
2006 - 2018 Copyright by rt-thread team
lwIP-2.0.2 initialized!
using armcc, version: 5060750
build time: May 2 2018 21:52:40
msh />[PHY] wait autonegotiation complete...
SD card capacity 123904 KB
probe mmcsd block device!
found part[0], begin: 32256, size: 120.992MB
File System initialized!
[PHY] wait autonegotiation complete...
```
## 4. 驱动支持情况及计划

190
bsp/imxrt1052-evk/drivers/drv_eth.c
View File

@ -23,6 +23,7 @@
#include "fsl_gpio.h"
#include "fsl_iomuxc.h"
#include "fsl_phy.h"
#include "fsl_cache.h"
#ifdef RT_USING_LWIP
@ -479,6 +480,188 @@ static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
return RT_EOK;
}
static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
{
assert(ringId < FSL_FEATURE_ENET_QUEUE);
switch (ringId)
{
case 0:
base->TDAR = ENET_TDAR_TDAR_MASK;
break;
#if FSL_FEATURE_ENET_QUEUE > 1
case kENET_Ring1:
base->TDAR1 = ENET_TDAR1_TDAR_MASK;
break;
case kENET_Ring2:
base->TDAR2 = ENET_TDAR2_TDAR_MASK;
break;
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
default:
base->TDAR = ENET_TDAR_TDAR_MASK;
break;
}
}
static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length)
{
assert(handle);
assert(data);
volatile enet_tx_bd_struct_t *curBuffDescrip;
uint32_t len = 0;
uint32_t sizeleft = 0;
uint32_t address;
/* Check the frame length. */
if (length > ENET_FRAME_MAX_FRAMELEN)
{
return kStatus_ENET_TxFrameOverLen;
}
/* Check if the transmit buffer is ready. */
curBuffDescrip = handle->txBdCurrent[0];
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
{
return kStatus_ENET_TxFrameBusy;
}
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
bool isPtpEventMessage = false;
/* Check PTP message with the PTP header. */
isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/* One transmit buffer is enough for one frame. */
if (handle->txBuffSizeAlign[0] >= length)
{
/* Copy data to the buffer for uDMA transfer. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0);
/* Set data length. */
curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* For enable the timestamp. */
if (isPtpEventMessage)
{
curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
else
{
curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK);
/* Increase the buffer descriptor address. */
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
{
handle->txBdCurrent[0] = handle->txBdBase[0];
}
else
{
handle->txBdCurrent[0]++;
}
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, length);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
_ENET_ActiveSend(base, 0);
return kStatus_Success;
}
else
{
/* One frame requires more than one transmit buffers. */
do
{
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* For enable the timestamp. */
if (isPtpEventMessage)
{
curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
else
{
curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/* Increase the buffer descriptor address. */
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
{
handle->txBdCurrent[0] = handle->txBdBase[0];
}
else
{
handle->txBdCurrent[0]++;
}
/* update the size left to be transmit. */
sizeleft = length - len;
if (sizeleft > handle->txBuffSizeAlign[0])
{
/* Data copy. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
/* Data length update. */
curBuffDescrip->length = handle->txBuffSizeAlign[0];
len += handle->txBuffSizeAlign[0];
/* Sets the control flag. */
curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
/* Active the transmit buffer descriptor*/
_ENET_ActiveSend(base, 0);
}
else
{
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, sizeleft);
curBuffDescrip->length = sizeleft;
/* Set Last buffer wrap flag. */
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
_ENET_ActiveSend(base, 0);
return kStatus_Success;
}
/* Get the current buffer descriptor address. */
curBuffDescrip = handle->txBdCurrent[0];
} while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
return kStatus_ENET_TxFrameBusy;
}
}
/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
@ -497,7 +680,7 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
do
{
result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
if (result == kStatus_ENET_TxFrameBusy)
{
@ -511,11 +694,6 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
return RT_EOK;
}
void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len)
{
pbuf_copy_partial((const struct pbuf *)data, dataptr, len, 0);
}
/* reception packet. */
struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
{

2
bsp/imxrt1052-evk/drivers/drv_sdio.c
View File

@ -56,7 +56,7 @@ static int enable_log = 1;
#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
#define IMXRT_MAX_FREQ (50UL * 1000UL * 1000UL)
#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL)
#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */