[BSP][RT1050] improve sdio stability and speed. | 优化SDIO接口稳定性和速度.
1.格式化代码. 2.优化SDIO接口稳定性和速度: 将SDIO时钟树中分频数增大, 提高内部时钟的稳定性, 同时SDIO速度提高到30M. 并且通过USB拷贝12M MP3文件测试, 多次拷贝数据稳定.
This commit is contained in:
liu2guang
parent
236fd82e5d
commit
51f638ad63
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@ -76,14 +76,15 @@ static int enable_log = 1;
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ALIGN(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable");
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struct imxrt_mmcsd {
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struct rt_mmcsd_host *host;
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struct rt_mmcsd_req *req;
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struct rt_mmcsd_cmd *cmd;
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struct imxrt_mmcsd
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{
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struct rt_mmcsd_host *host;
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struct rt_mmcsd_req *req;
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struct rt_mmcsd_cmd *cmd;
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struct rt_timer timer;
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struct rt_timer timer;
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rt_uint32_t *buf;
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rt_uint32_t *buf;
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//USDHC_Type *base;
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usdhc_host_t usdhc_host;
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@ -93,7 +94,7 @@ struct imxrt_mmcsd {
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uint32_t *usdhc_adma2_table;
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};
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static void _mmcsd_gpio_init(struct imxrt_mmcsd * mmcsd)
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static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd)
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{
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gpio_pin_config_t sw_config;
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@ -112,54 +113,54 @@ static void _mmcsd_gpio_init(struct imxrt_mmcsd * mmcsd)
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/* voltage select PIN */
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0);
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/* card detect PIN */
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/* card detect PIN */
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0);
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/* power reset pin */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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/*voltage select pin*/
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_GPIO2_IO28, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1));
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sw_config.direction = kGPIO_DigitalOutput;
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sw_config.outputLogic = 0;
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@ -172,10 +173,10 @@ static void _mmcsd_gpio_init(struct imxrt_mmcsd * mmcsd)
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#endif
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#ifdef RT_USING_SDIO2
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if (mmcsd->usdhc_host.base == USDHC2)
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{
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// todo
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}
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if (mmcsd->usdhc_host.base == USDHC2)
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{
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// todo
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}
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#endif
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}
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@ -199,7 +200,7 @@ static void SDMMCHOST_ErrorRecovery(USDHC_Type *base)
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}
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}
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static void _mmcsd_host_init(struct imxrt_mmcsd * mmcsd)
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static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd)
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{
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usdhc_host_t *usdhc_host = &mmcsd->usdhc_host;
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@ -214,28 +215,28 @@ static void _mmcsd_host_init(struct imxrt_mmcsd * mmcsd)
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USDHC_Init(usdhc_host->base, &(usdhc_host->config));
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}
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static void _mmcsd_clk_init(struct imxrt_mmcsd * mmcsd)
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static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd)
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{
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CLOCK_EnableClock(mmcsd->ip_clock);
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CLOCK_SetDiv(mmcsd->usdhc_div, 0U);
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CLOCK_SetDiv(mmcsd->usdhc_div, 5U);
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}
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static void _mmcsd_isr_init(struct imxrt_mmcsd * mmcsd)
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static void _mmcsd_isr_init(struct imxrt_mmcsd *mmcsd)
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{
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//NVIC_SetPriority(USDHC1_IRQn, 5U);
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}
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static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct imxrt_mmcsd * mmcsd;
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struct rt_mmcsd_cmd * cmd;
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struct rt_mmcsd_data * data;
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struct imxrt_mmcsd *mmcsd;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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status_t error;
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usdhc_adma_config_t dmaConfig;
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usdhc_transfer_t fsl_content = {0};
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usdhc_command_t fsl_command = {0};
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usdhc_data_t fsl_data = {0};
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rt_uint32_t * buf = NULL;
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rt_uint32_t *buf = NULL;
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RT_ASSERT(host != RT_NULL);
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RT_ASSERT(req != RT_NULL);
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@ -294,11 +295,11 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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case RESP_R5:
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fsl_command.responseType = kCARD_ResponseTypeR5;
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break;
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/*
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case RESP_R5B:
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fsl_command.responseType = kCARD_ResponseTypeR5b;
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break;
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*/
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/*
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case RESP_R5B:
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fsl_command.responseType = kCARD_ResponseTypeR5b;
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break;
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*/
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default:
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RT_ASSERT(NULL);
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}
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@ -341,7 +342,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount);
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if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte)
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((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM
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((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM
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((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM
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{
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@ -414,7 +415,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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cmd->resp[1] = fsl_command.response[2];
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cmd->resp[0] = fsl_command.response[3];
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MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n",
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cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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@ -430,7 +431,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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struct imxrt_mmcsd * mmcsd;
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struct imxrt_mmcsd *mmcsd;
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unsigned int usdhc_clk;
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unsigned int bus_width;
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uint32_t src_clk;
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@ -441,9 +442,9 @@ static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *i
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mmcsd = (struct imxrt_mmcsd *)host->private_data;
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usdhc_clk = io_cfg->clock;
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bus_width = io_cfg->bus_width;
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bus_width = io_cfg->bus_width;
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if(usdhc_clk > IMXRT_MAX_FREQ)
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if (usdhc_clk > IMXRT_MAX_FREQ)
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usdhc_clk = IMXRT_MAX_FREQ;
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src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U));
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@ -492,64 +493,65 @@ FINSH_FUNCTION_EXPORT(log_toggle, toglle log dumple);
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//
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//}
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static const struct rt_mmcsd_host_ops ops = {
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_mmc_request,
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_mmc_set_iocfg,
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static const struct rt_mmcsd_host_ops ops =
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{
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_mmc_request,
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_mmc_set_iocfg,
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RT_NULL,//_mmc_get_card_status,
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RT_NULL,//_mmc_enable_sdio_irq,
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RT_NULL,//_mmc_enable_sdio_irq,
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};
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rt_int32_t _imxrt_mci_init(void)
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{
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struct rt_mmcsd_host *host;
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struct imxrt_mmcsd *mmcsd;
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struct rt_mmcsd_host *host;
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struct imxrt_mmcsd *mmcsd;
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host = mmcsd_alloc_host();
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if (!host)
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{
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return -RT_ERROR;
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}
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host = mmcsd_alloc_host();
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if (!host)
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{
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return -RT_ERROR;
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}
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mmcsd = rt_malloc(sizeof(struct imxrt_mmcsd));
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if (!mmcsd)
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{
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rt_kprintf("alloc mci failed\n");
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goto err;
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}
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mmcsd = rt_malloc(sizeof(struct imxrt_mmcsd));
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if (!mmcsd)
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{
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rt_kprintf("alloc mci failed\n");
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goto err;
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}
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rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd));
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rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd));
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mmcsd->usdhc_host.base = USDHC1;
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mmcsd->usdhc_div = kCLOCK_Usdhc1Div;
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mmcsd->usdhc_adma2_table = g_usdhcAdma2Table;
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host->ops = &ops;
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host->freq_min = 375000;
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host->freq_max = 25000000;
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host->valid_ocr = VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
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MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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host->max_blk_size = 512;
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host->max_blk_count = 4096;
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host->ops = &ops;
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host->freq_min = 375000;
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host->freq_max = 25000000;
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host->valid_ocr = VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
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MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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host->max_blk_size = 512;
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host->max_blk_count = 4096;
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mmcsd->host = host;
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mmcsd->host = host;
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_mmcsd_clk_init(mmcsd);
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_mmcsd_isr_init(mmcsd);
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_mmcsd_gpio_init(mmcsd);
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_mmcsd_gpio_init(mmcsd);
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_mmcsd_host_init(mmcsd);
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host->private_data = mmcsd;
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host->private_data = mmcsd;
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mmcsd_change(host);
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mmcsd_change(host);
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return 0;
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return 0;
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err:
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mmcsd_free_host(host);
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mmcsd_free_host(host);
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return -RT_ENOMEM;
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return -RT_ENOMEM;
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}
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int imxrt_mci_init(void)
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