update lpc2148 startup_gcc.S
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1584 bbd45198-f89e-11dd-88c7-29a3b14d5316
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wuyangyong
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b4bc59f918
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518bdc44b2
@ -1,12 +1,5 @@
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.extern main /* ÒýÈëÍⲿCÈë¿Ú */
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.extern __bss_beg__
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.extern __bss_end
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.extern __stack_end__
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.extern __data_beg__
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.extern __data_end__
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.extern __data+beg_src__
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.extern rt_interrupt_enter
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.extern rt_interrupt_leave
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.extern rt_thread_switch_interrput_flag
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@ -18,19 +11,6 @@
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.global endless_loop
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.global rt_hw_context_switch_interrupt_do
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/************* 目标配置 *************/
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.set UND_STACK_SIZE, 0x00000004
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.set ABT_STACK_SIZE, 0x00000004
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.set FIQ_STACK_SIZE, 0x00000004
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.set IRQ_STACK_SIZE, 0x00000400
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.set SVC_STACK_SIZE, 0x00000400
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.set UND_Stack_Size, 0x00000004
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.set ABT_Stack_Size, 0x00000004
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.set FIQ_Stack_Size, 0x00000004
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.set IRQ_Stack_Size, 0x00000400
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.set SVC_Stack_Size, 0x00000400
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
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.set MODE_USR, 0x10 /* User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Mode */
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@ -39,13 +19,6 @@
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.set MODE_ABT, 0x17 /* Abort Mode */
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.set MODE_UND, 0x1B /* Undefined Mode */
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.set MODE_SYS, 0x1F /* System Mode */
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.set MODE_USR, 0x10 /* User Mode */
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.set Mode_FIQ, 0x11 /* FIQ Mode */
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.set Mode_IRQ, 0x12 /* IRQ Mode */
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.set Mode_SVC, 0x13 /* Supervisor Mode */
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.set Mode_ABT, 0x17 /* Abort Mode */
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.set Mode_UND, 0x1B /* Undefined Mode */
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.set Mode_SYS, 0x1F /* System Mode */
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.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
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@ -57,18 +30,17 @@
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.set VPBDIV_VALUE, 0x00000000
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/* Phase Locked Loop (PLL) definitions*/
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.equ PLL_BASE, 0xE01FC080
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.equ PLLCON_OFS, 0x00
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.equ PLLCFG_OFS, 0x04
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.equ PLLSTAT_OFS, 0x08
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.equ PLLFEED_OFS, 0x0C
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.equ PLLCON_PLLE, (1<<0) /* PLL Enable */
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.equ PLLCON_PLLC, (1<<1) /* PLL Connect */
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.equ PLLSTAT_LOCK, (1<<10) /* PLL Lock Status */
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//.equ PLLCFG_MSEL, ((PLL_MUL - 1) << 0)
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.equ PLLCFG_PSEL, (0x02 << 5)
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//.equ PLLCFG_Val, (PLLCFG_MSEL|PLLCFG_PSEL)
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.equ PLL_BASE, 0xE01FC080 /* PLL Base Address */
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.equ PLLCON_OFS, 0x00 /* PLL Control Offset */
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.equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */
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.equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */
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.equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */
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.equ PLLCON_PLLE, (1<<0) /* PLL Enable */
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.equ PLLCON_PLLC, (1<<1) /* PLL Connect */
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.equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */
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.equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */
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.equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */
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.equ PLLCFG_Val, 0x00000024 /* <o1.0..4> MSEL: PLL Multiplier Selection,<o1.5..6> PSEL: PLL Divider Selection */
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.equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/
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@ -87,19 +59,12 @@
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/* Setup the operating mode & stack.*/
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/* --------------------------------- */
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.global _start, start, _reset, reset,
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.func _start,
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_start:
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start:
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.global _reset
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_reset:
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reset:
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.code 32
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.align 0
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/************************* PLL_SETUP **********************************/
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#if (PLL_MUL>1)
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ldr r0, =PLL_BASE
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mov r1, #0xAA
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mov r2, #0x55
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@ -115,7 +80,7 @@ reset:
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/* Wait until PLL Locked */
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PLL_Locked_loop:
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ldr r3, [r0, #PLLSTAT_OFS]
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ands r3, r3, #PLLSTAT_LOCK
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ands r3, r3, #PLLSTAT_PLOCK
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beq PLL_Locked_loop
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/* Switch to PLL Clock */
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@ -123,8 +88,6 @@ PLL_Locked_loop:
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str r3, [r0, #PLLCON_OFS]
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str r1, [r0, #PLLFEED_OFS]
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str R2, [r0, #PLLFEED_OFS]
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#endif
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/************************* PLL_SETUP **********************************/
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/************************ Setup VPBDIV ********************************/
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@ -142,105 +105,104 @@ PLL_Locked_loop:
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/************** Setup MAM **************/
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/************************ setup stack *********************************/
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ldr r0, .LC6 /* LC6:__stack_end__ */
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ldr r0, .undefined_stack_top
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sub r0, r0, #4
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msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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mov sp, r0
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sub r0, r0, #UND_STACK_SIZE
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ldr r0, .abort_stack_top
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sub r0, r0, #4
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msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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mov sp, r0
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sub r0, r0, #ABT_STACK_SIZE
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ldr r0, .fiq_stack_top
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sub r0, r0, #4
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msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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mov sp, r0
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sub r0, r0, #FIQ_STACK_SIZE
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ldr r0, .irq_stack_top
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sub r0, r0, #4
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msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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mov sp, r0
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sub r0, r0, #IRQ_STACK_SIZE
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ldr r0, .svc_stack_top
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sub r0, r0, #4
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msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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mov sp, r0
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/************************ setup stack ********************************/
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/************************ Clear BSS ********************************/
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/* Clear BSS. */
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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mov a2, #0 /* Fill value */
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mov fp, a2 /* Null frame pointer */
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mov r7, a2 /* Null frame pointer for Thumb */
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add r1, r1, #4
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add r3, r3, #4
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ldr r1, .LC1 /* Start of memory block */
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ldr r3, .LC2 /* End of memory block */
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subs r3, r3, r1 /* Length of block */
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beq .end_clear_loop
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mov r2, #0
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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.clear_loop:
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strb r2, [r1], #1
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subs r3, r3, #1
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bgt .clear_loop
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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.end_clear_loop:
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/* Initialise data. */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ldr r1, .LC3 /* Start of memory block */
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ldr r2, .LC4 /* End of memory block */
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ldr r3, .LC5
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subs r3, r3, r1 /* Length of block */
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beq .end_set_loop
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.set_loop:
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ldrb r4, [r2], #1
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strb r4, [r1], #1
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subs r3, r3, #1
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bgt .set_loop
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.end_set_loop:
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mov r0, #0 /* no arguments */
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mov r1, #0 /* no argv either */
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* enter C code */
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bl main
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endless_loop:
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b endless_loop
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.align 0
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.LC1:
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.word __bss_beg__
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.LC2:
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.word __bss_end
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.LC3:
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.word __data_beg__
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.LC4:
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.word __data_beg_src__
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.LC5:
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.word __data_end__
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.LC6:
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.word __stack_end__
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.undefined_stack_top:
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.word _undefined_stack_top
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.abort_stack_top:
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.word _abort_stack_top
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.fiq_stack_top:
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.word _fiq_stack_top
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.irq_stack_top:
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.word _irq_stack_top
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.svc_stack_top:
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.word _svc_stack_top
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/*********************** END Clear BSS ******************************/
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/******************** 跳转到 main() ********************/
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LDR R0, =main /* 获得main()入口地址 */
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BX R0 /* 长跳转到main() */
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/******************** 跳转到 main() ********************/
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/* 本段为.startup段 在链接脚本中被链接到程序最开头 */
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.section .startup,"ax"
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.code 32
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.align 0
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.section .init,"ax"
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.code 32
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.align 0
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.globl _start
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_start:
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ldr pc, __start /* reset - _start */
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ldr pc, _undf /* undefined - _undf */
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ldr pc, _swi /* SWI - _swi */
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ldr pc, _pabt /* program abort - _pabt */
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ldr pc, _dabt /* data abort - _dabt */
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//.word 0xB9205F80 /* 默认 0xB9205F80 */
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.word 0xB8A06F58 /* 0xB8A06F58 全为 */
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.word 0xB8A06F58 /* reserved */
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ldr pc, __IRQ_Handler /* IRQ - read the VIC */
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ldr pc, _fiq /* FIQ - _fiq */
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__start:.word _start
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__start:.word _reset
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_undf: .word __undf /* undefined */
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_swi: .word __swi /* SWI */
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_pabt: .word __pabt /* program abort */
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