Merge pull request #125 from reynoldxu/K60Fxxxx
add K60Fxxxx bsp for TWR-K60F120M board.
This commit is contained in:
Bernard Xiong
commit
51532ae425
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@ -0,0 +1,14 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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cwd = str(Dir('#'))
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@ -0,0 +1,37 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-k60.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# build program
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env.Program(TARGET, objs)
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# end building
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EndBuilding(TARGET)
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@ -0,0 +1,11 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,120 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard the first version
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* 2013-07-11 reynolds port to TWR-K60F120M
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*/
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/**
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* @addtogroup k60
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*/
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/*@{*/
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#include <stdio.h>
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#include "MK60F12.h"
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#include <board.h>
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#include <rtthread.h>
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#include "led.h"
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#ifdef RT_USING_LWIP
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#include <lwip/sys.h>
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#include <lwip/api.h>
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#include <netif/ethernetif.h>
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#include "stm32_eth.h"
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#endif
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void rt_init_thread_entry(void* parameter)
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{
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/* LwIP Initialization */
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#ifdef RT_USING_LWIP
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{
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extern void lwip_sys_init(void);
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/* register ethernetif device */
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eth_system_device_init();
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rt_hw_stm32_eth_init();
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/* re-init device driver */
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rt_device_init_all();
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/* init lwip system */
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lwip_sys_init();
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rt_kprintf("TCP/IP initialized!\n");
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}
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#endif
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//FS
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//GUI
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}
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float f_var1;
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float f_var2;
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float f_var3;
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float f_var4;
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ALIGN(RT_ALIGN_SIZE)
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static char thread_led1_stack[1024];
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struct rt_thread thread_led1;
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static void rt_thread_entry_led1(void* parameter)
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{
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int n = 0;
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rt_hw_led_init();
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while (1)
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{
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//rt_kprintf("LED\t%d\tis shining\r\n",n);
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rt_hw_led_on(n);
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rt_thread_delay(RT_TICK_PER_SECOND/2);
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rt_hw_led_off(n);
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rt_thread_delay(RT_TICK_PER_SECOND/2);
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n++;
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if(n > LED_MAX-1)
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n = 0;
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}
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}
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int rt_application_init()
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{
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rt_thread_t init_thread;
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#if (RT_THREAD_PRIORITY_MAX == 32)
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init_thread = rt_thread_create("init",
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rt_init_thread_entry, RT_NULL,
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2048, 8, 20);
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#else
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init_thread = rt_thread_create("init",
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rt_init_thread_entry, RT_NULL,
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2048, 80, 20);
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#endif
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if (init_thread != RT_NULL)
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rt_thread_startup(init_thread);
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//------- init led1 thread
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rt_thread_init(&thread_led1,
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"led_demo",
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rt_thread_entry_led1,
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RT_NULL,
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&thread_led1_stack[0],
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sizeof(thread_led1_stack),11,5);
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rt_thread_startup(&thread_led1);
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return 0;
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}
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/*@}*/
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@ -0,0 +1,125 @@
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/*
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* File : startup.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2006-08-31 Bernard first implementation
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* 2013-07-11 reynolds port to TWR-K60F120M
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <MK60F12.H>
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#include "board.h"
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/**
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* @addtogroup k60
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*/
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/*@{*/
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extern int rt_application_init(void);
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#ifdef RT_USING_FINSH
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extern void finsh_system_init(void);
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extern void finsh_set_device(const char* device);
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#endif
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define k60_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="HEAP"
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#define k60_SRAM_BEGIN (__segment_end("HEAP"))
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#else
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extern int __bss_end;
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#define k60_SRAM_BEGIN (&__bss_end)
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#endif
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/*******************************************************************************
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* Function Name : assert_failed
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* Description : Reports the name of the source file and the source line number
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* where the assert error has occurred.
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* Input : - file: pointer to the source file name
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* - line: assert error line source number
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* Output : None
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* Return : None
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*******************************************************************************/
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void assert_failed(rt_uint8_t* file, rt_uint32_t line)
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{
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rt_kprintf("\n\r Wrong parameter value detected on\r\n");
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rt_kprintf(" file %s\r\n", file);
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rt_kprintf(" line %d\r\n", line);
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while (1) ;
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}
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/**
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* This function will startup RT-Thread RTOS.
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*/
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void rtthread_startup(void)
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{
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/* init board */
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rt_hw_board_init();
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/* show version */
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rt_show_version();
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/* init tick */
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rt_system_tick_init();
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/* init kernel object */
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rt_system_object_init();
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/* init timer system */
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rt_system_timer_init();
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rt_system_heap_init((void*)k60_SRAM_BEGIN, (void*)k60_SRAM_END);
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/* init scheduler system */
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rt_system_scheduler_init();
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/* init all device */
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rt_device_init_all();
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/* init application */
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rt_application_init();
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#ifdef RT_USING_FINSH
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/* init finsh */
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finsh_system_init();
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finsh_set_device( FINSH_DEVICE_NAME );
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#endif
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/* init timer thread */
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rt_system_timer_thread_init();
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/* init idle thread */
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rt_thread_idle_init();
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/* start scheduler */
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rt_system_scheduler_start();
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/* never reach here */
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return ;
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}
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int main(void)
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{
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/* disable interrupt first */
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rt_hw_interrupt_disable();
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/* startup RT-Thread RTOS */
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rtthread_startup();
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return 0;
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}
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/*@}*/
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@ -0,0 +1,12 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'drivers')
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src = Glob('*.c')
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src += Glob('*.s')
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,88 @@
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
|
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-11 reynolds port to TWR-K60F120M
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <MK60F12.H>
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#include "board.h"
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#include "drv_uart.h"
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/**
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* @addtogroup K60
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*/
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/*@{*/
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/*******************************************************************************
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* Function Name : NVIC_Configuration
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* Description : Configures Vector Table base location.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void NVIC_Configuration(void)
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{
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}
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/*******************************************************************************
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* Function Name : SysTick_Configuration
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* Description : Configures the SysTick for OS tick.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void SysTick_Configuration(void)
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{
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SystemCoreClockUpdate(); /* Update Core Clock Frequency */
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SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); /* Generate interrupt each 1 ms */
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}
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial Tower board.
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*/
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void rt_hw_board_init()
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{
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/* NVIC Configuration */
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NVIC_Configuration();
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/* Configure the SysTick */
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SysTick_Configuration();
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rt_hw_uart_init();
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(CONSOLE_DEVICE);
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#endif
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}
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/*@}*/
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@ -0,0 +1,58 @@
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/*
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* File : board.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
|
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*
|
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* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
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* Date Author Notes
|
||||
* 2013-07-11 reynolds port to TWR-K60F120M
|
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*/
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// <<< Use Configuration Wizard in Context Menu >>>
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <MK60F12.H>
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/* board configuration */
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// <o> Internal SRAM memory size[Kbytes] <8-64>
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// <i>Default: 64
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#define k60_SRAM_SIZE 128
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#define k60_SRAM_END (0x20000000 + (k60_SRAM_SIZE * 1024)/2)
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//#define RT_USING_UART1
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#define RT_USING_UART5
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//#define RT_USING_UART3
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// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
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// <i>Default: 1
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#define k60_CONSOLE_USART 5
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void rt_hw_board_init(void);
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#if k60_CONSOLE_USART == 0
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#define CONSOLE_DEVICE "no"
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#elif k60_CONSOLE_USART == 1
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#define CONSOLE_DEVICE "uart1"
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#elif k60_CONSOLE_USART == 2
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#define CONSOLE_DEVICE "uart2"
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#elif k60_CONSOLE_USART == 3
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#define CONSOLE_DEVICE "uart3"
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#elif k60_CONSOLE_USART == 4
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#define CONSOLE_DEVICE "uart4"
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#elif k60_CONSOLE_USART == 5
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#define CONSOLE_DEVICE "uart5"
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#endif
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#define FINSH_DEVICE_NAME CONSOLE_DEVICE
|
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|
||||
|
||||
#endif
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||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
|
@ -0,0 +1,219 @@
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/*
|
||||
* File : drv_uart.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-11 reynolds port to TWR-K60F120M
|
||||
*/
|
||||
|
||||
|
||||
#include "drv_uart.h"
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||||
|
||||
static struct rt_serial_device _k60_serial; //abstracted serial for RTT
|
||||
static struct serial_ringbuffer _k60_int_rx; //UART send buffer area
|
||||
|
||||
struct k60_serial_device
|
||||
{
|
||||
/* UART base address */
|
||||
UART_Type *baseAddress;
|
||||
|
||||
/* UART IRQ Number */
|
||||
int irq_num;
|
||||
|
||||
/* device config */
|
||||
struct serial_configure config;
|
||||
};
|
||||
|
||||
//hardware abstract device
|
||||
static struct k60_serial_device _k60_node =
|
||||
{
|
||||
(UART_Type *)UART5,
|
||||
k60_uasrt_irq_num,
|
||||
};
|
||||
|
||||
static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
unsigned int reg_C1 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2;
|
||||
unsigned int cal_SBR = 0;
|
||||
UART_Type *uart_reg;
|
||||
|
||||
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
cal_SBR = 60000000 / (16 * cfg->baud_rate);
|
||||
reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
|
||||
reg_BDL = cal_SBR & 0x00FF;
|
||||
|
||||
//calc baud_rate
|
||||
reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
|
||||
reg_BDL = cal_SBR & 0x00FF;
|
||||
|
||||
//calc bit_order
|
||||
if (cfg->bit_order == BIT_ORDER_LSB)
|
||||
reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
|
||||
else if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
|
||||
|
||||
//calc data_bits
|
||||
if (cfg->data_bits == DATA_BITS_8)
|
||||
reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
|
||||
else if (cfg->data_bits == DATA_BITS_9)
|
||||
reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
|
||||
|
||||
//clac parity
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
reg_C1 &= ~(UART_C1_PE_MASK<<UART_C1_PE_SHIFT);
|
||||
else
|
||||
{
|
||||
reg_C1 &= ~(UART_C1_PE_MASK<<UART_C1_PE_SHIFT);
|
||||
|
||||
if (cfg->parity == PARITY_ODD)
|
||||
reg_C1 |= UART_C1_PT_MASK<<UART_C1_PT_SHIFT;
|
||||
if (cfg->parity == PARITY_EVEN)
|
||||
reg_C1 &= ~(UART_C1_PT_MASK<<UART_C1_PT_SHIFT);
|
||||
}
|
||||
|
||||
switch( (int)uart_reg)
|
||||
{
|
||||
case UART5_BASE:
|
||||
|
||||
//set UART5 clock
|
||||
SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;//Enable UART gate clocking
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;//Enable PORTE gate clocking
|
||||
|
||||
//set UART5 pin
|
||||
PORTE->PCR[ 8] = (3UL << 8); //Pin mux configured as ALT3
|
||||
PORTE->PCR[ 9] = (3UL << 8); //Pin mux configured as ALT3
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
uart_reg->BDH = reg_BDH;
|
||||
uart_reg->BDL = reg_BDL;
|
||||
uart_reg->C1 = reg_C1;
|
||||
uart_reg->S2 = reg_S2;
|
||||
|
||||
uart_reg->S2 = 0;
|
||||
uart_reg->C3 = 0;
|
||||
|
||||
uart_reg->RWFIFO = UART_RWFIFO_RXWATER(1);
|
||||
uart_reg->TWFIFO = UART_TWFIFO_TXWATER(0);
|
||||
|
||||
uart_reg->C2 = UART_C2_RE_MASK | //Receiver enable
|
||||
UART_C2_TE_MASK; //Transmitter enable
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
UART_Type *uart_reg;
|
||||
int uart_irq_num = 0;
|
||||
|
||||
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
uart_irq_num = ((struct k60_serial_device *)serial->parent.user_data)->irq_num;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
uart_reg->C2 &= ~UART_C2_RIE_MASK;
|
||||
//disable NVIC
|
||||
NVICICER1 |= 1 << (uart_irq_num % 32);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
uart_reg->C2 |= UART_C2_RIE_MASK;
|
||||
//enable NVIC,we are sure uart's NVIC vector is in NVICICPR1
|
||||
NVICICPR1 |= 1 << (uart_irq_num % 32);
|
||||
NVICISER1 |= 1 << (uart_irq_num % 32);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SUSPEND:
|
||||
/* suspend device */
|
||||
uart_reg->C2 &= ~(UART_C2_RE_MASK | //Receiver enable
|
||||
UART_C2_TE_MASK); //Transmitter enable
|
||||
break;
|
||||
case RT_DEVICE_CTRL_RESUME:
|
||||
/* resume device */
|
||||
uart_reg->C2 = UART_C2_RE_MASK | //Receiver enable
|
||||
UART_C2_TE_MASK; //Transmitter enable
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int _putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
UART_Type *uart_reg;
|
||||
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
|
||||
while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
|
||||
uart_reg->D = (c & 0xFF);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int _getc(struct rt_serial_device *serial)
|
||||
{
|
||||
UART_Type *uart_reg;
|
||||
uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
|
||||
|
||||
if (uart_reg->S1 & UART_S1_RDRF_MASK)
|
||||
return (uart_reg->D);
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops _k60_ops =
|
||||
{
|
||||
_configure,
|
||||
_control,
|
||||
_putc,
|
||||
_getc,
|
||||
};
|
||||
|
||||
|
||||
void UART5_RX_TX_IRQHandler(void)
|
||||
{
|
||||
rt_hw_serial_isr((struct rt_serial_device*)&_k60_serial);
|
||||
}
|
||||
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config;
|
||||
|
||||
/* fake configuration */
|
||||
config.baud_rate = BAUD_RATE_115200;
|
||||
config.bit_order = BIT_ORDER_LSB;
|
||||
config.data_bits = DATA_BITS_8;
|
||||
config.parity = PARITY_NONE;
|
||||
config.stop_bits = STOP_BITS_1;
|
||||
config.invert = NRZ_NORMAL;
|
||||
|
||||
_k60_serial.ops = &_k60_ops;
|
||||
_k60_serial.int_rx = &_k60_int_rx;
|
||||
_k60_serial.config = config;
|
||||
|
||||
rt_hw_serial_register(&_k60_serial, "uart5",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
(void*)&_k60_node);
|
||||
|
||||
rt_device_control(&_k60_serial.parent, RT_DEVICE_CTRL_SET_INT, 0);
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while(*str != '\0')
|
||||
{
|
||||
if (*str == '\n')
|
||||
_putc(&_k60_serial,'\r');
|
||||
_putc(&_k60_serial,*str);
|
||||
str++;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* File : drv_uart.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-11 reynolds port to TWR-K60F120M
|
||||
*/
|
||||
|
||||
#ifndef DRV_UART_H
|
||||
#define DRV_UART_H
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <MK60F12.H>
|
||||
|
||||
#include <drivers/serial.h>
|
||||
|
||||
|
||||
#define k60_uasrt_irq_num (55)
|
||||
|
||||
void rt_hw_uart_init(void);
|
||||
|
||||
//for kernel debug when console not registered
|
||||
void rt_hw_console_output(const char *str);
|
||||
|
||||
#endif /* end of include guard: DRV_UART_H */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* File : led.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-11 reynolds port to TWR-K60F120M
|
||||
*/
|
||||
|
||||
#include <MK60F12.H>
|
||||
#include "led.h"
|
||||
|
||||
const rt_uint32_t led_mask[] = { 1 << 11, 1 << 28, 1 << 29, 1 << 10 };
|
||||
|
||||
void rt_hw_led_init(void)
|
||||
{
|
||||
SIM->SCGC5 |= (1UL << 9); //Enable Port A Clock
|
||||
PORTA->PCR[10] = (1UL << 8); //PTA10 is GPIO pin
|
||||
PORTA->PCR[11] = (1UL << 8); //PTA11 is GPIO pin
|
||||
PORTA->PCR[28] = (1UL << 8); //PTA28 is GPIO pin
|
||||
PORTA->PCR[29] = (1UL << 8); //PTA29 is GPIO pin
|
||||
|
||||
/* Switch LEDs off and enable output*/
|
||||
PTA->PDOR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
|
||||
PTA->PDDR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
|
||||
}
|
||||
|
||||
void rt_hw_led_uninit(void)
|
||||
{
|
||||
PORTA->PCR[10] = 0; //PTA10 is at reset state
|
||||
PORTA->PCR[11] = 0; //PTA11 is at reset state
|
||||
PORTA->PCR[28] = 0; //PTA28 is at reset state
|
||||
PORTA->PCR[29] = 0; //PTA29 is at reset state
|
||||
}
|
||||
|
||||
void rt_hw_led_on(rt_uint32_t n)
|
||||
{
|
||||
if (n < LED_MAX)
|
||||
{
|
||||
PTA->PCOR = led_mask[n];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void rt_hw_led_off(rt_uint32_t n)
|
||||
{
|
||||
if (n < LED_MAX) {
|
||||
PTA->PSOR = led_mask[n];
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* File : led.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-11 reynolds port to TWR-K60F120M
|
||||
*/
|
||||
|
||||
#ifndef __LED_H__
|
||||
#define __LED_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define LED_MAX 4
|
||||
|
||||
void rt_hw_led_init(void);
|
||||
void rt_hw_led_uninit(void);
|
||||
void rt_hw_led_on(rt_uint32_t n);
|
||||
void rt_hw_led_off(rt_uint32_t n);
|
||||
|
||||
#endif /* end of __LED_H__ */
|
||||
|
|
@ -0,0 +1,774 @@
|
|||
;/*****************************************************************************
|
||||
; * @file: startup_MK60F12.s
|
||||
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
|
||||
; * MK60F12
|
||||
; * @version: 1.1
|
||||
; * @date: 2011-11-3
|
||||
; *
|
||||
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
;*
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA0_DMA16_IRQHandler ; DMA channel 0/16 transfer complete interrupt
|
||||
DCD DMA1_DMA17_IRQHandler ; DMA channel 1/17 transfer complete interrupt
|
||||
DCD DMA2_DMA18_IRQHandler ; DMA channel 2/18 transfer complete interrupt
|
||||
DCD DMA3_DMA19_IRQHandler ; DMA channel 3/19 transfer complete interrupt
|
||||
DCD DMA4_DMA20_IRQHandler ; DMA channel 4/20 transfer complete interrupt
|
||||
DCD DMA5_DMA21_IRQHandler ; DMA channel 5/21 transfer complete interrupt
|
||||
DCD DMA6_DMA22_IRQHandler ; DMA channel 6/22 transfer complete interrupt
|
||||
DCD DMA7_DMA23_IRQHandler ; DMA channel 7/23 transfer complete interrupt
|
||||
DCD DMA8_DMA24_IRQHandler ; DMA channel 8/24 transfer complete interrupt
|
||||
DCD DMA9_DMA25_IRQHandler ; DMA channel 9/25 transfer complete interrupt
|
||||
DCD DMA10_DMA26_IRQHandler ; DMA channel 10/26 transfer complete interrupt
|
||||
DCD DMA11_DMA27_IRQHandler ; DMA channel 11/27 transfer complete interrupt
|
||||
DCD DMA12_DMA28_IRQHandler ; DMA channel 12/28 transfer complete interrupt
|
||||
DCD DMA13_DMA29_IRQHandler ; DMA channel 13/29 transfer complete interrupt
|
||||
DCD DMA14_DMA30_IRQHandler ; DMA channel 14/30 transfer complete interrupt
|
||||
DCD DMA15_DMA31_IRQHandler ; DMA channel 15/31 transfer complete interrupt
|
||||
DCD DMA_Error_IRQHandler ; DMA error interrupt
|
||||
DCD MCM_IRQHandler ; Normal interrupt
|
||||
DCD FTFE_IRQHandler ; FTFE interrupt
|
||||
DCD Read_Collision_IRQHandler ; Read collision interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD Watchdog_IRQHandler ; WDOG interrupt
|
||||
DCD RNG_IRQHandler ; RNGB interrupt
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ; SPI0 interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 interrupt
|
||||
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
|
||||
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
|
||||
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
|
||||
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
|
||||
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
|
||||
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
|
||||
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
|
||||
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
|
||||
DCD CAN1_ORed_Message_buffer_IRQHandler ; CAN1 OR'd message buffers interrupt
|
||||
DCD CAN1_Bus_Off_IRQHandler ; CAN1 bus off interrupt
|
||||
DCD CAN1_Error_IRQHandler ; CAN1 error interrupt
|
||||
DCD CAN1_Tx_Warning_IRQHandler ; CAN1 Tx warning interrupt
|
||||
DCD CAN1_Rx_Warning_IRQHandler ; CAN1 Rx warning interrupt
|
||||
DCD CAN1_Wake_Up_IRQHandler ; CAN1 wake up interrupt
|
||||
DCD Reserved59_IRQHandler ; Reserved interrupt 59
|
||||
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
|
||||
DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
|
||||
DCD UART0_ERR_IRQHandler ; UART0 error interrupt
|
||||
DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
|
||||
DCD UART1_ERR_IRQHandler ; UART1 error interrupt
|
||||
DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
|
||||
DCD UART2_ERR_IRQHandler ; UART2 error interrupt
|
||||
DCD UART3_RX_TX_IRQHandler ; UART3 receive/transmit interrupt
|
||||
DCD UART3_ERR_IRQHandler ; UART3 error interrupt
|
||||
DCD UART4_RX_TX_IRQHandler ; UART4 receive/transmit interrupt
|
||||
DCD UART4_ERR_IRQHandler ; UART4 error interrupt
|
||||
DCD UART5_RX_TX_IRQHandler ; UART5 receive/transmit interrupt
|
||||
DCD UART5_ERR_IRQHandler ; UART5 error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD CMP1_IRQHandler ; CMP1 interrupt
|
||||
DCD CMP2_IRQHandler ; CMP2 interrupt
|
||||
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
|
||||
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
|
||||
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
|
||||
DCD CMT_IRQHandler ; CMT interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
|
||||
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
|
||||
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
|
||||
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
|
||||
DCD PDB0_IRQHandler ; PDB0 interrupt
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD USBDCD_IRQHandler ; USBDCD interrupt
|
||||
DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 timer interrupt
|
||||
DCD ENET_Transmit_IRQHandler ; Ethernet MAC transmit interrupt
|
||||
DCD ENET_Receive_IRQHandler ; Ethernet MAC receive interrupt
|
||||
DCD ENET_Error_IRQHandler ; Ethernet MAC error and miscelaneous interrupt
|
||||
DCD Reserved95_IRQHandler ; Reserved interrupt 95
|
||||
DCD SDHC_IRQHandler ; SDHC interrupt
|
||||
DCD DAC0_IRQHandler ; DAC0 interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 interrupt
|
||||
DCD TSI0_IRQHandler ; TSI0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD Reserved102_IRQHandler ; Reserved interrupt 102
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTB_IRQHandler ; Port B interrupt
|
||||
DCD PORTC_IRQHandler ; Port C interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
DCD PORTE_IRQHandler ; Port E interrupt
|
||||
DCD PORTF_IRQHandler ; Port F interrupt
|
||||
DCD Reserved109_IRQHandler ; Reserved interrupt 109
|
||||
DCD SWI_IRQHandler ; Software interrupt
|
||||
DCD NFC_IRQHandler ; NAND flash controller interrupt
|
||||
DCD USBHS_IRQHandler ; USB high speed OTG interrupt
|
||||
DCD Reserved113_IRQHandler ; Reserved interrupt 113
|
||||
DCD CMP3_IRQHandler ; CMP3 interrupt
|
||||
DCD Reserved115_IRQHandler ; Reserved interrupt 115
|
||||
DCD Reserved116_IRQHandler ; Reserved interrupt 116
|
||||
DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 interrupt
|
||||
DCD ADC3_IRQHandler ; ADC3 interrupt
|
||||
DCD I2S1_Tx_IRQHandler ; I2S1 transmit interrupt
|
||||
DCD I2S1_Rx_IRQHandler ; I2S1 receive interrupt
|
||||
DCD DefaultISR ; 122
|
||||
DCD DefaultISR ; 123
|
||||
DCD DefaultISR ; 124
|
||||
DCD DefaultISR ; 125
|
||||
DCD DefaultISR ; 126
|
||||
DCD DefaultISR ; 127
|
||||
DCD DefaultISR ; 128
|
||||
DCD DefaultISR ; 129
|
||||
DCD DefaultISR ; 130
|
||||
DCD DefaultISR ; 131
|
||||
DCD DefaultISR ; 132
|
||||
DCD DefaultISR ; 133
|
||||
DCD DefaultISR ; 134
|
||||
DCD DefaultISR ; 135
|
||||
DCD DefaultISR ; 136
|
||||
DCD DefaultISR ; 137
|
||||
DCD DefaultISR ; 138
|
||||
DCD DefaultISR ; 139
|
||||
DCD DefaultISR ; 140
|
||||
DCD DefaultISR ; 141
|
||||
DCD DefaultISR ; 142
|
||||
DCD DefaultISR ; 143
|
||||
DCD DefaultISR ; 144
|
||||
DCD DefaultISR ; 145
|
||||
DCD DefaultISR ; 146
|
||||
DCD DefaultISR ; 147
|
||||
DCD DefaultISR ; 148
|
||||
DCD DefaultISR ; 149
|
||||
DCD DefaultISR ; 150
|
||||
DCD DefaultISR ; 151
|
||||
DCD DefaultISR ; 152
|
||||
DCD DefaultISR ; 153
|
||||
DCD DefaultISR ; 154
|
||||
DCD DefaultISR ; 155
|
||||
DCD DefaultISR ; 156
|
||||
DCD DefaultISR ; 157
|
||||
DCD DefaultISR ; 158
|
||||
DCD DefaultISR ; 159
|
||||
DCD DefaultISR ; 160
|
||||
DCD DefaultISR ; 161
|
||||
DCD DefaultISR ; 162
|
||||
DCD DefaultISR ; 163
|
||||
DCD DefaultISR ; 164
|
||||
DCD DefaultISR ; 165
|
||||
DCD DefaultISR ; 166
|
||||
DCD DefaultISR ; 167
|
||||
DCD DefaultISR ; 168
|
||||
DCD DefaultISR ; 169
|
||||
DCD DefaultISR ; 170
|
||||
DCD DefaultISR ; 171
|
||||
DCD DefaultISR ; 172
|
||||
DCD DefaultISR ; 173
|
||||
DCD DefaultISR ; 174
|
||||
DCD DefaultISR ; 175
|
||||
DCD DefaultISR ; 176
|
||||
DCD DefaultISR ; 177
|
||||
DCD DefaultISR ; 178
|
||||
DCD DefaultISR ; 179
|
||||
DCD DefaultISR ; 180
|
||||
DCD DefaultISR ; 181
|
||||
DCD DefaultISR ; 182
|
||||
DCD DefaultISR ; 183
|
||||
DCD DefaultISR ; 184
|
||||
DCD DefaultISR ; 185
|
||||
DCD DefaultISR ; 186
|
||||
DCD DefaultISR ; 187
|
||||
DCD DefaultISR ; 188
|
||||
DCD DefaultISR ; 189
|
||||
DCD DefaultISR ; 190
|
||||
DCD DefaultISR ; 191
|
||||
DCD DefaultISR ; 192
|
||||
DCD DefaultISR ; 193
|
||||
DCD DefaultISR ; 194
|
||||
DCD DefaultISR ; 195
|
||||
DCD DefaultISR ; 196
|
||||
DCD DefaultISR ; 197
|
||||
DCD DefaultISR ; 198
|
||||
DCD DefaultISR ; 199
|
||||
DCD DefaultISR ; 200
|
||||
DCD DefaultISR ; 201
|
||||
DCD DefaultISR ; 202
|
||||
DCD DefaultISR ; 203
|
||||
DCD DefaultISR ; 204
|
||||
DCD DefaultISR ; 205
|
||||
DCD DefaultISR ; 206
|
||||
DCD DefaultISR ; 207
|
||||
DCD DefaultISR ; 208
|
||||
DCD DefaultISR ; 209
|
||||
DCD DefaultISR ; 210
|
||||
DCD DefaultISR ; 211
|
||||
DCD DefaultISR ; 212
|
||||
DCD DefaultISR ; 213
|
||||
DCD DefaultISR ; 214
|
||||
DCD DefaultISR ; 215
|
||||
DCD DefaultISR ; 216
|
||||
DCD DefaultISR ; 217
|
||||
DCD DefaultISR ; 218
|
||||
DCD DefaultISR ; 219
|
||||
DCD DefaultISR ; 220
|
||||
DCD DefaultISR ; 221
|
||||
DCD DefaultISR ; 222
|
||||
DCD DefaultISR ; 223
|
||||
DCD DefaultISR ; 224
|
||||
DCD DefaultISR ; 225
|
||||
DCD DefaultISR ; 226
|
||||
DCD DefaultISR ; 227
|
||||
DCD DefaultISR ; 228
|
||||
DCD DefaultISR ; 229
|
||||
DCD DefaultISR ; 230
|
||||
DCD DefaultISR ; 231
|
||||
DCD DefaultISR ; 232
|
||||
DCD DefaultISR ; 233
|
||||
DCD DefaultISR ; 234
|
||||
DCD DefaultISR ; 235
|
||||
DCD DefaultISR ; 236
|
||||
DCD DefaultISR ; 237
|
||||
DCD DefaultISR ; 238
|
||||
DCD DefaultISR ; 239
|
||||
DCD DefaultISR ; 240
|
||||
DCD DefaultISR ; 241
|
||||
DCD DefaultISR ; 242
|
||||
DCD DefaultISR ; 243
|
||||
DCD DefaultISR ; 244
|
||||
DCD DefaultISR ; 245
|
||||
DCD DefaultISR ; 246
|
||||
DCD DefaultISR ; 247
|
||||
DCD DefaultISR ; 248
|
||||
DCD DefaultISR ; 249
|
||||
DCD DefaultISR ; 250
|
||||
DCD DefaultISR ; 251
|
||||
DCD DefaultISR ; 252
|
||||
DCD DefaultISR ; 253
|
||||
DCD DefaultISR ; 254
|
||||
DCD DefaultISR ; 255
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Key 0 <0x0-0xFF:2>
|
||||
; <o1> Backdoor Key 1 <0x0-0xFF:2>
|
||||
; <o2> Backdoor Key 2 <0x0-0xFF:2>
|
||||
; <o3> Backdoor Key 3 <0x0-0xFF:2>
|
||||
; <o4> Backdoor Key 4 <0x0-0xFF:2>
|
||||
; <o5> Backdoor Key 5 <0x0-0xFF:2>
|
||||
; <o6> Backdoor Key 6 <0x0-0xFF:2>
|
||||
; <o7> Backdoor Key 7 <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program flash protection bytes
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Data flash protection byte (FDPROT)
|
||||
; <i> Each bit protects a 1/8 region of the data flash memory.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FDPROT.0
|
||||
; <o.1> FDPROT.1
|
||||
; <o.2> FDPROT.2
|
||||
; <o.3> FDPROT.3
|
||||
; <o.4> FDPROT.4
|
||||
; <o.5> FDPROT.5
|
||||
; <o.6> FDPROT.6
|
||||
; <o.7> FDPROT.7
|
||||
nFDPROT EQU 0x00
|
||||
FDPROT EQU nFDPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> EEPROM protection byte (FEPROT)
|
||||
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
|
||||
; <i> (Program flash only devices: Reserved)
|
||||
; <o.0> FEPROT.0
|
||||
; <o.1> FEPROT.1
|
||||
; <o.2> FEPROT.2
|
||||
; <o.3> FEPROT.3
|
||||
; <o.4> FEPROT.4
|
||||
; <o.5> FEPROT.5
|
||||
; <o.6> FEPROT.6
|
||||
; <o.7> FEPROT.7
|
||||
nFEPROT EQU 0x00
|
||||
FEPROT EQU nFEPROT:EOR:0xFF
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT
|
||||
; <0=> Low-power boot
|
||||
; <1=> normal boot
|
||||
; <o.1> EZPORT_DIS
|
||||
; <0=> EzPort operation is enabled
|
||||
; <1=> EzPort operation is disabled
|
||||
FOPT EQU 0xFF
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <i> Mass Erase Enable Bits
|
||||
; <i> Enables and disables mass erase capability of the FTFL module
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor key Security Enable
|
||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DMA0_DMA16_IRQHandler [WEAK]
|
||||
EXPORT DMA1_DMA17_IRQHandler [WEAK]
|
||||
EXPORT DMA2_DMA18_IRQHandler [WEAK]
|
||||
EXPORT DMA3_DMA19_IRQHandler [WEAK]
|
||||
EXPORT DMA4_DMA20_IRQHandler [WEAK]
|
||||
EXPORT DMA5_DMA21_IRQHandler [WEAK]
|
||||
EXPORT DMA6_DMA22_IRQHandler [WEAK]
|
||||
EXPORT DMA7_DMA23_IRQHandler [WEAK]
|
||||
EXPORT DMA8_DMA24_IRQHandler [WEAK]
|
||||
EXPORT DMA9_DMA25_IRQHandler [WEAK]
|
||||
EXPORT DMA10_DMA26_IRQHandler [WEAK]
|
||||
EXPORT DMA11_DMA27_IRQHandler [WEAK]
|
||||
EXPORT DMA12_DMA28_IRQHandler [WEAK]
|
||||
EXPORT DMA13_DMA29_IRQHandler [WEAK]
|
||||
EXPORT DMA14_DMA30_IRQHandler [WEAK]
|
||||
EXPORT DMA15_DMA31_IRQHandler [WEAK]
|
||||
EXPORT DMA_Error_IRQHandler [WEAK]
|
||||
EXPORT MCM_IRQHandler [WEAK]
|
||||
EXPORT FTFE_IRQHandler [WEAK]
|
||||
EXPORT Read_Collision_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT LLW_IRQHandler [WEAK]
|
||||
EXPORT Watchdog_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
||||
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
||||
EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Error_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
|
||||
EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
|
||||
EXPORT Reserved59_IRQHandler [WEAK]
|
||||
EXPORT UART0_LON_IRQHandler [WEAK]
|
||||
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART0_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART1_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART2_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART3_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART3_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART4_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART4_ERR_IRQHandler [WEAK]
|
||||
EXPORT UART5_RX_TX_IRQHandler [WEAK]
|
||||
EXPORT UART5_ERR_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT CMP1_IRQHandler [WEAK]
|
||||
EXPORT CMP2_IRQHandler [WEAK]
|
||||
EXPORT FTM0_IRQHandler [WEAK]
|
||||
EXPORT FTM1_IRQHandler [WEAK]
|
||||
EXPORT FTM2_IRQHandler [WEAK]
|
||||
EXPORT CMT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||
EXPORT PIT0_IRQHandler [WEAK]
|
||||
EXPORT PIT1_IRQHandler [WEAK]
|
||||
EXPORT PIT2_IRQHandler [WEAK]
|
||||
EXPORT PIT3_IRQHandler [WEAK]
|
||||
EXPORT PDB0_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USBDCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_1588_Timer_IRQHandler [WEAK]
|
||||
EXPORT ENET_Transmit_IRQHandler [WEAK]
|
||||
EXPORT ENET_Receive_IRQHandler [WEAK]
|
||||
EXPORT ENET_Error_IRQHandler [WEAK]
|
||||
EXPORT Reserved95_IRQHandler [WEAK]
|
||||
EXPORT SDHC_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT TSI0_IRQHandler [WEAK]
|
||||
EXPORT MCG_IRQHandler [WEAK]
|
||||
EXPORT LPTimer_IRQHandler [WEAK]
|
||||
EXPORT Reserved102_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTB_IRQHandler [WEAK]
|
||||
EXPORT PORTC_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT PORTE_IRQHandler [WEAK]
|
||||
EXPORT PORTF_IRQHandler [WEAK]
|
||||
EXPORT Reserved109_IRQHandler [WEAK]
|
||||
EXPORT SWI_IRQHandler [WEAK]
|
||||
EXPORT NFC_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT Reserved113_IRQHandler [WEAK]
|
||||
EXPORT CMP3_IRQHandler [WEAK]
|
||||
EXPORT Reserved115_IRQHandler [WEAK]
|
||||
EXPORT Reserved116_IRQHandler [WEAK]
|
||||
EXPORT FTM3_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT I2S1_Tx_IRQHandler [WEAK]
|
||||
EXPORT I2S1_Rx_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
|
||||
DMA0_DMA16_IRQHandler
|
||||
DMA1_DMA17_IRQHandler
|
||||
DMA2_DMA18_IRQHandler
|
||||
DMA3_DMA19_IRQHandler
|
||||
DMA4_DMA20_IRQHandler
|
||||
DMA5_DMA21_IRQHandler
|
||||
DMA6_DMA22_IRQHandler
|
||||
DMA7_DMA23_IRQHandler
|
||||
DMA8_DMA24_IRQHandler
|
||||
DMA9_DMA25_IRQHandler
|
||||
DMA10_DMA26_IRQHandler
|
||||
DMA11_DMA27_IRQHandler
|
||||
DMA12_DMA28_IRQHandler
|
||||
DMA13_DMA29_IRQHandler
|
||||
DMA14_DMA30_IRQHandler
|
||||
DMA15_DMA31_IRQHandler
|
||||
DMA_Error_IRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFE_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
RNG_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
CAN0_ORed_Message_buffer_IRQHandler
|
||||
CAN0_Bus_Off_IRQHandler
|
||||
CAN0_Error_IRQHandler
|
||||
CAN0_Tx_Warning_IRQHandler
|
||||
CAN0_Rx_Warning_IRQHandler
|
||||
CAN0_Wake_Up_IRQHandler
|
||||
I2S0_Tx_IRQHandler
|
||||
I2S0_Rx_IRQHandler
|
||||
CAN1_ORed_Message_buffer_IRQHandler
|
||||
CAN1_Bus_Off_IRQHandler
|
||||
CAN1_Error_IRQHandler
|
||||
CAN1_Tx_Warning_IRQHandler
|
||||
CAN1_Rx_Warning_IRQHandler
|
||||
CAN1_Wake_Up_IRQHandler
|
||||
Reserved59_IRQHandler
|
||||
UART0_LON_IRQHandler
|
||||
UART0_RX_TX_IRQHandler
|
||||
UART0_ERR_IRQHandler
|
||||
UART1_RX_TX_IRQHandler
|
||||
UART1_ERR_IRQHandler
|
||||
UART2_RX_TX_IRQHandler
|
||||
UART2_ERR_IRQHandler
|
||||
UART3_RX_TX_IRQHandler
|
||||
UART3_ERR_IRQHandler
|
||||
UART4_RX_TX_IRQHandler
|
||||
UART4_ERR_IRQHandler
|
||||
UART5_RX_TX_IRQHandler
|
||||
UART5_ERR_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
CMP2_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0_IRQHandler
|
||||
PIT1_IRQHandler
|
||||
PIT2_IRQHandler
|
||||
PIT3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
ENET_1588_Timer_IRQHandler
|
||||
ENET_Transmit_IRQHandler
|
||||
ENET_Receive_IRQHandler
|
||||
ENET_Error_IRQHandler
|
||||
Reserved95_IRQHandler
|
||||
SDHC_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
Reserved102_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
PORTF_IRQHandler
|
||||
Reserved109_IRQHandler
|
||||
SWI_IRQHandler
|
||||
NFC_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
Reserved113_IRQHandler
|
||||
CMP3_IRQHandler
|
||||
Reserved115_IRQHandler
|
||||
Reserved116_IRQHandler
|
||||
FTM3_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
I2S1_Tx_IRQHandler
|
||||
I2S1_Rx_IRQHandler
|
||||
DefaultISR
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Compilers: ARM Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K60P144M150SF3RM, Rev. 2, Dec 2011
|
||||
** Version: rev. 1.3, 2012-04-13
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2011-08-24)
|
||||
** Initial version
|
||||
** - rev. 1.1 (2011-11-03)
|
||||
** Registers updated according to the new reference manual revision - Rev. 1, Oct 2011
|
||||
** Registers of the following modules have been updated - AXBS, CAN, I2S, MCG, MPU, NFC, RCM, RTC, SDHC, SIM, USBHS, WDOG
|
||||
** The following modules have been removed - DDR, DRY
|
||||
** - rev. 1.2 (2012-01-04)
|
||||
** Registers updated according to the new reference manual revision - Rev. 2, Dec 2011
|
||||
** EWM - INTEN bit in EWM_CTRL register has been added.
|
||||
** PDB - register PDB_PO0EN renamed to PRB_POEN.
|
||||
** PMC - BGEN bit in PMC_REGSC register has been removed.
|
||||
** SIM - several changes in SCGC registers. Bit USBHS in SOPT2 register removed.
|
||||
** UART - new bits RXOFE in regiter CFIFO and RXOF in register SFIFO.
|
||||
** - rev. 1.3 (2012-04-13)
|
||||
** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
|
||||
** Added new #define symbols <peripheralType>_BASE_PTRS.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file MK60F12
|
||||
* @version 1.3
|
||||
* @date 2012-04-13
|
||||
* @brief Device specific configuration file for MK60F12 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "MK60F12.h"
|
||||
|
||||
#define DISABLE_WDOG 1
|
||||
|
||||
|
||||
#define CLOCK_SETUP 1
|
||||
/* Predefined clock setups
|
||||
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
||||
Reference clock source for MCG module is the slow internal clock source 32.768kHz
|
||||
Core clock = 41.94MHz, BusClock = 41.94MHz
|
||||
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
|
||||
Reference clock source for MCG module is an external reference clock source 50MHz
|
||||
Core clock = 120MHz, BusClock = 60MHz
|
||||
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
|
||||
Core clock/Bus clock derived directly from an external reference clock source 50MHz with no multiplication
|
||||
Core clock = 50MHz, BusClock = 50MHz
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clock source values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
|
||||
#define CPU_XTAL1_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
|
||||
#define CPU_XTAL1_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
#define CPU_XTAL0_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
|
||||
#define CPU_XTAL1_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 50000000u /* Default System clock value */
|
||||
#endif /* (CLOCK_SETUP == 2) */
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
#if (DISABLE_WDOG)
|
||||
/* Disable the WDOG module */
|
||||
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
|
||||
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
|
||||
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
|
||||
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
|
||||
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
|
||||
WDOG->STCTRLH = (uint16_t)0x01D2u;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
/* System clock initialization */
|
||||
#if (CLOCK_SETUP == 0)
|
||||
/* SIM_SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
|
||||
/* SIM_SOPT2: PLLFLLSEL=0 */
|
||||
SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
|
||||
/* SIM_SOPT1: OSC32KSEL=0 */
|
||||
SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
|
||||
/* SIM_SCGC1: OSC1=1 */
|
||||
SIM->SCGC1 |= (uint32_t)0x20UL;
|
||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
|
||||
/* Switch to FEI Mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x06U;
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x20U;
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=1 */
|
||||
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
|
||||
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0->CR = (uint8_t)0x80U;
|
||||
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC1->CR = (uint8_t)0x80U;
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
|
||||
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
|
||||
MCG->C5 = (uint8_t)0x00U;
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U; /* 3 */
|
||||
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
|
||||
MCG->C11 = (uint8_t)0x00U; /* 3 */
|
||||
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
|
||||
MCG->C12 = (uint8_t)0x00U; /* 3 */
|
||||
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
|
||||
}
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
/* SIM_SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x01350000UL; /* Update system prescalers */
|
||||
/* SIM_SOPT2: PLLFLLSEL=1 */
|
||||
SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
|
||||
/* SIM_SOPT1: OSC32KSEL=0 */
|
||||
SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
|
||||
/* SIM_SCGC1: OSC1=1 */
|
||||
SIM->SCGC1 |= (uint32_t)0x20UL;
|
||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0->CR = (uint8_t)0x80U;
|
||||
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC1->CR = (uint8_t)0x80U;
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x20U;
|
||||
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0xAAU;
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
|
||||
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
|
||||
MCG->C5 = (uint8_t)0x04U;
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
|
||||
MCG->C6 = (uint8_t)0x08U;
|
||||
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
|
||||
MCG->C11 = (uint8_t)0x00U;
|
||||
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
|
||||
MCG->C12 = (uint8_t)0x00U;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to PBE Mode */
|
||||
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
|
||||
MCG->C6 = (uint8_t)0x48U;
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
|
||||
}
|
||||
/* Switch to PEE Mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x2AU;
|
||||
while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
|
||||
}
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
/* SIM_SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
|
||||
/* SIM_SOPT2: PLLFLLSEL=0 */
|
||||
SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
|
||||
/* SIM_SOPT1: OSC32KSEL=0 */
|
||||
SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
|
||||
/* SIM_SCGC1: OSC1=1 */
|
||||
SIM->SCGC1 |= (uint32_t)0x20UL;
|
||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0->CR = (uint8_t)0x80U;
|
||||
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC1->CR = (uint8_t)0x80U;
|
||||
/* MCG_C7: OSCSEL=0 */
|
||||
MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x20U;
|
||||
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0xAAU;
|
||||
/* MCG_C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
|
||||
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
|
||||
MCG->C5 = (uint8_t)0x00U;
|
||||
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U;
|
||||
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
|
||||
MCG->C11 = (uint8_t)0x00U;
|
||||
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
|
||||
MCG->C12 = (uint8_t)0x00U;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to BLPE Mode */
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x22U;
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
#endif /* (CLOCK_SETUP == 2) */
|
||||
|
||||
/* Disable MPU */
|
||||
MPU->CESR &= ~MPU_CESR_VLD_MASK;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
||||
uint8_t Divider;
|
||||
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
|
||||
/* Output of FLL or PLL is selected */
|
||||
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
|
||||
/* FLL is selected */
|
||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
|
||||
/* External reference clock is selected */
|
||||
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_XTAL0_CLK_HZ; /* System oscillator 0 drives MCG clock */
|
||||
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||||
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||||
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
||||
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
|
||||
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
|
||||
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
||||
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||||
/* Select correct multiplier to calculate the MCG output clock */
|
||||
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||||
case 0x0u:
|
||||
MCGOUTClock *= 640u;
|
||||
break;
|
||||
case 0x20u:
|
||||
MCGOUTClock *= 1280u;
|
||||
break;
|
||||
case 0x40u:
|
||||
MCGOUTClock *= 1920u;
|
||||
break;
|
||||
case 0x60u:
|
||||
MCGOUTClock *= 2560u;
|
||||
break;
|
||||
case 0x80u:
|
||||
MCGOUTClock *= 732u;
|
||||
break;
|
||||
case 0xA0u:
|
||||
MCGOUTClock *= 1464u;
|
||||
break;
|
||||
case 0xC0u:
|
||||
MCGOUTClock *= 2197u;
|
||||
break;
|
||||
case 0xE0u:
|
||||
MCGOUTClock *= 2929u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||||
/* PLL is selected */
|
||||
if ((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u) {
|
||||
/* PLL1 output is selected */
|
||||
if ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u) {
|
||||
/* OSC1 clock source used as an external reference clock */
|
||||
MCGOUTClock = CPU_XTAL1_CLK_HZ;
|
||||
} else { /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
|
||||
/* OSC0 clock source used as an external reference clock */
|
||||
MCGOUTClock = CPU_XTAL0_CLK_HZ;
|
||||
} /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
|
||||
Divider = (1u + (MCG->C11 & MCG_C11_PRDIV1_MASK));
|
||||
MCGOUTClock /= Divider; /* Calculate the PLL reference clock */
|
||||
Divider = ((MCG->C12 & MCG_C12_VDIV1_MASK) + 16u);
|
||||
MCGOUTClock = (MCGOUTClock * Divider) / 2u; /* Calculate the MCG output clock */
|
||||
} else { /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
|
||||
/* PLL0 output is selected */
|
||||
if ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u) {
|
||||
/* OSC1 clock source used as an external reference clock */
|
||||
MCGOUTClock = CPU_XTAL1_CLK_HZ;
|
||||
} else { /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
|
||||
/* OSC0 clock source used as an external reference clock */
|
||||
MCGOUTClock = CPU_XTAL0_CLK_HZ;
|
||||
} /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
|
||||
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
|
||||
MCGOUTClock /= Divider; /* Calculate the PLL reference clock */
|
||||
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 16u);
|
||||
MCGOUTClock = (MCGOUTClock * Divider) / 2u; /* Calculate the MCG output clock */
|
||||
} /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
|
||||
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
|
||||
/* Internal reference clock is selected */
|
||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
||||
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
|
||||
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
|
||||
/* External reference clock is selected */
|
||||
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_XTAL0_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||||
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||||
/* Reserved value */
|
||||
return;
|
||||
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||||
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
board info:
|
||||
Freescale Tower TWR-K60F120M
|
||||
http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-K60F120M
|
||||
with:
|
||||
TWR-SER
|
||||
http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-SER
|
||||
and TWR-ELEV
|
||||
http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-ELEV
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/* RT-Thread config file */
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
/* RT_NAME_MAX*/
|
||||
#define RT_NAME_MAX 8
|
||||
|
||||
/* RT_ALIGN_SIZE*/
|
||||
#define RT_ALIGN_SIZE 8
|
||||
|
||||
/* PRIORITY_MAX */
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
|
||||
/* Tick per Second */
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
|
||||
/* SECTION: RT_DEBUG */
|
||||
/* Thread Debug */
|
||||
#define RT_DEBUG
|
||||
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
|
||||
/* Using Hook */
|
||||
#define RT_USING_HOOK
|
||||
|
||||
#define IDLE_THREAD_STACK_SIZE 1024
|
||||
|
||||
/* Using Software Timer */
|
||||
/* #define RT_USING_TIMER_SOFT */
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
#define RT_TIMER_TICK_PER_SECOND 10
|
||||
|
||||
/* SECTION: IPC */
|
||||
/* Using Semaphore*/
|
||||
#define RT_USING_SEMAPHORE
|
||||
|
||||
/* Using Mutex */
|
||||
#define RT_USING_MUTEX
|
||||
|
||||
/* Using Event */
|
||||
#define RT_USING_EVENT
|
||||
|
||||
/* Using MailBox */
|
||||
#define RT_USING_MAILBOX
|
||||
|
||||
/* Using Message Queue */
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* SECTION: Memory Management */
|
||||
/* Using Memory Pool Management*/
|
||||
#define RT_USING_MEMPOOL
|
||||
|
||||
/* Using Dynamic Heap Management */
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Using Small MM */
|
||||
#define RT_USING_SMALL_MEM
|
||||
|
||||
/* "Using Device Driver Framework" default="true" */
|
||||
#define RT_USING_DEVICE
|
||||
/* Using IPC in Device Driver Framework" default="true" */
|
||||
#define RT_USING_DEVICE_IPC
|
||||
/* Using Serial Device Driver Framework" default="true" */
|
||||
#define RT_USING_SERIAL
|
||||
|
||||
|
||||
/* SECTION: Console options */
|
||||
#define RT_USING_CONSOLE
|
||||
/* the buffer size of console*/
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
|
||||
/* SECTION: finsh, a C-Express shell */
|
||||
#define RT_USING_FINSH
|
||||
/* Using symbol table */
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
|
||||
/* SECTION: device filesystem */
|
||||
/* #define RT_USING_DFS */
|
||||
//#define RT_USING_DFS_ELMFAT
|
||||
#define RT_DFS_ELM_WORD_ACCESS
|
||||
/* Reentrancy (thread safe) of the FatFs module. */
|
||||
#define RT_DFS_ELM_REENTRANT
|
||||
/* Number of volumes (logical drives) to be used. */
|
||||
#define RT_DFS_ELM_DRIVES 2
|
||||
/* #define RT_DFS_ELM_USE_LFN 1 */
|
||||
#define RT_DFS_ELM_MAX_LFN 255
|
||||
/* Maximum sector size to be handled. */
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
|
||||
|
||||
#define RT_USING_DFS_ROMFS
|
||||
|
||||
/* the max number of mounted filesystem */
|
||||
#define DFS_FILESYSTEMS_MAX 2
|
||||
/* the max number of opened files */
|
||||
#define DFS_FD_MAX 4
|
||||
|
||||
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
|
||||
/* #define RT_USING_LWIP */
|
||||
/* LwIP uses RT-Thread Memory Management */
|
||||
#define RT_LWIP_USING_RT_MEM
|
||||
/* Enable ICMP protocol*/
|
||||
#define RT_LWIP_ICMP
|
||||
/* Enable UDP protocol*/
|
||||
#define RT_LWIP_UDP
|
||||
/* Enable TCP protocol*/
|
||||
#define RT_LWIP_TCP
|
||||
/* Enable DNS */
|
||||
#define RT_LWIP_DNS
|
||||
|
||||
/* the number of simulatenously active TCP connections*/
|
||||
#define RT_LWIP_TCP_PCB_NUM 5
|
||||
|
||||
/* ip address of target*/
|
||||
#define RT_LWIP_IPADDR0 192
|
||||
#define RT_LWIP_IPADDR1 168
|
||||
#define RT_LWIP_IPADDR2 1
|
||||
#define RT_LWIP_IPADDR3 201
|
||||
|
||||
/* gateway address of target*/
|
||||
#define RT_LWIP_GWADDR0 192
|
||||
#define RT_LWIP_GWADDR1 168
|
||||
#define RT_LWIP_GWADDR2 1
|
||||
#define RT_LWIP_GWADDR3 1
|
||||
|
||||
/* mask address of target*/
|
||||
#define RT_LWIP_MSKADDR0 255
|
||||
#define RT_LWIP_MSKADDR1 255
|
||||
#define RT_LWIP_MSKADDR2 255
|
||||
#define RT_LWIP_MSKADDR3 0
|
||||
|
||||
/* tcp thread options */
|
||||
#define RT_LWIP_TCPTHREAD_PRIORITY 12
|
||||
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
|
||||
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
|
||||
|
||||
/* ethernet if thread options */
|
||||
#define RT_LWIP_ETHTHREAD_PRIORITY 15
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
|
||||
|
||||
/* TCP sender buffer space */
|
||||
#define RT_LWIP_TCP_SND_BUF 8192
|
||||
/* TCP receive window. */
|
||||
#define RT_LWIP_TCP_WND 8192
|
||||
|
||||
#define CHECKSUM_CHECK_TCP 0
|
||||
#define CHECKSUM_CHECK_IP 0
|
||||
#define CHECKSUM_CHECK_UDP 0
|
||||
|
||||
#define CHECKSUM_GEN_TCP 0
|
||||
#define CHECKSUM_GEN_IP 0
|
||||
#define CHECKSUM_GEN_UDP 0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='keil'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'C:/Keil'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
print '================ERROR============================'
|
||||
print 'Not support iar yet!'
|
||||
print '================================================='
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
TOWER_TYPE = 'K60FN1M0'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'axf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T k60_rom.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --device DARMSTM'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k60.map --scatter k60_rom.sct'
|
||||
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
|
@ -0,0 +1,394 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread_mk60f120m</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MK60FN1M0xxx12</Device>
|
||||
<Vendor>Freescale Semiconductor</Vendor>
|
||||
<Cpu>IRAM(0x1FFF0000-0x1FFFFFFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x0-0xFFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile>"STARTUP\Freescale\Kinetis\startup_MK60F12.s" ("Freescale MK60Xxxxxxx12 Startup Code")</StartupFile>
|
||||
<FlashDriverDll>ULP2CM3(-O2510 -S0 -C0 -FO15 -FD20000000 -FC4000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000)</FlashDriverDll>
|
||||
<DeviceId>6123</DeviceId>
|
||||
<RegisterFile>MK60F12.H</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>SFD\Freescale\Kinetis\MK60F12.sfr</SFDFile>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>Freescale\Kinetis\</RegisterFilePath>
|
||||
<DBRegisterFilePath>Freescale\Kinetis\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>thread-mk60f120m</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments>-MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments>-MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>1</RestoreTracepoints>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>12</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>PEMicro\Pemicro_ArmCortexInterface.dll</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4103</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>0</bUseTDR>
|
||||
<Flash2>PEMicro\Pemicro_ArmCortexInterface.dll</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1fff0000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x100000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x100000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1fff0000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x1FFF0000</DataAddressRange>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
Loading…
Reference in New Issue