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Merge pull request #1265 from enkiller/development 

[bsp][allwinner_tina]更改表意不清晰的函数名字
This commit is contained in:
Bernard Xiong 2018-03-08 13:54:56 +08:00 committed by GitHub
parent 6107b74ac3 5301a1b9d3
commit 505dc4182e
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 5 additions and 14 deletions
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4
bsp/allwinner_tina/drivers/drv_clock.c
View File

@ -485,7 +485,7 @@ rt_err_t bus_gate_clk_disalbe(enum bus_gate bus)
return RT_EOK;
}
rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
rt_err_t bus_software_reset_disalbe(enum bus_gate bus)
{
rt_uint32_t offset;
rt_uint32_t gate_reg;
@ -505,7 +505,7 @@ rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
return RT_EOK;
}
rt_err_t bus_software_reset_disalbe(enum bus_gate bus)
rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
{
rt_uint32_t offset;
rt_uint32_t gate_reg;

9
bsp/allwinner_tina/drivers/drv_clock.h
View File

@ -42,7 +42,6 @@
#define CSI_GATING_DRAM (0x1<<1)
#define VE_GATING_DRAM (0x1<<0)
/* */
#define TCON_PLL_VIDEO_X1 (0x000)
#define TCON_PLL_VIDEO_X2 (0x002)
@ -218,13 +217,6 @@ typedef struct tina_ccu *tina_ccu_t;
#define CCU ((tina_ccu_t) CCU_BASE_ADDR)
int cpu_get_pll_clk(void);
int audio_get_pll_clk(void);
int video_get_pll_clk(void);
@ -243,7 +235,6 @@ rt_err_t periph_set_pll_clk(int clk);
rt_err_t cpu_set_clk(int clk);
rt_err_t bus_gate_clk_enalbe(enum bus_gate bus);
rt_err_t bus_gate_clk_disalbe(enum bus_gate bus);
rt_err_t bus_software_reset_enalbe(enum bus_gate bus);

6
bsp/allwinner_tina/drivers/drv_uart.c
View File

@ -184,20 +184,20 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
if ((rt_uint32_t)(uart->hw_base) == UART0_BASE_ADDR)
{
bus_gate_clk_enalbe(UART0_GATING);
bus_software_reset_disalbe(UART0_GATING);
bus_software_reset_enalbe(UART0_GATING);
bus_software_reset_disalbe(UART0_GATING);
}
else if ((rt_uint32_t)(uart->hw_base) == UART1_BASE_ADDR)
{
bus_gate_clk_enalbe(UART1_GATING);
bus_software_reset_disalbe(UART1_GATING);
bus_software_reset_enalbe(UART1_GATING);
bus_software_reset_disalbe(UART1_GATING);
}
else if ((rt_uint32_t)(uart->hw_base) == UART2_BASE_ADDR)
{
bus_gate_clk_enalbe(UART2_GATING);
bus_software_reset_disalbe(UART2_GATING);
bus_software_reset_enalbe(UART2_GATING);
bus_software_reset_disalbe(UART2_GATING);
}
else
RT_ASSERT(0);