Add Onchip flash

bsp/cypress/libraries/HAL_Drivers/SConscript

@@ -41,6 +41,9 @@ if GetDepend(['BSP_USING_ADC']):
 if GetDepend('BSP_USING_RTC'):
     src += ['drv_rtc.c']
 
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    src += ['drv_flash.c']
+
 if GetDepend(['RT_USING_WDT']):
     src += ['drv_wdt.c']
 

bsp/cypress/libraries/HAL_Drivers/drv_adc.c

@@ -30,9 +30,9 @@ struct ifx_adc
 
 static struct ifx_adc ifx_adc_obj[] =
 {
-#ifdef BSP_USING_ADC1
+    #ifdef BSP_USING_ADC1
     ADC1_CONFIG,
-#endif
+    #endif
 };
 
 static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
@@ -54,6 +54,7 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
     {
         /* Initialize ADC. The ADC block which can connect to pin 10[0] is selected */
         result = cyhal_adc_init(&adc_obj, VPLUS_CHANNEL_0, NULL);
+
         if (result != RT_EOK)
         {
             LOG_E("ADC initialization failed. Error: %ld\n", (long unsigned int)result);
@@ -63,6 +64,7 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
         /* Initialize a channel 0 and configure it to scan P10_0 in single ended mode. */
         result  = cyhal_adc_channel_init_diff(adc_ch, &adc_obj, VPLUS_CHANNEL_0,
                                               CYHAL_ADC_VNEG, &channel_config);
+
         if (result != RT_EOK)
         {
             LOG_E("ADC single ended channel initialization failed. Error: %ld\n", (long unsigned int)result);
@@ -71,6 +73,7 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
 
         /* Update ADC configuration */
         result = cyhal_adc_configure(&adc_obj, &adc_config);
+
         if (result != RT_EOK)
         {
             printf("ADC configuration update failed. Error: %ld\n", (long unsigned int)result);

bsp/cypress/libraries/HAL_Drivers/drv_common.c

@@ -11,7 +11,7 @@
 #include "drv_common.h"
 
 #ifdef RT_USING_SERIAL
-#include "drv_uart.h"
+    #include "drv_uart.h"
 #endif
 
 #define DBG_TAG "drv_common"
@@ -58,6 +58,7 @@ void _Error_Handler(char *s, int num)
 {
     /* User can add his own implementation to report the HAL error return state */
     LOG_E("Error_Handler at file:%s num:%d", s, num);
+
     while (1)
     {
     }
@@ -74,10 +75,13 @@ void rt_hw_us_delay(rt_uint32_t us)
     start = SysTick->VAL;
     reload = SysTick->LOAD;
     us_tick = SystemCoreClock / 1000000UL;
-    do {
+
+    do
+    {
         now = SysTick->VAL;
         delta = start > now ? start - now : reload + start - now;
-    } while(delta < us_tick * us);
+    }
+    while(delta < us_tick * us);
 }
 
 /**
@@ -91,27 +95,27 @@ RT_WEAK void rt_hw_board_init()
     rt_hw_systick_init();
 
     /* heap initialization */
-#if defined(RT_USING_HEAP)
+    #if defined(RT_USING_HEAP)
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
-#endif
+    #endif
 
     /* pin driver initialization is open by default */
-#ifdef RT_USING_PIN
+    #ifdef RT_USING_PIN
     rt_hw_pin_init();
-#endif
+    #endif
 
     /* usart driver initialization is open by default */
-#ifdef RT_USING_SERIAL
+    #ifdef RT_USING_SERIAL
     rt_hw_uart_init();
-#endif
+    #endif
 
     /* set the shell console output device */
-#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
+    #endif
 
     /* board underlying hardware initialization */
-#ifdef RT_USING_COMPONENTS_INIT
+    #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
-#endif
+    #endif
 }

bsp/cypress/libraries/HAL_Drivers/drv_flash.c

@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-26     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_flash.h"
+
+#if defined(RT_USING_FAL)
+    #include "fal.h"
+#endif
+
+#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+static cyhal_flash_t flash_obj;
+static cyhal_flash_block_info_t block_info;
+static cyhal_flash_info_t flash_info;
+
+int _flash_init(void)
+{
+    cy_rslt_t err = CY_RSLT_SUCCESS;
+    /* Init Flash */
+    err = cyhal_flash_init(&flash_obj);
+
+    /* Handle Error */
+    if (CY_RSLT_SUCCESS != err)
+    {
+        LOG_E("\r\n Flash Init failed");
+    }
+
+    cyhal_flash_get_info(&flash_obj, &flash_info);
+
+    block_info = flash_info.blocks[flash_info.block_count - 1u];
+
+    return 0;
+}
+
+static rt_uint32_t get_page_32k(uint32_t addr)
+{
+    rt_uint32_t page = 0;
+
+    page = RT_ALIGN_DOWN(addr, IFX_EFLASH_PAGE_SIZE);
+
+    return page;
+}
+
+/**
+  * @brief  gets the page of a given address
+  * @param  addr: address of the flash memory
+  * @retval the page of a given address
+  */
+static rt_uint32_t get_page_256k(uint32_t addr)
+{
+    rt_uint32_t page = 0;
+
+    page = RT_ALIGN_DOWN(addr, IFX_FLASH_PAGE_SIZE);
+
+    return page;
+}
+
+int ifx_flash_read_32k(rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_uint32_t i;
+
+    if ((addr + size) > IFX_EFLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * @brief read data from flash.
+ * @note this operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int ifx_flash_read_256k(rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_uint32_t i;
+
+    if ((addr + size) > IFX_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * @brief write data to flash.
+ * @note this operation's units is word.
+ * @note this operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int ifx_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_base_t level;
+    cy_rslt_t err = CY_RSLT_SUCCESS;
+    size_t written_size = 0;
+
+#define BSP_FEATURE_FLASH_WRITE_SIZE 512U
+
+    if (size % BSP_FEATURE_FLASH_WRITE_SIZE)
+    {
+        LOG_E("Flash Write size must be an integer multiple of %d", BSP_FEATURE_FLASH_WRITE_SIZE);
+        return -RT_EINVAL;
+    }
+
+    while (written_size < size)
+    {
+        level = rt_hw_interrupt_disable();
+        /* Write code flash data*/
+        err = cyhal_flash_write(&flash_obj, addr + written_size, (rt_uint32_t *)(buf + written_size));
+        rt_hw_interrupt_enable(level);
+
+        /* Error Handle */
+        if (CY_RSLT_SUCCESS != err)
+        {
+            LOG_E("Write API failed");
+            return -RT_EIO;
+        }
+
+        written_size += BSP_FEATURE_FLASH_WRITE_SIZE;
+    }
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+int ifx_flash_erase_32k(rt_uint32_t addr, rt_uint32_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t page_addr = 0;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+
+    if ((end_addr) > IFX_EFLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    while (addr < end_addr)
+    {
+        page_addr = get_page_32k(addr);
+
+        if (cyhal_flash_erase(&flash_obj, page_addr) != CY_RSLT_SUCCESS)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        addr += IFX_FLASH_PAGE_SIZE;
+    }
+
+    rt_hw_interrupt_enable(level);
+
+__exit:
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * @brief erase data on flash .
+ * @note this operation is irreversible.
+ * @note this operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int ifx_flash_erase_256k(rt_uint32_t addr, rt_uint32_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t page_addr = 0;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+
+    if ((end_addr) > IFX_FLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    while (addr < end_addr)
+    {
+        page_addr = get_page_256k(addr);
+
+        if (cyhal_flash_erase(&flash_obj, page_addr) != CY_RSLT_SUCCESS)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        addr += IFX_FLASH_PAGE_SIZE;
+    }
+
+    rt_hw_interrupt_enable(level);
+
+__exit:
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+#if defined(RT_USING_FAL)
+static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_read_256k(long offset, rt_uint8_t *buf, size_t size);
+
+static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_write_256k(long offset, const rt_uint8_t *buf, size_t size);
+
+static int fal_flash_erase_32k(long offset, size_t size);
+static int fal_flash_erase_256k(long offset, size_t size);
+
+const struct fal_flash_dev ifx_onchip_flash_32k =
+{
+    "onchip_flash_32k",
+    IFX_EFLASH_START_ADRESS,
+    IFX_EFLASH_SIZE,
+    IFX_EFLASH_PAGE_SIZE,
+    {
+        NULL,
+        fal_flash_read_32k,
+        fal_flash_write_32k,
+        fal_flash_erase_32k
+    }
+};
+
+const struct fal_flash_dev ifx_onchip_flash_256k =
+{
+    "onchip_flash_256k",
+    IFX_FLASH_START_ADRESS,
+    IFX_FLASH_SIZE,
+    IFX_FLASH_PAGE_SIZE,
+    {
+        _flash_init,
+        fal_flash_read_256k,
+        fal_flash_write_256k,
+        fal_flash_erase_256k
+    }
+};
+
+static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_read_32k(ifx_onchip_flash_32k.addr + offset, buf, size);
+}
+
+static int fal_flash_read_256k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_read_256k(ifx_onchip_flash_256k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_write(ifx_onchip_flash_32k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_256k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_write(ifx_onchip_flash_256k.addr + offset, buf, size);
+}
+
+static int fal_flash_erase_32k(long offset, size_t size)
+{
+    return ifx_flash_erase_32k(ifx_onchip_flash_32k.addr + offset, size);
+}
+
+static int fal_flash_erase_256k(long offset, size_t size)
+{
+    return ifx_flash_erase_256k(ifx_onchip_flash_256k.addr + offset, size);
+}
+
+#if defined(BSP_USING_ON_CHIP_FLASH)
+static int rt_hw_on_chip_flash_init(void)
+{
+    fal_init();
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(rt_hw_on_chip_flash_init);
+
+int flash64k_test(void)
+{
+#define TEST_OFF (ifx_onchip_flash_256k.len - 0x40000)
+    const struct fal_partition *param;
+    uint8_t write_buffer[512U] = {0};
+    uint8_t read_buffer[512U] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint16_t index = 0; index < 512U; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    param = fal_partition_find("app");
+
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition app!");
+        return -1;
+    }
+
+    LOG_I("Erase Start...");
+    fal_partition_erase(param, TEST_OFF, 0x40000);
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST_OFF, read_buffer, 128U);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < 128U; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash64k_test, "drv flash64k test.");
+
+int flash32k_test(void)
+{
+#define TEST32_OFF (ifx_onchip_flash_32k.len - 0x8000)
+    const struct fal_partition *param;
+    uint8_t write_buffer[512U] = {0};
+    uint8_t read_buffer[512U] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint16_t index = 0; index < 512U; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    param = fal_partition_find("param");
+
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition param!");
+        return -1;
+    }
+
+    LOG_I("Erase Start...");
+    fal_partition_erase(param, TEST32_OFF, 0x8000);
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST32_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST32_OFF, read_buffer, 128U);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < 128U; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash32k_test, "drv flash32k test.");
+#endif
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */

bsp/cypress/libraries/HAL_Drivers/drv_flash.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-26     Rbb666       first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int ifx_flash_read(rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t size);
+int ifx_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, rt_uint32_t size);
+int ifx_flash_erase(rt_uint32_t addr, rt_uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

bsp/cypress/libraries/HAL_Drivers/drv_gpio.c

@@ -104,21 +104,25 @@ static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 
     switch (mode)
     {
-    case PIN_MODE_OUTPUT:
+        case PIN_MODE_OUTPUT:
-        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true);
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true);
-        break;
+            break;
-    case PIN_MODE_INPUT:
+
-        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_NONE, false);
+        case PIN_MODE_INPUT:
-        break;
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_NONE, false);
-    case PIN_MODE_INPUT_PULLUP:
+            break;
-        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
+
-        break;
+        case PIN_MODE_INPUT_PULLUP:
-    case PIN_MODE_INPUT_PULLDOWN:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
-        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLDOWN, false);
+            break;
-        break;
+
-    case PIN_MODE_OUTPUT_OD:
+        case PIN_MODE_INPUT_PULLDOWN:
-        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLDOWN, false);
-        break;
+            break;
+
+        case PIN_MODE_OUTPUT_OD:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
+            break;
     }
 }
 
@@ -172,6 +176,7 @@ static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     }
 
     level = rt_hw_interrupt_disable();
+
     if (pin_irq_handler_tab[gpio_port].pin == pin &&
             pin_irq_handler_tab[gpio_port].hdr == hdr &&
             pin_irq_handler_tab[gpio_port].mode == mode &&
@@ -180,11 +185,13 @@ static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
         rt_hw_interrupt_enable(level);
         return RT_EOK;
     }
+
     if (pin_irq_handler_tab[gpio_port].pin != -1)
     {
         rt_hw_interrupt_enable(level);
         return RT_EBUSY;
     }
+
     pin_irq_handler_tab[gpio_port].pin = pin;
     pin_irq_handler_tab[gpio_port].hdr = hdr;
     pin_irq_handler_tab[gpio_port].mode = mode;
@@ -211,6 +218,7 @@ static rt_err_t ifx_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     }
 
     level = rt_hw_interrupt_disable();
+
     if (pin_irq_handler_tab[gpio_port].pin == -1)
     {
         rt_hw_interrupt_enable(level);
@@ -267,17 +275,20 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
 
         switch (pin_irq_handler_tab[gpio_port].mode)
         {
-        case PIN_IRQ_MODE_RISING:
+            case PIN_IRQ_MODE_RISING:
-            pin_irq_mode = CYHAL_GPIO_IRQ_RISE;
+                pin_irq_mode = CYHAL_GPIO_IRQ_RISE;
-            break;
+                break;
-        case PIN_IRQ_MODE_FALLING:
+
-            pin_irq_mode = CYHAL_GPIO_IRQ_FALL;
+            case PIN_IRQ_MODE_FALLING:
-            break;
+                pin_irq_mode = CYHAL_GPIO_IRQ_FALL;
-        case PIN_IRQ_MODE_RISING_FALLING:
+                break;
-            pin_irq_mode = CYHAL_GPIO_IRQ_BOTH;
+
-            break;
+            case PIN_IRQ_MODE_RISING_FALLING:
-        default:
+                pin_irq_mode = CYHAL_GPIO_IRQ_BOTH;
-            break;
+                break;
+
+            default:
+                break;
         }
 
         cyhal_gpio_enable_event(gpio_pin, pin_irq_mode, GPIO_INTERRUPT_PRIORITY, RT_TRUE);
@@ -290,9 +301,9 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
 
         Cy_GPIO_Port_Deinit(CYHAL_GET_PORTADDR(gpio_pin));
 
-#if !defined(COMPONENT_CAT1C)
+        #if !defined(COMPONENT_CAT1C)
         IRQn_Type irqn = (IRQn_Type)(irqmap->irqno + PORT_GET(irqmap->port));
-#endif
+        #endif
         _cyhal_irq_disable(irqn);
 
         rt_hw_interrupt_enable(level);

bsp/cypress/libraries/HAL_Drivers/drv_log.h

@@ -13,15 +13,15 @@
  */
 
 #ifndef LOG_TAG
-#define DBG_TAG               "drv"
+    #define DBG_TAG               "drv"
 #else
-#define DBG_TAG               LOG_TAG
+    #define DBG_TAG               LOG_TAG
 #endif /* LOG_TAG */
 
 #ifdef DRV_DEBUG
-#define DBG_LVL               DBG_LOG
+    #define DBG_LVL               DBG_LOG
 #else
-#define DBG_LVL               DBG_INFO
+    #define DBG_LVL               DBG_INFO
 #endif /* DRV_DEBUG */
 
 #include <rtdbg.h>

bsp/cypress/libraries/HAL_Drivers/drv_pwm.c

@@ -31,47 +31,47 @@ struct ifx_pwm
 
 enum
 {
-#ifdef BSP_USING_PWM0
+    #ifdef BSP_USING_PWM0
     PWM0_INDEX,
-#endif
+    #endif
 };
 
 static struct ifx_pwm ifx_pwm_obj[] =
 {
-#ifdef BSP_USING_PWM0
+    #ifdef BSP_USING_PWM0
     PWM0_CONFIG,
-#endif
+    #endif
 };
 
 static void pwm_get_pin_number(void)
 {
-#ifdef BSP_USING_PWM0_CH7
+    #ifdef BSP_USING_PWM0_CH7
-#ifdef BSP_USING_PWM0_PORT2
+    #ifdef BSP_USING_PWM0_PORT2
     ifx_pwm_obj[PWM0_INDEX].gpio = GET_PIN(2, 2);
-#endif
+    #endif
-#ifdef BSP_USING_PWM0_PORT5
+    #ifdef BSP_USING_PWM0_PORT5
     ifx_pwm_obj[PWM0_INDEX].gpio = GET_PIN(5, 6);
-#endif
+    #endif
-#ifdef BSP_USING_PWM0_PORT7
+    #ifdef BSP_USING_PWM0_PORT7
     ifx_pwm_obj[PWM0_INDEX].gpio = GET_PIN(7, 7);
-#endif
+    #endif
-#ifdef BSP_USING_PWM0_PORT9
+    #ifdef BSP_USING_PWM0_PORT9
     ifx_pwm_obj[PWM0_INDEX].gpio = GET_PIN(9, 4);
-#endif
+    #endif
-#ifdef BSP_USING_PWM0_PORT10
+    #ifdef BSP_USING_PWM0_PORT10
     ifx_pwm_obj[PWM0_INDEX].gpio = GET_PIN(10, 2);
-#endif
+    #endif
-#ifdef BSP_USING_PWM0_PORT12
+    #ifdef BSP_USING_PWM0_PORT12
     ifx_pwm_obj[PWM0_INDEX].gpio = GET_PIN(12, 6);
-#endif
+    #endif
-#endif
+    #endif
 }
 
 static void pwm_get_channel(void)
 {
-#ifdef BSP_USING_PWM0_CH7
+    #ifdef BSP_USING_PWM0_CH7
     ifx_pwm_obj[PWM0_INDEX].channel = 7;
-#endif
+    #endif
 }
 
 static rt_err_t drv_pwm_enable(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
@@ -136,20 +136,26 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
 
     switch (cmd)
     {
-    case PWMN_CMD_ENABLE:
+        case PWMN_CMD_ENABLE:
-        configuration->complementary = RT_TRUE;
+            configuration->complementary = RT_TRUE;
-    case PWM_CMD_ENABLE:
+
-        return drv_pwm_enable(htim, configuration, RT_TRUE);
+        case PWM_CMD_ENABLE:
-    case PWMN_CMD_DISABLE:
+            return drv_pwm_enable(htim, configuration, RT_TRUE);
-        configuration->complementary = RT_FALSE;
+
-    case PWM_CMD_DISABLE:
+        case PWMN_CMD_DISABLE:
-        return drv_pwm_enable(htim, configuration, RT_FALSE);
+            configuration->complementary = RT_FALSE;
-    case PWM_CMD_SET:
+
-        return drv_pwm_set(htim, configuration);
+        case PWM_CMD_DISABLE:
-    case PWM_CMD_GET:
+            return drv_pwm_enable(htim, configuration, RT_FALSE);
-        return drv_pwm_get(htim, configuration);
+
-    default:
+        case PWM_CMD_SET:
-        return RT_EINVAL;
+            return drv_pwm_set(htim, configuration);
+
+        case PWM_CMD_GET:
+            return drv_pwm_get(htim, configuration);
+
+        default:
+            return RT_EINVAL;
     }
 }
 
@@ -232,6 +238,7 @@ static int pwm_sample(int argc, char *argv[])
     pulse = 0;
 
     pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+
     if (pwm_dev == RT_NULL)
     {
         rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
@@ -253,10 +260,12 @@ static int pwm_sample(int argc, char *argv[])
         {
             pulse -= 5000;
         }
+
         if (pulse >= period)
         {
             dir = 0;
         }
+
         if (0 == pulse)
         {
             dir = 1;

bsp/cypress/libraries/HAL_Drivers/drv_pwm.h

@@ -24,9 +24,9 @@ extern "C" {
 #ifndef PWM0_CONFIG
 #define PWM0_CONFIG                             \
     {                                           \
-       .name                    = "pwm0",       \
+        .name                    = "pwm0",       \
-       .channel                 = 0,            \
+                                   .channel                 = 0,            \
-       .gpio                    = 0,            \
+                                           .gpio                    = 0,            \
     }
 #endif /* PWM0_CONFIG */
 #endif /* BSP_USING_PWM0 */

bsp/cypress/libraries/HAL_Drivers/drv_rtc.c

@@ -28,6 +28,7 @@ static int get_day_of_week(int day, int month, int year)
     int ret;
     int k = 0;
     int j = 0;
+
     if (month < CY_RTC_MARCH)
     {
         month += CY_RTC_MONTHS_PER_YEAR;
@@ -48,6 +49,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
     struct tm new_time = {0};
 
     gmtime_r(&time_stamp, &tm);
+
     if (tm.tm_year < 100)
     {
         return -RT_ERROR;
@@ -120,6 +122,7 @@ static rt_err_t _rtc_set_secs(time_t *sec)
     {
         result = -RT_ERROR;
     }
+
     LOG_D("RTC: set rtc_time %d", *sec);
 
     return result;

bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.c

@@ -24,9 +24,9 @@
 
 static const struct ifx_soft_i2c_config soft_i2c_config[] =
 {
-#ifdef BSP_USING_I2C1
+    #ifdef BSP_USING_I2C1
     I2C1_BUS_CONFIG,
-#endif
+    #endif
 };
 
 static struct ifx_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
@@ -56,6 +56,7 @@ static void ifx_i2c_gpio_init(struct ifx_i2c *i2c)
 static void ifx_set_sda(void *data, rt_int32_t state)
 {
     struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+
     if (state)
     {
         rt_pin_write(cfg->sda, PIN_HIGH);
@@ -75,6 +76,7 @@ static void ifx_set_sda(void *data, rt_int32_t state)
 static void ifx_set_scl(void *data, rt_int32_t state)
 {
     struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+
     if (state)
     {
         rt_pin_write(cfg->scl, PIN_HIGH);
@@ -140,6 +142,7 @@ static rt_err_t ifx_i2c_bus_unlock(const struct ifx_soft_i2c_config *cfg)
             rt_hw_us_delay(100);
         }
     }
+
     if (PIN_LOW == rt_pin_read(cfg->sda))
     {
         return -RT_ERROR;

bsp/cypress/libraries/HAL_Drivers/drv_spi.c

@@ -32,7 +32,7 @@ struct ifx_sw_spi_cs
 
 static struct ifx_spi spi_bus_obj[] =
 {
-#ifdef BSP_USING_SPI3
+    #ifdef BSP_USING_SPI3
     {
         .bus_name = "spi3",
         .spi_bus = &spi_bus3,
@@ -40,7 +40,7 @@ static struct ifx_spi spi_bus_obj[] =
         .miso_pin = GET_PIN(6, 1),
         .mosi_pin = GET_PIN(6, 0),
     },
-#endif
+    #endif
 };
 
 /* private rt-thread spi ops function */
@@ -100,18 +100,21 @@ static rt_err_t spi_configure(struct rt_spi_device *device,
     /* MSB or LSB */
     switch (configuration->mode & RT_SPI_MODE_3)
     {
-    case RT_SPI_MODE_0:
+        case RT_SPI_MODE_0:
-        spi_device->spi_obj->mode = CYHAL_SPI_MODE_00_MSB;
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_00_MSB;
-        break;
+            break;
-    case RT_SPI_MODE_1:
+
-        spi_device->spi_obj->mode = CYHAL_SPI_MODE_01_MSB;
+        case RT_SPI_MODE_1:
-        break;
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_01_MSB;
-    case RT_SPI_MODE_2:
+            break;
-        spi_device->spi_obj->mode = CYHAL_SPI_MODE_10_MSB;
+
-        break;
+        case RT_SPI_MODE_2:
-    case RT_SPI_MODE_3:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_10_MSB;
-        spi_device->spi_obj->mode = CYHAL_SPI_MODE_11_MSB;
+            break;
-        break;
+
+        case RT_SPI_MODE_3:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_11_MSB;
+            break;
     }
 
     ifx_spi_init(spi_device);

bsp/cypress/libraries/HAL_Drivers/drv_uart.c

@@ -17,46 +17,46 @@
 
 enum
 {
-#ifdef BSP_USING_UART0
+    #ifdef BSP_USING_UART0
     UART0_INDEX,
-#endif
+    #endif
-#ifdef BSP_USING_UART1
+    #ifdef BSP_USING_UART1
     UART1_INDEX,
-#endif
+    #endif
-#ifdef BSP_USING_UART2
+    #ifdef BSP_USING_UART2
     UART2_INDEX,
-#endif
+    #endif
-#ifdef BSP_USING_UART3
+    #ifdef BSP_USING_UART3
     UART3_INDEX,
-#endif
+    #endif
-#ifdef BSP_USING_UART4
+    #ifdef BSP_USING_UART4
     UART4_INDEX,
-#endif
+    #endif
-#ifdef BSP_USING_UART5
+    #ifdef BSP_USING_UART5
     UART5_INDEX,
-#endif
+    #endif
 };
 
 static struct ifx_uart_config uart_config[] =
 {
-#ifdef BSP_USING_UART0
+    #ifdef BSP_USING_UART0
     UART0_CONFIG,
-#endif
+    #endif
-#ifdef BSP_USING_UART1
+    #ifdef BSP_USING_UART1
     UART1_CONFIG,
-#endif
+    #endif
-#ifdef BSP_USING_UART2
+    #ifdef BSP_USING_UART2
     UART2_CONFIG,
-#endif
+    #endif
-#ifdef BSP_USING_UART3
+    #ifdef BSP_USING_UART3
     UART3_CONFIG,
-#endif
+    #endif
-#ifdef BSP_USING_UART4
+    #ifdef BSP_USING_UART4
     UART4_CONFIG,
-#endif
+    #endif
-#ifdef BSP_USING_UART5
+    #ifdef BSP_USING_UART5
     UART5_CONFIG,
-#endif
+    #endif
 };
 
 static struct ifx_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
@@ -196,20 +196,20 @@ static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg)
 
     switch (cmd)
     {
-    case RT_DEVICE_CTRL_CLR_INT:
+        case RT_DEVICE_CTRL_CLR_INT:
 
-        break;
+            break;
 
-    case RT_DEVICE_CTRL_SET_INT:
+        case RT_DEVICE_CTRL_SET_INT:
-        /* Unmasking only the RX fifo not empty interrupt bit */
+            /* Unmasking only the RX fifo not empty interrupt bit */
-        uart->config->usart_x->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
+            uart->config->usart_x->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
 
-        /* Interrupt Settings for UART */
+            /* Interrupt Settings for UART */
-        Cy_SysInt_Init(uart->config->UART_SCB_IRQ_cfg, uart->config->userIsr);
+            Cy_SysInt_Init(uart->config->UART_SCB_IRQ_cfg, uart->config->userIsr);
 
-        /* Enable the interrupt */
+            /* Enable the interrupt */
-        NVIC_EnableIRQ(uart->config->intrSrc);
+            NVIC_EnableIRQ(uart->config->intrSrc);
-        break;
+            break;
     }
 
     return (RT_EOK);
@@ -227,6 +227,7 @@ static int ifx_uarths_putc(struct rt_serial_device *serial, char c)
         return CYHAL_SYSPM_RSLT_ERR_PM_PENDING;
 
     uint32_t count = 0;
+
     while (count == 0)
     {
         count = Cy_SCB_UART_Put(uart->config->usart_x, c);
@@ -245,6 +246,7 @@ static int ifx_uarths_getc(struct rt_serial_device *serial)
     RT_ASSERT(uart != RT_NULL);
 
     ch = -1;
+
     if (RT_EOK == cyhal_uart_getc(uart->config->uart_obj, (uint8_t *)&read_data, 1))
     {
         ch = read_data & 0xff;

bsp/cypress/libraries/HAL_Drivers/drv_wdt.c

@@ -39,41 +39,49 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg)
     cfg = wdt_device->parent.user_data;
 
     rt_uint32_t timeout_ms = 0;
+
     switch (cmd)
     {
-    /* feed the watchdog */
+        /* feed the watchdog */
-    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        case RT_DEVICE_CTRL_WDT_KEEPALIVE:
-        cyhal_wdt_kick(cfg->WDTx);
+            cyhal_wdt_kick(cfg->WDTx);
-        break;
+            break;
-    /* set watchdog timeout */
-    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
-    {
-        timeout_ms = *((rt_uint32_t *)arg) * 1000;
 
-        rt_uint32_t max_timeout_ms = cyhal_wdt_get_max_timeout_ms();
+        /* set watchdog timeout */
-        if (timeout_ms >= max_timeout_ms)
+        case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
-            timeout_ms = max_timeout_ms;
+        {
+            timeout_ms = *((rt_uint32_t *)arg) * 1000;
 
-        /* Initialize the WDT */
+            rt_uint32_t max_timeout_ms = cyhal_wdt_get_max_timeout_ms();
-        int result = cyhal_wdt_init(cfg->WDTx, (rt_uint32_t)timeout_ms);
+
-        /* WDT initialization failed. Stop program execution */
+            if (timeout_ms >= max_timeout_ms)
-        RT_ASSERT(result != RT_ERROR);
+                timeout_ms = max_timeout_ms;
-    }
+
-    break;
+            /* Initialize the WDT */
-    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+            int result = cyhal_wdt_init(cfg->WDTx, (rt_uint32_t)timeout_ms);
-        timeout_ms = cyhal_wdt_get_timeout_ms(cfg->WDTx);
+            /* WDT initialization failed. Stop program execution */
-        *(rt_uint32_t *)arg = timeout_ms / 1000;
+            RT_ASSERT(result != RT_ERROR);
-        break;
+        }
-    case RT_DEVICE_CTRL_WDT_START:
+        break;
-        cyhal_wdt_start(cfg->WDTx);
+
-        break;
+        case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
-    case RT_DEVICE_CTRL_WDT_STOP:
+            timeout_ms = cyhal_wdt_get_timeout_ms(cfg->WDTx);
-        cyhal_wdt_stop(cfg->WDTx);
+            *(rt_uint32_t *)arg = timeout_ms / 1000;
-        break;
+            break;
-    default:
+
-        LOG_W("This command is not supported.");
+        case RT_DEVICE_CTRL_WDT_START:
-        return -RT_ERROR;
+            cyhal_wdt_start(cfg->WDTx);
+            break;
+
+        case RT_DEVICE_CTRL_WDT_STOP:
+            cyhal_wdt_stop(cfg->WDTx);
+            break;
+
+        default:
+            LOG_W("This command is not supported.");
+            return -RT_ERROR;
     }
+
     return RT_EOK;
 }
 
@@ -93,6 +101,7 @@ int rt_hw_wdt_init(void)
         LOG_E("wdt device register failed.");
         return -RT_ERROR;
     }
+
     LOG_D("wdt device register success.");
     return RT_EOK;
 }

bsp/cypress/libraries/IFX_PSOC6_HAL/SConscript

@@ -99,6 +99,10 @@ if GetDepend('BSP_USING_RTC'):
     src += ['mtb-pdl-cat1/drivers/source/cy_rtc.c']
     src += ['mtb-hal-cat1/source/cyhal_rtc.c']
 
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
+    src += ['mtb-hal-cat1/source/cyhal_flash.c']
+
 if GetDepend(['RT_USING_WDT']):
     src += ['mtb-pdl-cat1/drivers/source/cy_wdt.c']
     src += ['mtb-hal-cat1/source/cyhal_wdt.c']

bsp/cypress/psoc6-cy8cproto-4343w/board/Kconfig

@@ -213,6 +213,10 @@ menu "On-chip Peripheral Drivers"
             endchoice
         endif
 
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n 
+
     config BSP_USING_WDT
         bool "Enable Watchdog Timer"
         select RT_USING_WDT

bsp/cypress/psoc6-cy8cproto-4343w/board/SConscript

@@ -20,7 +20,7 @@ if GetDepend(['BSP_USING_RW007']):
     src += Glob('ports/drv_rw007.c')
 
 path = [cwd]
-path += [cwd + '/port']
+path += [cwd + '/ports']
 
 startup_path_prefix = SDK_LIB
 

bsp/cypress/psoc6-cy8cproto-4343w/board/board.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-06-29     Rbb666       first version
+ * 2022-07-26     Rbb666       Add Flash Config
  */
 
 #ifndef __BOARD_H__
@@ -20,8 +21,21 @@
 #include "cy_pdl.h"
 #include "cy_retarget_io.h"
 
-#define IFX_SRAM_SIZE       1014
+/*FLASH CONFIG*/
-#define IFX_SRAM_END        (0x08002000 + IFX_SRAM_SIZE * 1024)
+#define IFX_FLASH_START_ADRESS          ((uint32_t)0x10000000)
+#define IFX_FLASH_PAGE_SIZE             (256 * 1024)
+#define IFX_FLASH_SIZE                  (2 * 1024 * 1024)
+#define IFX_FLASH_END_ADDRESS           ((uint32_t)(IFX_FLASH_START_ADRESS + IFX_FLASH_SIZE))
+
+/*EFLASH CONFIG*/
+#define IFX_EFLASH_START_ADRESS         ((uint32_t)0x14000000)
+#define IFX_EFLASH_PAGE_SIZE            (32 * 1024)
+#define IFX_EFLASH_SIZE                 (32 * 1024)
+#define IFX_EFLASH_END_ADDRESS          ((uint32_t)(IFX_EFLASH_START_ADRESS + IFX_EFLASH_SIZE))
+
+/*SRAM CONFIG*/
+#define IFX_SRAM_SIZE                   (1014)
+#define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)
 
 #ifdef __ARMCC_VERSION
     extern int Image$$RW_IRAM1$$ZI$$Limit;

bsp/cypress/psoc6-cy8cproto-4343w/board/ports/fal_cfg.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-27     Rbb666       first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev ifx_onchip_flash_32k;
+extern const struct fal_flash_dev ifx_onchip_flash_256k;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE         \
+    {                               \
+        &ifx_onchip_flash_32k,      \
+        &ifx_onchip_flash_256k,     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                  \
+    {                                                                                   \
+        {FAL_PART_MAGIC_WROD, "param", "onchip_flash_32k", 0, IFX_EFLASH_SIZE, 0},      \
+        {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0, IFX_FLASH_SIZE, 0},        \
+    }
+
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */