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update libcpu/arm/cortex-m3: restore MSP.

This commit is contained in:
aozima 2013-06-18 11:25:56 +08:00
parent f9e673354a
commit 4d421cad73
3 changed files with 129 additions and 102 deletions
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9
libcpu/arm/cortex-m3/context_gcc.S
View File

@ -13,6 +13,7 @@
* 2010-12-29 onelife Modify for EFM32 * 2010-12-29 onelife Modify for EFM32
* 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S
* 2011-07-12 onelife Add interrupt context check function * 2011-07-12 onelife Add interrupt context check function
* 2013-06-18 aozima add restore MSP feature.
*/ */
.cpu cortex-m3 .cpu cortex-m3
@ -21,6 +22,7 @@
.thumb .thumb
.text .text
.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */
.equ ICSR, 0xE000ED04 /* interrupt control state register */ .equ ICSR, 0xE000ED04 /* interrupt control state register */
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
@ -152,6 +154,13 @@ rt_hw_context_switch_to:
LDR R1, =PENDSVSET_BIT LDR R1, =PENDSVSET_BIT
STR R1, [R0] STR R1, [R0]
/* restore MSP */
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
CPSIE I /* enable interrupts at processor level */ CPSIE I /* enable interrupts at processor level */
/* never reach here! */ /* never reach here! */

9
libcpu/arm/cortex-m3/context_iar.S
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@ -11,6 +11,7 @@
; * Date Author Notes ; * Date Author Notes
; * 2009-01-17 Bernard first version ; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs ; * 2009-09-27 Bernard add protect when contex switch occurs
; * 2013-06-18 aozima add restore MSP feature.
; */ ; */
;/** ;/**
@ -18,6 +19,7 @@
; */ ; */
;/*@{*/ ;/*@{*/
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
@ -151,6 +153,13 @@ rt_hw_context_switch_to:
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
; restore MSP
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
CPSIE I ; enable interrupts at processor level CPSIE I ; enable interrupts at processor level
; never reach here! ; never reach here!

9
libcpu/arm/cortex-m3/context_rvds.S
View File

@ -10,6 +10,7 @@
; * Change Logs: ; * Change Logs:
; * Date Author Notes ; * Date Author Notes
; * 2009-01-17 Bernard first version ; * 2009-01-17 Bernard first version
; * 2013-06-18 aozima add restore MSP feature.
; */ ; */
;/** ;/**
@ -17,6 +18,7 @@
; */ ; */
;/*@{*/ ;/*@{*/
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
@ -158,6 +160,13 @@ rt_hw_context_switch_to PROC
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
; restore MSP
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
; enable interrupts at processor level ; enable interrupts at processor level
CPSIE I CPSIE I