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fix:fix wch startup risks.

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1: If IAP has set mstatus to other value, using csrs will not change old value of mstatus in IAP. It should using csrw instead.
2: Reduce the flash size of undefined irq functions.
This commit is contained in:
CoderNotCute 2023-11-03 20:14:03 +08:00 committed by guo
parent 3143289486
commit 4ac9754f5b
4 changed files with 190 additions and 185 deletions
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2
bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Source/GCC/startup_ch32v10x.S
View File

@ -174,7 +174,7 @@ handle_reset:
2: 2:
/* disable interrupt */ /* disable interrupt */
li t0, 0x1800 li t0, 0x1800
csrs mstatus, t0 csrw mstatus, t0
la t0, _vector_base la t0, _vector_base
ori t0, t0, 1 ori t0, t0, 1
csrw mtvec, t0 csrw mtvec, t0

126
bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/startup_ch32v20x_D8W.S
View File

@ -168,67 +168,69 @@ _vector_base:
.weak OSC32KCal_IRQHandler /* OSC32 KCal */ .weak OSC32KCal_IRQHandler /* OSC32 KCal */
.weak OSCWakeUp_IRQHandler /* OSC Wake Up */ .weak OSCWakeUp_IRQHandler /* OSC Wake Up */
NMI_Handler: 1: j 1b NMI_Handler:
HardFault_Handler: 1: j 1b HardFault_Handler:
Ecall_M_Mode_Handler: 1: j 1b Ecall_M_Mode_Handler:
Ecall_U_Mode_Handler: 1: j 1b Ecall_U_Mode_Handler:
Break_Point_Handler: 1: j 1b Break_Point_Handler:
SysTick_Handler: 1: j 1b SysTick_Handler:
SW_handler: 1: j 1b SW_handler:
WWDG_IRQHandler: 1: j 1b WWDG_IRQHandler:
PVD_IRQHandler: 1: j 1b PVD_IRQHandler:
TAMPER_IRQHandler: 1: j 1b TAMPER_IRQHandler:
RTC_IRQHandler: 1: j 1b RTC_IRQHandler:
FLASH_IRQHandler: 1: j 1b FLASH_IRQHandler:
RCC_IRQHandler: 1: j 1b RCC_IRQHandler:
EXTI0_IRQHandler: 1: j 1b EXTI0_IRQHandler:
EXTI1_IRQHandler: 1: j 1b EXTI1_IRQHandler:
EXTI2_IRQHandler: 1: j 1b EXTI2_IRQHandler:
EXTI3_IRQHandler: 1: j 1b EXTI3_IRQHandler:
EXTI4_IRQHandler: 1: j 1b EXTI4_IRQHandler:
DMA1_Channel1_IRQHandler: 1: j 1b DMA1_Channel1_IRQHandler:
DMA1_Channel2_IRQHandler: 1: j 1b DMA1_Channel2_IRQHandler:
DMA1_Channel3_IRQHandler: 1: j 1b DMA1_Channel3_IRQHandler:
DMA1_Channel4_IRQHandler: 1: j 1b DMA1_Channel4_IRQHandler:
DMA1_Channel5_IRQHandler: 1: j 1b DMA1_Channel5_IRQHandler:
DMA1_Channel6_IRQHandler: 1: j 1b DMA1_Channel6_IRQHandler:
DMA1_Channel7_IRQHandler: 1: j 1b DMA1_Channel7_IRQHandler:
ADC1_2_IRQHandler: 1: j 1b ADC1_2_IRQHandler:
USB_HP_CAN1_TX_IRQHandler: 1: j 1b USB_HP_CAN1_TX_IRQHandler:
USB_LP_CAN1_RX0_IRQHandler: 1: j 1b USB_LP_CAN1_RX0_IRQHandler:
CAN1_RX1_IRQHandler: 1: j 1b CAN1_RX1_IRQHandler:
CAN1_SCE_IRQHandler: 1: j 1b CAN1_SCE_IRQHandler:
EXTI9_5_IRQHandler: 1: j 1b EXTI9_5_IRQHandler:
TIM1_BRK_IRQHandler: 1: j 1b TIM1_BRK_IRQHandler:
TIM1_UP_IRQHandler: 1: j 1b TIM1_UP_IRQHandler:
TIM1_TRG_COM_IRQHandler: 1: j 1b TIM1_TRG_COM_IRQHandler:
TIM1_CC_IRQHandler: 1: j 1b TIM1_CC_IRQHandler:
TIM2_IRQHandler: 1: j 1b TIM2_IRQHandler:
TIM3_IRQHandler: 1: j 1b TIM3_IRQHandler:
TIM4_IRQHandler: 1: j 1b TIM4_IRQHandler:
I2C1_EV_IRQHandler: 1: j 1b I2C1_EV_IRQHandler:
I2C1_ER_IRQHandler: 1: j 1b I2C1_ER_IRQHandler:
I2C2_EV_IRQHandler: 1: j 1b I2C2_EV_IRQHandler:
I2C2_ER_IRQHandler: 1: j 1b I2C2_ER_IRQHandler:
SPI1_IRQHandler: 1: j 1b SPI1_IRQHandler:
SPI2_IRQHandler: 1: j 1b SPI2_IRQHandler:
USART1_IRQHandler: 1: j 1b USART1_IRQHandler:
USART2_IRQHandler: 1: j 1b USART2_IRQHandler:
USART3_IRQHandler: 1: j 1b USART3_IRQHandler:
EXTI15_10_IRQHandler: 1: j 1b EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler: 1: j 1b RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler: 1: j 1b USBWakeUp_IRQHandler:
USBHD_IRQHandler: 1: j 1b USBHD_IRQHandler:
USBHDWakeUp_IRQHandler: 1: j 1b USBHDWakeUp_IRQHandler:
ETH_IRQHandler: 1: j 1b ETH_IRQHandler:
ETHWakeUp_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler:
BB_IRQHandler: 1: j 1b BB_IRQHandler:
LLE_IRQHandler: 1: j 1b LLE_IRQHandler:
TIM5_IRQHandler: 1: j 1b TIM5_IRQHandler:
UART4_IRQHandler: 1: j 1b UART4_IRQHandler:
DMA1_Channel8_IRQHandler: 1: j 1b DMA1_Channel8_IRQHandler:
OSC32KCal_IRQHandler: 1: j 1b OSC32KCal_IRQHandler:
OSCWakeUp_IRQHandler: 1: j 1b OSCWakeUp_IRQHandler:
1:
j 1b
.section .text.handle_reset,"ax",@progbits .section .text.handle_reset,"ax",@progbits
.weak handle_reset .weak handle_reset
@ -271,7 +273,7 @@ handle_reset:
/* Enable interrupt */ /* Enable interrupt */
li t0, 0x1800 li t0, 0x1800
csrs mstatus, t0 csrw mstatus, t0
la t0, _vector_base la t0, _vector_base
ori t0, t0, 3 ori t0, t0, 3

194
bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/startup_ch32v30x.S
View File

@ -233,101 +233,103 @@ _vector_base:
.weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
.weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
NMI_Handler: 1: j 1b NMI_Handler:
HardFault_Handler: 1: j 1b HardFault_Handler:
Ecall_M_Mode_Handler: 1: j 1b Ecall_M_Mode_Handler:
Ecall_U_Mode_Handler: 1: j 1b Ecall_U_Mode_Handler:
Break_Point_Handler: 1: j 1b Break_Point_Handler:
SysTick_Handler: 1: j 1b SysTick_Handler:
SW_handler: 1: j 1b SW_handler:
WWDG_IRQHandler: 1: j 1b WWDG_IRQHandler:
PVD_IRQHandler: 1: j 1b PVD_IRQHandler:
TAMPER_IRQHandler: 1: j 1b TAMPER_IRQHandler:
RTC_IRQHandler: 1: j 1b RTC_IRQHandler:
FLASH_IRQHandler: 1: j 1b FLASH_IRQHandler:
RCC_IRQHandler: 1: j 1b RCC_IRQHandler:
EXTI0_IRQHandler: 1: j 1b EXTI0_IRQHandler:
EXTI1_IRQHandler: 1: j 1b EXTI1_IRQHandler:
EXTI2_IRQHandler: 1: j 1b EXTI2_IRQHandler:
EXTI3_IRQHandler: 1: j 1b EXTI3_IRQHandler:
EXTI4_IRQHandler: 1: j 1b EXTI4_IRQHandler:
DMA1_Channel1_IRQHandler: 1: j 1b DMA1_Channel1_IRQHandler:
DMA1_Channel2_IRQHandler: 1: j 1b DMA1_Channel2_IRQHandler:
DMA1_Channel3_IRQHandler: 1: j 1b DMA1_Channel3_IRQHandler:
DMA1_Channel4_IRQHandler: 1: j 1b DMA1_Channel4_IRQHandler:
DMA1_Channel5_IRQHandler: 1: j 1b DMA1_Channel5_IRQHandler:
DMA1_Channel6_IRQHandler: 1: j 1b DMA1_Channel6_IRQHandler:
DMA1_Channel7_IRQHandler: 1: j 1b DMA1_Channel7_IRQHandler:
ADC1_2_IRQHandler: 1: j 1b ADC1_2_IRQHandler:
USB_HP_CAN1_TX_IRQHandler: 1: j 1b USB_HP_CAN1_TX_IRQHandler:
USB_LP_CAN1_RX0_IRQHandler: 1: j 1b USB_LP_CAN1_RX0_IRQHandler:
CAN1_RX1_IRQHandler: 1: j 1b CAN1_RX1_IRQHandler:
CAN1_SCE_IRQHandler: 1: j 1b CAN1_SCE_IRQHandler:
EXTI9_5_IRQHandler: 1: j 1b EXTI9_5_IRQHandler:
TIM1_BRK_IRQHandler: 1: j 1b TIM1_BRK_IRQHandler:
TIM1_UP_IRQHandler: 1: j 1b TIM1_UP_IRQHandler:
TIM1_TRG_COM_IRQHandler: 1: j 1b TIM1_TRG_COM_IRQHandler:
TIM1_CC_IRQHandler: 1: j 1b TIM1_CC_IRQHandler:
TIM2_IRQHandler: 1: j 1b TIM2_IRQHandler:
TIM3_IRQHandler: 1: j 1b TIM3_IRQHandler:
TIM4_IRQHandler: 1: j 1b TIM4_IRQHandler:
I2C1_EV_IRQHandler: 1: j 1b I2C1_EV_IRQHandler:
I2C1_ER_IRQHandler: 1: j 1b I2C1_ER_IRQHandler:
I2C2_EV_IRQHandler: 1: j 1b I2C2_EV_IRQHandler:
I2C2_ER_IRQHandler: 1: j 1b I2C2_ER_IRQHandler:
SPI1_IRQHandler: 1: j 1b SPI1_IRQHandler:
SPI2_IRQHandler: 1: j 1b SPI2_IRQHandler:
USART1_IRQHandler: 1: j 1b USART1_IRQHandler:
USART2_IRQHandler: 1: j 1b USART2_IRQHandler:
USART3_IRQHandler: 1: j 1b USART3_IRQHandler:
EXTI15_10_IRQHandler: 1: j 1b EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler: 1: j 1b RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler: 1: j 1b USBWakeUp_IRQHandler:
TIM8_BRK_IRQHandler: 1: j 1b TIM8_BRK_IRQHandler:
TIM8_UP_IRQHandler: 1: j 1b TIM8_UP_IRQHandler:
TIM8_TRG_COM_IRQHandler: 1: j 1b TIM8_TRG_COM_IRQHandler:
TIM8_CC_IRQHandler: 1: j 1b TIM8_CC_IRQHandler:
RNG_IRQHandler: 1: j 1b RNG_IRQHandler:
FSMC_IRQHandler: 1: j 1b FSMC_IRQHandler:
SDIO_IRQHandler: 1: j 1b SDIO_IRQHandler:
TIM5_IRQHandler: 1: j 1b TIM5_IRQHandler:
SPI3_IRQHandler: 1: j 1b SPI3_IRQHandler:
UART4_IRQHandler: 1: j 1b UART4_IRQHandler:
UART5_IRQHandler: 1: j 1b UART5_IRQHandler:
TIM6_IRQHandler: 1: j 1b TIM6_IRQHandler:
TIM7_IRQHandler: 1: j 1b TIM7_IRQHandler:
DMA2_Channel1_IRQHandler: 1: j 1b DMA2_Channel1_IRQHandler:
DMA2_Channel2_IRQHandler: 1: j 1b DMA2_Channel2_IRQHandler:
DMA2_Channel3_IRQHandler: 1: j 1b DMA2_Channel3_IRQHandler:
DMA2_Channel4_IRQHandler: 1: j 1b DMA2_Channel4_IRQHandler:
DMA2_Channel5_IRQHandler: 1: j 1b DMA2_Channel5_IRQHandler:
ETH_IRQHandler: 1: j 1b ETH_IRQHandler:
ETH_WKUP_IRQHandler: 1: j 1b ETH_WKUP_IRQHandler:
CAN2_TX_IRQHandler: 1: j 1b CAN2_TX_IRQHandler:
CAN2_RX0_IRQHandler: 1: j 1b CAN2_RX0_IRQHandler:
CAN2_RX1_IRQHandler: 1: j 1b CAN2_RX1_IRQHandler:
CAN2_SCE_IRQHandler: 1: j 1b CAN2_SCE_IRQHandler:
OTG_FS_IRQHandler: 1: j 1b OTG_FS_IRQHandler:
USBHSWakeup_IRQHandler: 1: j 1b USBHSWakeup_IRQHandler:
USBHS_IRQHandler: 1: j 1b USBHS_IRQHandler:
DVP_IRQHandler: 1: j 1b DVP_IRQHandler:
UART6_IRQHandler: 1: j 1b UART6_IRQHandler:
UART7_IRQHandler: 1: j 1b UART7_IRQHandler:
UART8_IRQHandler: 1: j 1b UART8_IRQHandler:
TIM9_BRK_IRQHandler: 1: j 1b TIM9_BRK_IRQHandler:
TIM9_UP_IRQHandler: 1: j 1b TIM9_UP_IRQHandler:
TIM9_TRG_COM_IRQHandler: 1: j 1b TIM9_TRG_COM_IRQHandler:
TIM9_CC_IRQHandler: 1: j 1b TIM9_CC_IRQHandler:
TIM10_BRK_IRQHandler: 1: j 1b TIM10_BRK_IRQHandler:
TIM10_UP_IRQHandler: 1: j 1b TIM10_UP_IRQHandler:
TIM10_TRG_COM_IRQHandler: 1: j 1b TIM10_TRG_COM_IRQHandler:
TIM10_CC_IRQHandler: 1: j 1b TIM10_CC_IRQHandler:
DMA2_Channel6_IRQHandler: 1: j 1b DMA2_Channel6_IRQHandler:
DMA2_Channel7_IRQHandler: 1: j 1b DMA2_Channel7_IRQHandler:
DMA2_Channel8_IRQHandler: 1: j 1b DMA2_Channel8_IRQHandler:
DMA2_Channel9_IRQHandler: 1: j 1b DMA2_Channel9_IRQHandler:
DMA2_Channel10_IRQHandler: 1: j 1b DMA2_Channel10_IRQHandler:
DMA2_Channel11_IRQHandler: 1: j 1b DMA2_Channel11_IRQHandler:
1:
j 1b
.section .text.handle_reset,"ax",@progbits .section .text.handle_reset,"ax",@progbits
@ -373,7 +375,7 @@ handle_reset:
/* Enable floating point and interrupt */ /* Enable floating point and interrupt */
li t0, 0x7800 li t0, 0x7800
csrs mstatus, t0 csrw mstatus, t0
la t0, _vector_base la t0, _vector_base
ori t0, t0, 3 ori t0, t0, 3

53
bsp/wch/risc-v/ch569w-evt/board/startup_gcc.S
View File

@ -85,31 +85,32 @@ _vector_base:
.weak pmt_irq_handler .weak pmt_irq_handler
.weak ecdc_irq_handler .weak ecdc_irq_handler
nmi_handler: j .L_rip nmi_handler:
hardfault_handler: j .L_rip hardfault_handler:
systick_handler: j .L_rip systick_handler:
swi_handler: j .L_rip swi_handler:
wdog_irq_handler: j .L_rip wdog_irq_handler:
tmr0_irq_handler: j .L_rip tmr0_irq_handler:
gpio_irq_handler: j .L_rip gpio_irq_handler:
spi0_irq_handler: j .L_rip spi0_irq_handler:
usbss_irq_handler: j .L_rip usbss_irq_handler:
link_irq_handler: j .L_rip link_irq_handler:
tmr1_irq_handler: j .L_rip tmr1_irq_handler:
tmr2_irq_handler: j .L_rip tmr2_irq_handler:
uart0_irq_handler: j .L_rip uart0_irq_handler:
usbhs_irq_handler: j .L_rip usbhs_irq_handler:
emmc_irq_handler: j .L_rip emmc_irq_handler:
dvp_irq_handler: j .L_rip dvp_irq_handler:
hspi_irq_handler: j .L_rip hspi_irq_handler:
spi1_irq_handler: j .L_rip spi1_irq_handler:
uart1_irq_handler: j .L_rip uart1_irq_handler:
uart2_irq_handler: j .L_rip uart2_irq_handler:
uart3_irq_handler: j .L_rip uart3_irq_handler:
serdes_irq_handler: j .L_rip serdes_irq_handler:
eth_irq_handler: j .L_rip eth_irq_handler:
pmt_irq_handler: j .L_rip pmt_irq_handler:
ecdc_irq_handler: j .L_rip ecdc_irq_handler:
j .L_rip
.L_rip: .L_rip:
csrr t0, mepc csrr t0, mepc
@ -165,7 +166,7 @@ handle_reset:
2: 2:
/* leave all interrupt disabled */ /* leave all interrupt disabled */
li t0, 0x1800 li t0, 0x1800
csrs mstatus, t0 csrw mstatus, t0
la t0, _vector_base la t0, _vector_base
ori t0, t0, 1 ori t0, t0, 1
csrw mtvec, t0 csrw mtvec, t0