heyuanjie87
GitHub
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47d941388b
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49b6614763
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@ -248,6 +248,18 @@ config ARCH_RISCV_FPU
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config ARCH_RISCV_VECTOR
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bool
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if ARCH_RISCV_VECTOR
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choice
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prompt "RISCV Vector Vlen"
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default ARCH_VECTOR_VLEN_128
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config ARCH_VECTOR_VLEN_128
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bool "128"
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config ARCH_VECTOR_VLEN_256
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bool "256"
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endchoice
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endif
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config ARCH_RISCV_FPU_S
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select ARCH_RISCV_FPU
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bool
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@ -16,7 +16,6 @@
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#include <rtconfig.h>
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#include "encoding.h"
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#include "ext_context.h"
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/* bytes of register width */
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#ifdef ARCH_CPU_64BIT
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@ -30,6 +29,8 @@
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#error "Not supported XLEN"
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#endif
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#include "ext_context.h"
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/* 33 general register + 1 padding */
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#define CTX_GENERAL_REG_NR 34
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@ -5,8 +5,8 @@ cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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if not GetDepend('ARCH_USING_ASID'):
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SrcRemove(src, ['asid.c'])
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if GetDepend('ARCH_RISCV_VECTOR'):
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CPPPATH += [cwd + '/../../vector/rvv-1.0']
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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@ -0,0 +1,112 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-10 RT-Thread the first version,
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* compatible to riscv-v-spec-1.0
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*/
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#ifndef __RVV_CONTEXT_1_0_H__
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#define __RVV_CONTEXT_1_0_H__
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#if defined(ARCH_VECTOR_VLEN_128)
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#define CTX_VECTOR_REGS 64
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#elif defined(ARCH_VECTOR_VLEN_256)
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#define CTX_VECTOR_REGS 128
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#else
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#error "No supported VLEN"
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#endif /* VLEN */
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#define CTX_VECTOR_REG_NR (CTX_VECTOR_REGS + 4)
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#ifdef __ASSEMBLY__
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/**
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* ==================================
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* VECTOR EXTENSION
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* ==================================
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*/
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#define VEC_FRAME_VSTART (0 * REGBYTES)
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#define VEC_FRAME_VTYPE (1 * REGBYTES)
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#define VEC_FRAME_VL (2 * REGBYTES)
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#define VEC_FRAME_VCSR (3 * REGBYTES)
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#define VEC_FRAME_V0 (4 * REGBYTES)
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.macro GET_VEC_FRAME_LEN, xreg
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csrr \xreg, vlenb
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slli \xreg, \xreg, 5
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addi \xreg, \xreg, 4 * REGBYTES
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.endm
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/**
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* @brief save vector extension hardware state
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*
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* @param dst register storing bottom of storage block
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*
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*/
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.macro SAVE_VECTOR, dst
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mv t1, \dst
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csrr t0, vstart
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STORE t0, VEC_FRAME_VSTART(t1)
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csrr t0, vtype
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STORE t0, VEC_FRAME_VTYPE(t1)
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csrr t0, vl
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STORE t0, VEC_FRAME_VL(t1)
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csrr t0, vcsr
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STORE t0, VEC_FRAME_VCSR(t1)
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addi t1, t1, VEC_FRAME_V0
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// config vector setting,
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// t2 is updated to length of a vector group in bytes
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VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
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vse8.v v0, (t1)
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add t1, t1, t2
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vse8.v v8, (t1)
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add t1, t1, t2
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vse8.v v16, (t1)
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add t1, t1, t2
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vse8.v v24, (t1)
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.endm
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/**
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* @brief restore vector extension hardware states
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*
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* @param dst register storing bottom of storage block
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*
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*/
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.macro RESTORE_VECTOR, dst
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// restore vector registers first since it will modify vector states
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mv t0, \dst
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addi t1, t0, VEC_FRAME_V0
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VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
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vle8.v v0, (t1)
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add t1, t1, t2
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vle8.v v8, (t1)
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add t1, t1, t2
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vle8.v v16, (t1)
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add t1, t1, t2
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vle8.v v24, (t1)
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mv t1, t0
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LOAD t0, VEC_FRAME_VSTART(t1)
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csrw vstart, t0
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LOAD t0, VEC_FRAME_VCSR(t1)
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csrw vcsr, t0
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LOAD t0, VEC_FRAME_VTYPE(t1)
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LOAD t3, VEC_FRAME_VL(t1)
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VEC_CONFIG_SET_VL_VTYPE(t3, t0)
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.endm
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#endif
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#endif /* __RVV_CONTEXT_H__ */
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-10 RT-Thread the first version,
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* compatible to riscv-v-spec-1.0
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*/
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#ifndef __VECTOR_ENCODING_1_0_H__
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#define __VECTOR_ENCODING_1_0_H__
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/* mstatus/sstatus */
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#define MSTATUS_VS 0x00000600
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#define SSTATUS_VS 0x00000600 /* Vector Status */
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#define SSTATUS_VS_INITIAL 0x00000200
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#define SSTATUS_VS_CLEAN 0x00000400
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#define SSTATUS_VS_DIRTY 0x00000600
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#ifdef __ASSEMBLY__
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/**
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* assembler names used for vset{i}vli vtypei immediate
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*/
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#define VEC_IMM_SEW_8 e8
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#define VEC_IMM_SEW_16 e16
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#define VEC_IMM_SEW_32 e32
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#define VEC_IMM_SEW_64 e64
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/* group setting, encoding by multiplier */
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#define VEC_IMM_LMUL_F8 mf8
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#define VEC_IMM_LMUL_F4 mf4
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#define VEC_IMM_LMUL_F2 mf2
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#define VEC_IMM_LMUL_1 m1
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#define VEC_IMM_LMUL_2 m2
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#define VEC_IMM_LMUL_4 m4
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#define VEC_IMM_LMUL_8 m8
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/* TAIL & MASK agnostic bits */
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#define VEC_IMM_TAIL_AGNOSTIC ta
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#define VEC_IMM_MASK_AGNOSTIC ma
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#define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC
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#define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC
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#define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC
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/**
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* configuration setting instruction
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*/
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#define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype
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#define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype
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#endif
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#endif /* __VECTOR_ENCODING_H__ */
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