[libcpu] remove nds32 porting
This commit is contained in:
liang yongxiang
parent
ae98804dfb
commit
46b9be6038
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@ -1,188 +0,0 @@
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#include "nds32.h"
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#include "os_cpu_common.h"
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#include "config.h"
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.align 4
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! void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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! R0 --> from
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! R1 --> to
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.section .text
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.global rt_hw_context_switch_interrupt
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.global rt_hw_context_switch
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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push25 $r6,#8 ! {$r6, $fp, $gp, $lp}
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la $r2, rt_thread_switch_interrupt_flag
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lw $r3, [$r2]
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movi $r4, #1
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beq $r3, $r4, _reswitch
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sw $r4, [$r2] ! set rt_thread_switch_interrupt_flag to 1
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la $r2, rt_interrupt_from_thread
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sw $r0, [$r2] ! set rt_interrupt_from_thread
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_reswitch:
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la $r2, rt_interrupt_to_thread
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sw $r1, [$r2] ! set rt_interrupt_to_thread
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bal hal_intc_swi_trigger ! trigger the swi exception (causes context switch)
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pop25 $r6,#8 ! {$r6, $fp, $gp, $lp}
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! R0 --> switch from thread stack
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! R1 --> switch to thread stack
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! psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
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.align 4
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.global OS_Trap_Interrupt_SWI
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OS_Trap_Interrupt_SWI:
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! pushm $r0, $r5
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setgie.d ! disable interrupt to protect context switch
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dsb
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IntlDescend ! Descend interrupt level
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movi $r0, 0x0
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mtsr $r0, $INT_PEND ! clean SWI pending
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la $r0, rt_thread_switch_interrupt_flag ! get rt_thread_switch_interrupt_flag
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lw $r1, [$r0]
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beqz $r1, pendsv_exit ! swi has already been handled
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movi $r1, #0
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sw $r1, [$r0] ! clear rt_thread_switch_interrupt_flag to 0
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la $r0, rt_interrupt_from_thread
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lw $r1, [$r0]
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beqz $r1, switch_to_thread ! skip register save at the first time(os startup phase)
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SAVE_ALL
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move $r1, $sp
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la $r0, rt_interrupt_from_thread
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lw $r0, [$r0]
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sw $r1, [$r0]
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switch_to_thread:
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la $r1, rt_interrupt_to_thread
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lw $r1, [$r1]
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lw $r1, [$r1] ! load thread stack pointer
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move $sp, $r1 ! update stack pointer
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RESTORE_ALL ! pop registers
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pendsv_exit:
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setgie.e
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iret
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.align 4
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! void rt_hw_context_switch_to(rt_uint32 to);
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! R0 --> to
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.global rt_hw_context_switch_to
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rt_hw_context_switch_to:
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la $r1, rt_interrupt_to_thread
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sw $r0, [$r1]
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! set from thread to 0
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la $r1, rt_interrupt_from_thread
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movi $r0, #0
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sw $r0, [$r1]
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! set interrupt flag to 1
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la $r1, rt_thread_switch_interrupt_flag
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movi $r0, #1
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sw $r0, [$r1]
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! set the SWI exception priority(must be the lowest level)
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! todo
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! trigger the SWI exception (causes context switch)
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jal hal_intc_swi_trigger
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setgie.e ! enable interrupts at processor level
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1:
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b 1b ! never reach here
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#ifndef VECTOR_NUMINTRS
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#define VECTOR_NUMINTRS 32
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#endif
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.global OS_Trap_Int_Common
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! Set up Interrupt vector ISR
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! HW#IRQ_SWI_VECTOR : OS_Trap_Interrupt_SWI (SWI)
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! HW#n : OS_Trap_Int_Common
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.macro SET_HWISR num
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.global OS_Trap_Interrupt_HW\num
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.if \num == IRQ_SWI_VECTOR
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.set OS_Trap_Interrupt_HW\num, OS_Trap_Interrupt_SWI
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.else
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.set OS_Trap_Interrupt_HW\num, OS_Trap_Int_Common
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.endif
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.endm
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.altmacro
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.set irqno, 0
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.rept VECTOR_NUMINTRS
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SET_HWISR %irqno
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.set irqno, irqno+1
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.endr
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.noaltmacro
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! .global OS_Trap_Int_Common
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OS_Trap_Int_Common:
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#ifdef MPU_SUPPORT
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mfsr $p1, $PSW
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ori $p1, $p1, (PSW_mskIT | PSW_mskDT)
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mtsr $p1, $PSW ! enable IT/DT
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dsb
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pushm $r0, $r5
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move $r0, $p0 ! IRQ number
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#endif
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! $r0 : HW Interrupt vector number
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SAVE_CALLER
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IntlDescend ! Descend interrupt level
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mfsr $r1, $IPSW ! Use IPSW.CPL to check come from thread or ISR
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srli45 $r1, #PSW_offCPL
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fexti33 $r1, #0x2 ! IPSW.CPL
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bnec $r1, #0x7, 2f ! IPSW.CPL != 7, come form ISR, reentrant
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move $fp, $sp ! save old stack pointer
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la $sp, __OS_Int_Stack ! switch to interrupt stack
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2:
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setgie.e ! allow nested now
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! The entire CPU state is now stashed on the stack,
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! and the stack is also 8-byte alignment.
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! We can call C program based interrupt handler now.
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la $r1, OS_CPU_Vector_Table
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lw $r1, [$r1+($r0<<2)] ! ISR function pointer
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jral $r1 ! Call ISR
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la $r1, __OS_Int_Stack ! Check for nested interruption return
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bne $r1, $sp, 3f ! $sp != __OS_Int_Stack?
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move $sp, $fp ! Move back to the thread stack
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3:
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RESTORE_CALLER
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iret
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! .set OS_Trap_Interrupt_HW9, OS_Trap_Interrupt_SWI
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! .set OS_Trap_Interrupt_HW19, OS_Trap_Int_Common
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!*********************************************
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! POINTERS TO VARIABLES
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!*********************************************
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#ifdef MPU_SUPPORT
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.section privileged_data
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#else
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.section .bss
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#endif
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.skip IRQ_STACK_SIZE
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.align 3
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__OS_Int_Stack:
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.end
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@ -1,202 +0,0 @@
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/*
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* File : cpuport.c
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-08-25 Archer first version
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*/
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#include <rtthread.h>
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#include "nds32.h"
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* SAVE_CONTEXT had been called.
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*
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* See header file for description.
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*
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*
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* Stack Layout:
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* High |-----------------|
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* | $R5 |
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* |-----------------|
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* | . |
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* | . |
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* |-----------------|
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* | $R0 |
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* |-----------------|
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* | $R30 (LP) |
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* |-----------------|
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* | $R29 (GP) |
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* |-----------------|
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* | $R28 (FP) |
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* |-----------------|
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* | $R15 $R27 |
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* |-----------------|
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* | $R10 $R26 |
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* |-----------------|
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* | . |
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* | . |
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* |-----------------|
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* | $R6 |
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* |-----------------|
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* | $IFC_LP | (Option)
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* |-----------------|
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* | $LC/$LE/$LB | (Option)
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* | (ZOL) |
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* |-----------------|
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* | $IPSW |
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* |-----------------|
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* | $IPC |
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* |-----------------|
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* | Dummy word | (Option, only exist when IFC & ZOL both configured)
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* |-----------------|
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* | $FPU | (Option)
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* |-----------------|
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* Low
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*
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*/
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struct stack_frame
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{
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rt_uint32_t topOfStack[34];
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};
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/* flag in interrupt handling */
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/* exception hook */
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static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
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rt_base_t rt_hw_interrupt_disable(void)
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{
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rt_base_t level = __nds32__mfsr(NDS32_SR_PSW);
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GIE_DISABLE();
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return level;
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}
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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if (level & PSW_mskGIE)
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GIE_ENABLE();
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}
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/* For relax support, must initial $gp at task init*/
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extern uint32_t _SDA_BASE_ __attribute__ ((weak));
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/**************************************************************
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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**************************************************************/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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rt_int32_t i;
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rt_uint32_t *pxTopOfStack;
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pxTopOfStack = (rt_uint32_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 4);
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/* Simulate the stack frame as it would be created by a context switch */
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/* R0 ~ R5 registers */
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for (i = 5; i >= 1; i--) /* R5, R4, R3, R2 and R1. */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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*--pxTopOfStack = (rt_uint32_t)parameter; /* R0 : Argument */
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/* R6 ~ R30 registers */
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*--pxTopOfStack = (rt_uint32_t)texit; /* R30: $LP */
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*--pxTopOfStack = (rt_uint32_t)&_SDA_BASE_; /* R29: $GP */
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*--pxTopOfStack = (rt_uint32_t)0x2828282828; /* R28: $FP */
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#ifdef __NDS32_REDUCE_REGS__
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*--pxTopOfStack = (rt_uint32_t)0x1515151515; /* R15 */
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for (i = 10; i >= 6; i--) /* R10 ~ R6 */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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#else
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for (i = 27; i >= 6; i--) /* R27 ~ R6 */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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#endif
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/* IFC system register */
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#ifdef __TARGET_IFC_EXT
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $IFC_LP */
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#endif
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/* ZOL system registers */
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#ifdef __TARGET_ZOL_EXT
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LC */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LE */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LB */
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#endif
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/* IPSW and IPC system registers */
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/* Default IPSW: enable GIE, set CPL to 7, clear IFCON */
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i = (__nds32__mfsr(NDS32_SR_PSW) | PSW_mskGIE | PSW_mskCPL) & ~PSW_mskIFCON;
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*--pxTopOfStack = (rt_uint32_t)i; /* $IPSW */
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*--pxTopOfStack = (rt_uint32_t)tentry; /* $IPC */
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/* Dummy word for 8-byte stack alignment */
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#if defined(__TARGET_IFC_EXT) && defined(__TARGET_ZOL_EXT)
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*--pxTopOfStack = (rt_uint32_t)0xFFFFFFFF; /* Dummy */
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#endif
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/* FPU registers */
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#ifdef __TARGET_FPU_EXT
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for (i = 0; i < FPU_REGS; i++)
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*--pxTopOfStack = (rt_uint32_t)0x0; /* FPU */
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#endif
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return (rt_uint8_t *)pxTopOfStack;
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}
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/**
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* This function set the hook, which is invoked on fault exception handling.
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*
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* @param exception_handle the exception handling hook function.
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*/
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void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context))
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{
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rt_exception_hook = exception_handle;
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}
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#ifdef RT_USING_CPU_FFS
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/**
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* This function finds the first bit set (beginning with the least significant bit)
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* in value and return the index of that bit.
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*
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* Bits are numbered starting at 1 (the least significant bit). A return value of
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* zero from any of these functions means that the argument was zero.
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*
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* @return return the index of the first bit set. If value is 0, then this function
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* shall return 0.
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*/
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#if defined(__GNUC__)
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int __rt_ffs(int value)
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{
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return __builtin_ffs(value);
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}
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#endif
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#endif
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