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Merge remote-tracking branch 'upstream/master'

This commit is contained in:
ZYH 2018-03-23 09:37:04 +08:00
parent 5713db3fb9 39ebfa9e32
commit 45c9b8c19a
11 changed files with 3367 additions and 2731 deletions
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2
bsp/imxrt1052-evk/drivers/SConscript
View File

@ -7,7 +7,7 @@ cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drivers.
src = Split("""
board.c
usart.c
drv_uart.c
hyper_flash_boot.c
drv_sdram.c
""")

2
bsp/imxrt1052-evk/drivers/board.c
View File

@ -16,7 +16,7 @@
#include <rtthread.h>
#include "board.h"
#include "usart.h"
#include "drv_uart.h"
static struct rt_memheap system_heap;

461
bsp/imxrt1052-evk/drivers/drv_pin.c
View File

@ -9,7 +9,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-03-13 Liuguang the first version.
* 2018-03-13 Liuguang the first version.
* 2018-03-19 Liuguang add GPIO interrupt mode support.
*/
#include "drv_pin.h"
@ -19,12 +20,10 @@
#ifdef RT_USING_PIN
/* GPIO外设时钟会在GPIO_PinInit中自动配置, 如果定义了以下宏则不会自动配置 */
#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
#endif
/* RT1052 PIN描述结构体 */
struct rt1052_pin
{
rt_uint16_t pin;
@ -32,10 +31,18 @@ struct rt1052_pin
rt_uint32_t gpio_pin;
};
struct rt1052_irq
{
rt_uint16_t enable;
struct rt_pin_irq_hdr irq_info;
};
#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
#define __RT1052_PIN_DEFAULT {0, 0, 0}
#define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN}
static struct rt_pin_ops rt1052_pin_ops;
static struct rt1052_pin rt1052_pin_map[] =
{
__RT1052_PIN_DEFAULT,
@ -179,6 +186,279 @@ static struct rt1052_pin rt1052_pin_map[] =
__RT1052_PIN(127, GPIO5, 2) /* PMIC_STBY_REQ */
};
static struct rt1052_irq rt1052_irq_map[] =
{
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
};
void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
{
if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0)
{
GPIO_PortClearInterruptFlags(base, gpio_pin);
if(rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
{
rt1052_irq_map[gpio_pin].irq_info.hdr(rt1052_irq_map[gpio_pin].irq_info.args);
}
}
}
void GPIO1_Combined_0_15_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{
gpio_isr(GPIO1, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO1_Combined_16_31_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{
gpio_isr(GPIO1, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO2_Combined_0_15_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{
gpio_isr(GPIO2, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO2_Combined_16_31_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{
gpio_isr(GPIO2, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO3_Combined_0_15_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{
gpio_isr(GPIO3, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO3_Combined_16_31_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{
gpio_isr(GPIO3, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO4_Combined_0_15_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{
gpio_isr(GPIO4, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO4_Combined_16_31_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{
gpio_isr(GPIO4, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
void GPIO5_Combined_0_15_IRQHandler(void)
{
rt_uint8_t gpio_pin;
rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++)
{
gpio_isr(GPIO5, gpio_pin);
}
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
rt_interrupt_leave();
}
static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
{
IRQn_Type irq_num;
if(gpio == GPIO1)
{
if(gpio_pin <= 15)
{
irq_num = GPIO1_Combined_0_15_IRQn;
}
else
{
irq_num = GPIO1_Combined_16_31_IRQn;
}
}
else if(gpio == GPIO2)
{
if(gpio_pin <= 15)
{
irq_num = GPIO2_Combined_0_15_IRQn;
}
else
{
irq_num = GPIO2_Combined_16_31_IRQn;
}
}
else if(gpio == GPIO3)
{
if(gpio_pin <= 15)
{
irq_num = GPIO3_Combined_0_15_IRQn;
}
else
{
irq_num = GPIO3_Combined_16_31_IRQn;
}
}
else if(gpio == GPIO4)
{
if(gpio_pin <= 15)
{
irq_num = GPIO4_Combined_0_15_IRQn;
}
else
{
irq_num = GPIO4_Combined_16_31_IRQn;
}
}
else if(gpio == GPIO5)
{
if(gpio_pin <= 15)
{
irq_num = GPIO5_Combined_0_15_IRQn;
}
else
{
irq_num = GPIO5_Combined_16_31_IRQn;
}
}
return irq_num;
}
static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
gpio_pin_config_t gpio;
@ -193,15 +473,15 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0);
}
else
{
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0);
}
/* 配置IOMUXC: 将IO配置为GPIO */
IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0);
gpio.outputLogic = 0;
gpio.interruptMode = kGPIO_NoIntmode;
@ -243,7 +523,6 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
break;
}
/* 配置GPIO模式: 上下拉模式, 开漏模, IO翻转速度(50MHz) */
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value);
GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
@ -259,17 +538,175 @@ static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
GPIO_PinWrite(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, value);
}
static struct rt_pin_ops rt1052_pin_ops =
static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
.pin_mode = rt1052_pin_mode,
.pin_read = rt1052_pin_read,
.pin_write = rt1052_pin_write
};
struct rt1052_pin* pin_map = RT_NULL;
struct rt1052_irq* irq_map = RT_NULL;
pin_map = &rt1052_pin_map[pin];
irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL)
{
return RT_ENOSYS;
}
if(irq_map->enable == PIN_IRQ_ENABLE)
{
return RT_EBUSY;
}
irq_map->irq_info.pin = pin;
irq_map->irq_info.hdr = hdr;
irq_map->irq_info.mode = mode;
irq_map->irq_info.args = args;
return RT_EOK;
}
static rt_err_t rt1052_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
struct rt1052_pin* pin_map = RT_NULL;
struct rt1052_irq* irq_map = RT_NULL;
pin_map = &rt1052_pin_map[pin];
irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL)
{
return RT_ENOSYS;
}
if(irq_map->enable == PIN_IRQ_DISABLE)
{
return RT_EOK;
}
irq_map->irq_info.pin = PIN_IRQ_PIN_NONE;
irq_map->irq_info.hdr = RT_NULL;
irq_map->irq_info.mode = PIN_IRQ_MODE_RISING;
irq_map->irq_info.args = RT_NULL;
return RT_EOK;
}
static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
gpio_pin_config_t gpio;
IRQn_Type irq_num;
struct rt1052_pin* pin_map = RT_NULL;
struct rt1052_irq* irq_map = RT_NULL;
pin_map = &rt1052_pin_map[pin];
irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL)
{
return RT_ENOSYS;
}
if(enabled == PIN_IRQ_ENABLE)
{
if(irq_map->enable == PIN_IRQ_ENABLE)
{
return RT_EBUSY;
}
if(irq_map->irq_info.pin != pin)
{
return RT_EIO;
}
irq_map->enable = PIN_IRQ_ENABLE;
if(rt1052_pin_map[pin].gpio != GPIO5)
{
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0);
}
else
{
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0);
}
gpio.direction = kGPIO_DigitalInput;
gpio.outputLogic = 0;
switch(irq_map->irq_info.mode)
{
case PIN_IRQ_MODE_RISING:
{
gpio.interruptMode = kGPIO_IntRisingEdge;
}
break;
case PIN_IRQ_MODE_FALLING:
{
gpio.interruptMode = kGPIO_IntFallingEdge;
}
break;
case PIN_IRQ_MODE_RISING_FALLING:
{
gpio.interruptMode = kGPIO_IntRisingOrFallingEdge;
}
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
{
gpio.interruptMode = kGPIO_IntHighLevel;
}
break;
case PIN_IRQ_MODE_LOW_LEVEL:
{
gpio.interruptMode = kGPIO_IntLowLevel;
}
break;
}
irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
EnableIRQ(irq_num);
GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin);
}
else if(enabled == PIN_IRQ_DISABLE)
{
if(irq_map->enable == PIN_IRQ_DISABLE)
{
return RT_EOK;
}
irq_map->enable = PIN_IRQ_DISABLE;
irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
NVIC_DisableIRQ(irq_num);
}
else
{
return RT_EINVAL;
}
return RT_EOK;
}
int rt_hw_pin_init(void)
{
int ret = RT_EOK;
rt1052_pin_ops.pin_mode = rt1052_pin_mode;
rt1052_pin_ops.pin_read = rt1052_pin_read;
rt1052_pin_ops.pin_write = rt1052_pin_write;
rt1052_pin_ops.pin_attach_irq = rt1052_pin_attach_irq;
rt1052_pin_ops.pin_dettach_irq = rt1052_pin_dettach_irq;
rt1052_pin_ops.pin_irq_enable = rt1052_pin_irq_enable;
ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL);
return ret;

1
bsp/imxrt1052-evk/drivers/drv_pin.h
View File

@ -10,6 +10,7 @@
* Change Logs:
* Date Author Notes
* 2018-03-13 Liuguang the first version.
* 2018-03-19 Liuguang add GPIO interrupt mode support.
*/
#ifndef __DRV_PIN_H__

244
bsp/imxrt1052-evk/drivers/usart.c → bsp/imxrt1052-evk/drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* File : usart.c
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2013, RT-Thread Development Team
*
@ -10,9 +10,10 @@
* Change Logs:
* Date Author Notes
* 2017-10-10 Tanek the first version
* 2018-03-17 laiyiketang Add other uart.
*/
#include <rtthread.h>
#include "usart.h"
#include "drv_uart.h"
#include "fsl_common.h"
#include "fsl_lpuart.h"
@ -20,14 +21,21 @@
#ifdef RT_USING_SERIAL
#if !defined(RT_USING_UART0) && !defined(RT_USING_UART1) && \
!defined(RT_USING_UART2) && !defined(RT_USING_UART3) && \
!defined(RT_USING_UART4) && !defined(RT_USING_UART5) && \
!defined(RT_USING_UART6) && !defined(RT_USING_UART7)
/* GPIO外设时钟会在LPUART_Init中自动配置, 如果定义了以下宏则不会自动配置 */
#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
#endif
#if !defined(RT_USING_UART1) && !defined(RT_USING_UART2) && \
!defined(RT_USING_UART3) && !defined(RT_USING_UART4) && \
!defined(RT_USING_UART5) && !defined(RT_USING_UART6) && \
!defined(RT_USING_UART7) && !defined(RT_USING_UART8)
#error "Please define at least one UARTx"
#endif
#include <rtdevice.h>
/* imxrt uart driver */
@ -55,7 +63,7 @@ void LPUART1_IRQHandler(void)
#if defined(RT_USING_UART2)
struct rt_serial_device serial2;
void USART2_IRQHandler(void)
void LPUART2_IRQHandler(void)
{
uart_isr(&serial2);
}
@ -65,7 +73,7 @@ void USART2_IRQHandler(void)
#if defined(RT_USING_UART3)
struct rt_serial_device serial3;
void UART3_IRQHandler(void)
void LPUART3_IRQHandler(void)
{
uart_isr(&serial3);
}
@ -75,7 +83,7 @@ void UART3_IRQHandler(void)
#if defined(RT_USING_UART4)
struct rt_serial_device serial4;
void UART4_IRQHandler(void)
void LPUART4_IRQHandler(void)
{
uart_isr(&serial4);
}
@ -84,7 +92,7 @@ void UART4_IRQHandler(void)
#if defined(RT_USING_UART5)
struct rt_serial_device serial5;
void USART5_IRQHandler(void)
void LPUART5_IRQHandler(void)
{
uart_isr(&serial5);
}
@ -94,7 +102,7 @@ void USART5_IRQHandler(void)
#if defined(RT_USING_UART6)
struct rt_serial_device serial6;
void UART6_IRQHandler(void)
void LPUART6_IRQHandler(void)
{
uart_isr(&serial6);
}
@ -104,7 +112,7 @@ void UART6_IRQHandler(void)
#if defined(RT_USING_UART7)
struct rt_serial_device serial7;
void UART7_IRQHandler(void)
void LPUART7_IRQHandler(void)
{
uart_isr(&serial7);
}
@ -114,7 +122,7 @@ void UART7_IRQHandler(void)
#if defined(RT_USING_UART8)
struct rt_serial_device serial8;
void UART8_IRQHandler(void)
void LPUART8_IRQHandler(void)
{
uart_isr(&serial8);
}
@ -122,14 +130,70 @@ void UART8_IRQHandler(void)
#endif /* RT_USING_UART8 */
static const struct imxrt_uart uarts[] = {
#ifdef RT_USING_UART1
#ifdef RT_USING_UART1
{
LPUART1,
LPUART1_IRQn,
&serial1,
"uart1",
},
#endif
#endif
#ifdef RT_USING_UART2
{
LPUART2,
LPUART2_IRQn,
&serial2,
"uart2",
},
#endif
#ifdef RT_USING_UART3
{
LPUART3,
LPUART3_IRQn,
&serial3,
"uart3",
},
#endif
#ifdef RT_USING_UART4
{
LPUART4,
LPUART4_IRQn,
&serial4,
"uart4",
},
#endif
#ifdef RT_USING_UART5
{
LPUART5,
LPUART5_IRQn,
&serial5,
"uart5",
},
#endif
#ifdef RT_USING_UART6
{
LPUART6,
LPUART6_IRQn,
&serial6,
"uart6",
},
#endif
#ifdef RT_USING_UART7
{
LPUART7,
LPUART7_IRQn,
&serial7,
"uart7",
},
#endif
#ifdef RT_USING_UART8
{
LPUART8,
LPUART8_IRQn,
&serial8,
"uart8",
},
#endif
};
@ -164,19 +228,20 @@ uint32_t BOARD_DebugConsoleSrcFreq(void)
*/
void imxrt_uart_gpio_init(struct imxrt_uart *uart)
{
if (uart->uart_base == LPUART1)
if (uart->uart_base != RT_NULL)
{
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
#ifdef RT_USING_UART1
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
@ -185,8 +250,8 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
@ -194,6 +259,128 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef RT_USING_UART2
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0x10B0u);
#endif
#ifdef RT_USING_UART3
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
0x10B0u);
#endif
#ifdef RT_USING_UART4
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_00_LPUART4_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_01_LPUART4_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_00_LPUART4_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_01_LPUART4_RX,
0x10B0u);
#endif
#ifdef RT_USING_UART5
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_12_LPUART5_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_13_LPUART5_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_12_LPUART5_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_13_LPUART5_RX,
0x10B0u);
#endif
#ifdef RT_USING_UART6
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
0x10B0u);
#endif
#ifdef RT_USING_UART7
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_31_LPUART7_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_32_LPUART7_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_31_LPUART7_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_32_LPUART7_RX,
0x10B0u);
#endif
#ifdef RT_USING_UART8
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
0x10B0u);
#endif
}
else
{
@ -324,10 +511,10 @@ static void uart_isr(struct rt_serial_device *serial)
LPUART_Type *base;
RT_ASSERT(serial != RT_NULL);
uart = (struct imxrt_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
base = uart->uart_base;
RT_ASSERT(base != RT_NULL);
@ -339,7 +526,7 @@ static void uart_isr(struct rt_serial_device *serial)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/* If RX overrun. */
if (LPUART_STAT_OR_MASK & base->STAT)
{
@ -363,7 +550,6 @@ int imxrt_hw_usart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &imxrt_uart_ops;

6
bsp/imxrt1052-evk/drivers/usart.h → bsp/imxrt1052-evk/drivers/drv_uart.h
View File

@ -1,5 +1,5 @@
/*
* File : usart.h
* File : drv_uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
@ -12,8 +12,8 @@
* 2017-10-10 Tanek the first version
*/
#ifndef __USART_H__
#define __USART_H__
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rthw.h>
#include <rtthread.h>

5099
bsp/imxrt1052-evk/project.ewp
View File

File diff suppressed because it is too large Load Diff

19
bsp/imxrt1052-evk/project.uvoptx
View File

@ -73,7 +73,7 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
@ -101,7 +101,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>2</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -164,11 +166,16 @@
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<Lin2Executable></Lin2Executable>
<Lin2ConfigFile></Lin2ConfigFile>
<bLin2Auto>0</bLin2Auto>
<bAutoGenD>0</bAutoGenD>
<bAuto2GenD>0</bAuto2GenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>

8
bsp/imxrt1052-evk/project.uvprojx
View File

@ -8,11 +8,13 @@
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>MIMXRT1052:M7</Device>
<Vendor>NXP</Vendor>
<PackID>NXP.iMXRT_DFP.1.0.1</PackID>
<PackID>NXP.iMXRT_DFP.1.0.2</PackID>
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
<Cpu>IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
@ -414,9 +416,9 @@
</Files>
<Files>
<File>
<FileName>usart.c</FileName>
<FileName>drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\usart.c</FilePath>
<FilePath>drivers\drv_uart.c</FilePath>
</File>
</Files>
<Files>

6
bsp/tm4c129x/libraries/SConscript
View File

@ -18,12 +18,6 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPPATH = [cwd, cwd + '/inc', cwd + '/driverlib']
CPPDEFINES = [rtconfig.PART_TYPE]
if rtconfig.CROSS_TOOL == 'gcc':
CPPDEFINES += ['gcc'];
CPPDEFINES += ['uint_fast8_t=uint32_t'];
CPPDEFINES += ['uint_fast32_t=uint32_t'];
CPPDEFINES += ['int_fast8_t=int32_t'];
CPPDEFINES += ['uint_fast16_t=uint32_t'];
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')

250
components/libc/compilers/minilibc/stdint.h
View File

@ -1,18 +1,75 @@
/*
* ISO C Standard: 7.18 Integer types <stdint.h>
*/
#ifndef __STDINT_H__
#define __STDINT_H__
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
/* 7.8.1.1 Exact-width integer types */
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#ifdef __INT8_TYPE__
typedef __INT8_TYPE__ int8_t;
#endif
#ifdef __INT16_TYPE__
typedef __INT16_TYPE__ int16_t;
#endif
#ifdef __INT32_TYPE__
typedef __INT32_TYPE__ int32_t;
#endif
#ifdef __INT64_TYPE__
typedef __INT64_TYPE__ int64_t;
#endif
#ifdef __UINT8_TYPE__
typedef __UINT8_TYPE__ uint8_t;
#endif
#ifdef __UINT16_TYPE__
typedef __UINT16_TYPE__ uint16_t;
#endif
#ifdef __UINT32_TYPE__
typedef __UINT32_TYPE__ uint32_t;
#endif
#ifdef __UINT64_TYPE__
typedef __UINT64_TYPE__ uint64_t;
#endif
typedef long long int64_t;
typedef unsigned long long uint64_t;
typedef signed long intptr_t;
typedef unsigned long uintptr_t;
/* 7.8.1.2 Minimum-width integer types */
typedef __INT_LEAST8_TYPE__ int_least8_t;
typedef __INT_LEAST16_TYPE__ int_least16_t;
typedef __INT_LEAST32_TYPE__ int_least32_t;
typedef __INT_LEAST64_TYPE__ int_least64_t;
typedef __UINT_LEAST8_TYPE__ uint_least8_t;
typedef __UINT_LEAST16_TYPE__ uint_least16_t;
typedef __UINT_LEAST32_TYPE__ uint_least32_t;
typedef __UINT_LEAST64_TYPE__ uint_least64_t;
/* 7.8.1.3 Fastest minimum-width integer types */
typedef __INT_FAST8_TYPE__ int_fast8_t;
typedef __INT_FAST16_TYPE__ int_fast16_t;
typedef __INT_FAST32_TYPE__ int_fast32_t;
typedef __INT_FAST64_TYPE__ int_fast64_t;
typedef __UINT_FAST8_TYPE__ uint_fast8_t;
typedef __UINT_FAST16_TYPE__ uint_fast16_t;
typedef __UINT_FAST32_TYPE__ uint_fast32_t;
typedef __UINT_FAST64_TYPE__ uint_fast64_t;
/* 7.8.1.4 Integer types capable of holding object pointers */
#ifdef __INTPTR_TYPE__
typedef __INTPTR_TYPE__ intptr_t;
#endif
#ifdef __UINTPTR_TYPE__
typedef __UINTPTR_TYPE__ uintptr_t;
#endif
/* 7.8.1.5 Greatest-width integer types */
typedef __INTMAX_TYPE__ intmax_t;
typedef __UINTMAX_TYPE__ uintmax_t;
#if (!defined __cplusplus || __cplusplus >= 201103L \
|| defined __STDC_LIMIT_MACROS)
/*
* 7.18.2 Limits of specified-width integer types.
@ -22,17 +79,170 @@ typedef unsigned long uintptr_t;
*/
/* 7.18.2.1 Limits of exact-width integer types */
#define INT8_MIN (-0x7f - 1)
#define INT16_MIN (-0x7fff - 1)
#define INT32_MIN (-0x7fffffff - 1)
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#ifdef __INT8_MAX__
# undef INT8_MAX
# define INT8_MAX __INT8_MAX__
# undef INT8_MIN
# define INT8_MIN (-INT8_MAX - 1)
#endif
#ifdef __UINT8_MAX__
# undef UINT8_MAX
# define UINT8_MAX __UINT8_MAX__
#endif
#ifdef __INT16_MAX__
# undef INT16_MAX
# define INT16_MAX __INT16_MAX__
# undef INT16_MIN
# define INT16_MIN (-INT16_MAX - 1)
#endif
#ifdef __UINT16_MAX__
# undef UINT16_MAX
# define UINT16_MAX __UINT16_MAX__
#endif
#ifdef __INT32_MAX__
# undef INT32_MAX
# define INT32_MAX __INT32_MAX__
# undef INT32_MIN
# define INT32_MIN (-INT32_MAX - 1)
#endif
#ifdef __UINT32_MAX__
# undef UINT32_MAX
# define UINT32_MAX __UINT32_MAX__
#endif
#ifdef __INT64_MAX__
# undef INT64_MAX
# define INT64_MAX __INT64_MAX__
# undef INT64_MIN
# define INT64_MIN (-INT64_MAX - 1)
#endif
#ifdef __UINT64_MAX__
# undef UINT64_MAX
# define UINT64_MAX __UINT64_MAX__
#endif
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#undef INT_LEAST8_MAX
#define INT_LEAST8_MAX __INT_LEAST8_MAX__
#undef INT_LEAST8_MIN
#define INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)
#undef UINT_LEAST8_MAX
#define UINT_LEAST8_MAX __UINT_LEAST8_MAX__
#undef INT_LEAST16_MAX
#define INT_LEAST16_MAX __INT_LEAST16_MAX__
#undef INT_LEAST16_MIN
#define INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)
#undef UINT_LEAST16_MAX
#define UINT_LEAST16_MAX __UINT_LEAST16_MAX__
#undef INT_LEAST32_MAX
#define INT_LEAST32_MAX __INT_LEAST32_MAX__
#undef INT_LEAST32_MIN
#define INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)
#undef UINT_LEAST32_MAX
#define UINT_LEAST32_MAX __UINT_LEAST32_MAX__
#undef INT_LEAST64_MAX
#define INT_LEAST64_MAX __INT_LEAST64_MAX__
#undef INT_LEAST64_MIN
#define INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)
#undef UINT_LEAST64_MAX
#define UINT_LEAST64_MAX __UINT_LEAST64_MAX__
#undef INT_FAST8_MAX
#define INT_FAST8_MAX __INT_FAST8_MAX__
#undef INT_FAST8_MIN
#define INT_FAST8_MIN (-INT_FAST8_MAX - 1)
#undef UINT_FAST8_MAX
#define UINT_FAST8_MAX __UINT_FAST8_MAX__
#undef INT_FAST16_MAX
#define INT_FAST16_MAX __INT_FAST16_MAX__
#undef INT_FAST16_MIN
#define INT_FAST16_MIN (-INT_FAST16_MAX - 1)
#undef UINT_FAST16_MAX
#define UINT_FAST16_MAX __UINT_FAST16_MAX__
#undef INT_FAST32_MAX
#define INT_FAST32_MAX __INT_FAST32_MAX__
#undef INT_FAST32_MIN
#define INT_FAST32_MIN (-INT_FAST32_MAX - 1)
#undef UINT_FAST32_MAX
#define UINT_FAST32_MAX __UINT_FAST32_MAX__
#undef INT_FAST64_MAX
#define INT_FAST64_MAX __INT_FAST64_MAX__
#undef INT_FAST64_MIN
#define INT_FAST64_MIN (-INT_FAST64_MAX - 1)
#undef UINT_FAST64_MAX
#define UINT_FAST64_MAX __UINT_FAST64_MAX__
#ifdef __INTPTR_MAX__
# undef INTPTR_MAX
# define INTPTR_MAX __INTPTR_MAX__
# undef INTPTR_MIN
# define INTPTR_MIN (-INTPTR_MAX - 1)
#endif
#ifdef __UINTPTR_MAX__
# undef UINTPTR_MAX
# define UINTPTR_MAX __UINTPTR_MAX__
#endif
#undef INTMAX_MAX
#define INTMAX_MAX __INTMAX_MAX__
#undef INTMAX_MIN
#define INTMAX_MIN (-INTMAX_MAX - 1)
#undef UINTMAX_MAX
#define UINTMAX_MAX __UINTMAX_MAX__
/* 7.18.3 Limits of other integer types */
#undef PTRDIFF_MAX
#define PTRDIFF_MAX __PTRDIFF_MAX__
#undef PTRDIFF_MIN
#define PTRDIFF_MIN (-PTRDIFF_MAX - 1)
#undef SIG_ATOMIC_MAX
#define SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__
#undef SIG_ATOMIC_MIN
#define SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__
#undef SIZE_MAX
#define SIZE_MAX __SIZE_MAX__
#undef WCHAR_MAX
#define WCHAR_MAX __WCHAR_MAX__
#undef WCHAR_MIN
#define WCHAR_MIN __WCHAR_MIN__
#undef WINT_MAX
#define WINT_MAX __WINT_MAX__
#undef WINT_MIN
#define WINT_MIN __WINT_MIN__
#endif /* (!defined __cplusplus || __cplusplus >= 201103L
|| defined __STDC_LIMIT_MACROS) */
#if (!defined __cplusplus || __cplusplus >= 201103L \
|| defined __STDC_CONSTANT_MACROS)
#undef INT8_C
#define INT8_C(c) __INT8_C(c)
#undef INT16_C
#define INT16_C(c) __INT16_C(c)
#undef INT32_C
#define INT32_C(c) __INT32_C(c)
#undef INT64_C
#define INT64_C(c) __INT64_C(c)
#undef UINT8_C
#define UINT8_C(c) __UINT8_C(c)
#undef UINT16_C
#define UINT16_C(c) __UINT16_C(c)
#undef UINT32_C
#define UINT32_C(c) __UINT32_C(c)
#undef UINT64_C
#define UINT64_C(c) __UINT64_C(c)
#undef INTMAX_C
#define INTMAX_C(c) __INTMAX_C(c)
#undef UINTMAX_C
#define UINTMAX_C(c) __UINTMAX_C(c)
#endif /* (!defined __cplusplus || __cplusplus >= 201103L
|| defined __STDC_CONSTANT_MACROS) */
#ifndef __INT_MAX__
#define __INT_MAX__ 2147483647
@ -45,6 +255,4 @@ typedef unsigned long uintptr_t;
#define LONG_MIN (-LONG_MAX - 1)
#define ULONG_MAX (~0UL)
#define SIZE_MAX ULONG_MAX
#endif