Merge pull request #5037 from Rbb666/master
添加ART-PI在rtthread主分支的bsp模板。
This commit is contained in:
guo
GitHub
commit
45440d2456
@ -28,3 +28,12 @@ int main(void)
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rt_thread_mdelay(500);
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rt_thread_mdelay(500);
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}
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}
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}
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}
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#include "stm32h7xx.h"
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static int vtor_config(void)
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{
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/* Vector Table Relocation in Internal QSPI_FLASH */
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SCB->VTOR = QSPI_BASE;
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return 0;
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}
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INIT_BOARD_EXPORT(vtor_config);
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@ -9,12 +9,12 @@ config SOC_STM32H750XB
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menu "Onboard Peripheral Drivers"
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menu "Onboard Peripheral Drivers"
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config BSP_USING_QSPI_FLASH
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config BSP_USING_USB_TO_USART
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bool "Enable QSPI FLASH (W25Q64)"
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bool "Enable Debuger USART (uart4)"
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select BSP_USING_QSPI
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select BSP_USING_UART
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select RT_USING_SFUD
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select BSP_USING_UART4
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select RT_SFUD_USING_QSPI
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default n
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default n
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endmenu
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endmenu
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menu "On-chip Peripheral Drivers"
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menu "On-chip Peripheral Drivers"
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@ -26,27 +26,96 @@ menu "On-chip Peripheral Drivers"
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menuconfig BSP_USING_UART
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menuconfig BSP_USING_UART
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bool "Enable UART"
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bool "Enable UART"
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default y
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default n
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select RT_USING_SERIAL
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select RT_USING_SERIAL
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select RT_SERIAL_USING_DMA
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if BSP_USING_UART
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if BSP_USING_UART
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config BSP_USING_UART1
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bool "Enable UART1"
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default n
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config BSP_UART1_RX_USING_DMA
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bool "Enable UART1 RX DMA"
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depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
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default n
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config BSP_UART1_TX_USING_DMA
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bool "Enable UART1 TX DMA"
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depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
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default n
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config BSP_USING_UART3
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config BSP_USING_UART3
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bool "Enable UART3"
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bool "Enable UART3"
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default y
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default n
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config BSP_USING_UART4
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config BSP_USING_UART4
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bool "Enable UART4"
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bool "Enable UART4"
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default y
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default n
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config BSP_USING_UART6
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bool "Enable UART6"
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default n
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endif
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endif
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config BSP_USING_ONCHIP_RTC
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bool "Enable Onchip RTC"
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config BSP_USING_SDIO
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select RT_USING_RTC
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bool "Enable SDIO"
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select RT_USING_SDIO
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select RT_USING_DFS
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default n
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default n
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menuconfig BSP_USING_I2C
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bool "Enable I2C BUS (software simulation)"
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select RT_USING_I2C
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select RT_USING_I2C_BITOPS
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select RT_USING_PIN
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default n
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if BSP_USING_I2C
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menuconfig BSP_USING_I2C1
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bool "Enable I2C1 BUS (software simulation)"
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default n
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select RT_USING_I2C
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select RT_USING_I2C_BITOPS
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select RT_USING_PIN
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if BSP_USING_I2C1
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comment "Notice: PB6 --> 22; PB7 --> 23"
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config BSP_I2C1_SCL_PIN
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int "I2C1 scl pin number"
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range 0 175
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default 22
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config BSP_I2C1_SDA_PIN
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int "I2C1 sda pin number"
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range 0 175
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default 23
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endif
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menuconfig BSP_USING_I2C2
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bool "Enable I2C2 BUS (software simulation)"
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default n
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if BSP_USING_I2C2
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comment "Notice: PH13 --> 125; PH15 --> 127"
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config BSP_I2C2_SCL_PIN
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int "i2c2 scl pin number"
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range 1 176
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default 127
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config BSP_I2C2_SDA_PIN
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int "I2C2 sda pin number"
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range 0 175
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default 125
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endif
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menuconfig BSP_USING_I2C3
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bool "Enable I2C3 BUS (software simulation)"
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default n
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if BSP_USING_I2C3
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comment "Notice: PH12 --> 124; PH11 --> 123"
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config BSP_I2C3_SCL_PIN
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int "i2c3 scl pin number"
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range 0 175
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default 123
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config BSP_I2C3_SDA_PIN
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int "I2C3 sda pin number"
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range 0 175
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default 124
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endif
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endif
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source "../libraries/HAL_Drivers/Kconfig"
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source "../libraries/HAL_Drivers/Kconfig"
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endmenu
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endmenu
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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@ -16,59 +16,95 @@
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*/
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*/
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void SystemClock_Config(void)
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void SystemClock_Config(void)
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{
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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/** Supply configuration update enable
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/** Supply configuration update enable
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*/
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*/
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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/** Configure the main internal regulator output voltage
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/** Configure the main internal regulator output voltage
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*/
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 5;
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RCC_OscInitStruct.PLL.PLLN = 192;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
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|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
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/** Initializes the RCC Oscillators according to the specified parameters
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{
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* in the RCC_OscInitTypeDef structure.
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Error_Handler();
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*/
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}
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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{
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RCC_OscInitStruct.PLL.PLLM = 5;
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Error_Handler();
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RCC_OscInitStruct.PLL.PLLN = 192;
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}
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
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| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_USART3
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| RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_SPI4
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| RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SDMMC
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| RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB
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| RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_FMC;
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PeriphClkInitStruct.PLL2.PLL2M = 2;
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PeriphClkInitStruct.PLL2.PLL2N = 64;
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PeriphClkInitStruct.PLL2.PLL2P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 2;
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PeriphClkInitStruct.PLL2.PLL2R = 4;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
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PeriphClkInitStruct.PLL3.PLL3M = 5;
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PeriphClkInitStruct.PLL3.PLL3N = 160;
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PeriphClkInitStruct.PLL3.PLL3P = 8;
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PeriphClkInitStruct.PLL3.PLL3Q = 8;
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PeriphClkInitStruct.PLL3.PLL3R = 24;
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PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2;
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PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
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PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
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PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
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PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
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PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2;
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PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL3;
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PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Enable USB Voltage detector
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*/
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HAL_PWREx_EnableUSBVoltageDetector();
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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@ -20,12 +20,62 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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/*-------------------------- CHIP CONFIG BEGIN --------------------------*/
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#define STM32_FLASH_SIZE (128 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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#define STM32_SRAM_SIZE (128)
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#define CHIP_FAMILY_STM32
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define CHIP_SERIES_STM32H7
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#define CHIP_NAME_STM32H750XBHX
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/*-------------------------- CHIP CONFIG END --------------------------*/
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/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/
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#define ROM_START ((uint32_t)0x90000000)
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#define ROM_SIZE (16384)
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#define ROM_END ((uint32_t)(ROM_START + ROM_SIZE * 1024))
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#define RAM_START (0x24000000)
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#define RAM_SIZE (512)
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#define RAM_END (RAM_START + RAM_SIZE * 1024)
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/*-------------------------- ROM/RAM CONFIG END --------------------------*/
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/*-------------------------- CLOCK CONFIG BEGIN --------------------------*/
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#define BSP_CLOCK_SOURCE ("HSE")
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#define BSP_CLOCK_SOURCE_FREQ_MHZ ((int32_t)0)
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#define BSP_CLOCK_SYSTEM_FREQ_MHZ ((int32_t)480)
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/*-------------------------- CLOCK CONFIG END --------------------------*/
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/*-------------------------- UART CONFIG BEGIN --------------------------*/
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/** After configuring corresponding UART or UART DMA, you can use it.
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*
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* STEP 1, define macro define related to the serial port opening based on the serial port number
|
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* such as #define BSP_USING_UATR1
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*
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* STEP 2, according to the corresponding pin of serial port, define the related serial port information macro
|
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* such as #define BSP_UART1_TX_PIN "PA9"
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* #define BSP_UART1_RX_PIN "PA10"
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*
|
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* STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
|
||||||
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* RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
|
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*
|
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* STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
|
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* such as #define BSP_UART1_RX_USING_DMA
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*
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*/
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||||||
|
#define STM32_FLASH_START_ADRESS ROM_START
|
||||||
|
#define STM32_FLASH_SIZE ROM_SIZE
|
||||||
|
#define STM32_FLASH_END_ADDRESS ROM_END
|
||||||
|
|
||||||
|
#define RAM_START (0x24000000)
|
||||||
|
#define RAM_SIZE (512)
|
||||||
|
#define RAM_END (RAM_START + RAM_SIZE * 1024)
|
||||||
|
|
||||||
|
#define STM32_SRAM1_SIZE RAM_SIZE
|
||||||
|
#define STM32_SRAM1_START RAM_START
|
||||||
|
#define STM32_SRAM1_END RAM_END
|
||||||
|
|
||||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
@ -38,7 +88,7 @@ extern int __bss_end;
|
|||||||
#define HEAP_BEGIN (&__bss_end)
|
#define HEAP_BEGIN (&__bss_end)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define HEAP_END STM32_SRAM_END
|
#define HEAP_END STM32_SRAM1_END
|
||||||
|
|
||||||
void SystemClock_Config(void);
|
void SystemClock_Config(void);
|
||||||
|
|
||||||
|
|||||||
@ -2,18 +2,16 @@
|
|||||||
; *** Scatter-Loading Description File generated by uVision ***
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
; *************************************************************
|
; *************************************************************
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00020000 { ; load region size_region
|
LR_IROM1 0x90000000 0x00800000 { ; load region size_region
|
||||||
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
|
ER_IROM1 0x90000000 0x00800000 { ; load address = execution address
|
||||||
*.o (RESET, +First)
|
*.o (RESET, +First)
|
||||||
*(InRoot$$Sections)
|
*(InRoot$$Sections)
|
||||||
.ANY (+RO)
|
.ANY (+RO)
|
||||||
.ANY (+XO)
|
.ANY (+XO)
|
||||||
}
|
}
|
||||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
RW_IRAM1 0x24000000 0x00080000 { ; AXI SRAM 512K
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
RW_IRAM2 0x24000000 0x00080000 {
|
|
||||||
.ANY (+RW +ZI)
|
.ANY (+RW +ZI)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user