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[bsp/renesas/ebf_qi_min_6m5]use fsp v4.4.0, add sci spi config item, add sci i2c driver, update README.

This commit is contained in:
vandoul 2023-06-04 13:00:38 +08:00 committed by Man, Jianting (Meco)
parent 4003172797
commit 446fdf1329
76 changed files with 41296 additions and 48899 deletions
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34
bsp/renesas/ebf_qi_min_6m5/.settings/standalone.prefs
View File

@ -1,19 +1,21 @@
#Sun Nov 13 22:01:41 CST 2022
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5BH3CFC\#\#3.5.0/libraries=
#Sun Jun 04 12:44:50 CST 2023
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|2208590403,ra/fsp/inc/instances/r_ioport.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2425160085,ra/fsp/inc/api/bsp_api.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|1728953905,ra/fsp/inc/fsp_features.h|3297195641,ra/fsp/inc/fsp_version.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|546480625,ra/fsp/inc/fsp_common_api.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#4.4.0/all=1446732504,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5BH3CFC\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.4.0/all=1835725510,ra/fsp/src/bsp/mcu/all/bsp_io.c|2359800297,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1399471156,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1915400095,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|668319255,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1060094479,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2399628405,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|27008654,ra/fsp/src/bsp/mcu/all/bsp_io.h|2365965045,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|271204625,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1664932476,ra/fsp/inc/fsp_version.h|1884526901,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3610800851,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3793821860,ra/fsp/inc/instances/r_ioport.h|270868601,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2678185049,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2970131887,ra/fsp/src/bsp/mcu/all/bsp_security.c|552454302,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1610748464,ra/fsp/inc/fsp_features.h|543620856,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2942601344,ra/fsp/inc/fsp_common_api.h|3376402702,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1707338993,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2618298326,ra/fsp/inc/api/r_ioport_api.h|3085135894,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1246740431,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1668386995,ra/fsp/src/bsp/mcu/all/bsp_security.h|1509328298,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2932063803,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3032783805,ra/fsp/src/bsp/mcu/all/bsp_common.h|1128795121,ra/fsp/inc/api/bsp_api.h|1220888647,ra/fsp/src/bsp/mcu/all/bsp_common.c|871460117,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4290340792,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3375746094,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=DeviceAndToolSelection
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#4.4.0/all=3548214691,ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h|1616333260,ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h|4125051366,ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.582032887=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#3.5.0/all=3982164632,ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h|1585467956,ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h|4282536086,ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.4.0/all=3793821860,ra/fsp/inc/instances/r_ioport.h|2618298326,ra/fsp/inc/api/r_ioport_api.h|2879227488,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.4.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5BH3CFC\#\#4.4.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#4.4.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.4.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.4.0/all=620459583,ra/fsp/src/r_sci_uart/r_sci_uart.c|1201226050,ra/fsp/inc/instances/r_sci_uart.h|1461745579,ra/fsp/inc/api/r_uart_api.h|1910009580,ra/fsp/inc/api/r_transfer_api.h

10
bsp/renesas/ebf_qi_min_6m5/README.md
View File

@ -29,14 +29,15 @@
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------------- | :------------- |
|:-------- |:-------- |:--------------- |
| UART | 支持 | UART4 为默认日志输出端口 |
| GPIO | 支持 | |
| I2C | 支持 | |
| SPI | 支持 | |
| 持续更新中... | | |
| **外接外设** | **支持情况** | **备注** |
| 持续更新中... | | |
## 使用说明
使用说明分为如下两个章节：
@ -44,6 +45,7 @@
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
@ -129,7 +131,7 @@ void hal_entry(void)
需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 3.5.0 版本
1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 4.4.0 版本
2. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
**ENV 配置**
@ -139,12 +141,12 @@ void hal_entry(void)
此 BSP 默认只开启了 UART4 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)

105
bsp/renesas/ebf_qi_min_6m5/board/Kconfig
View File

@ -50,6 +50,111 @@ menu "Hardware Drivers Config"
endif
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
menuconfig BSP_USING_SCI_I2C
bool "Enable SCI I2C BUS"
default n
if BSP_USING_SCI_I2C
config BSP_USING_SCI_I2C0
bool "Enable SCI I2C0 BUS"
default n
config BSP_USING_SCI_I2C1
bool "Enable SCI I2C1 BUS"
default n
config BSP_USING_SCI_I2C2
bool "Enable SCI I2C2 BUS"
default n
config BSP_USING_SCI_I2C3
bool "Enable SCI I2C3 BUS"
default n
config BSP_USING_SCI_I2C4
bool "Enable SCI I2C4 BUS"
default n
config BSP_USING_SCI_I2C5
bool "Enable SCI I2C5 BUS"
default n
config BSP_USING_SCI_I2C6
bool "Enable SCI I2C6 BUS"
default n
config BSP_USING_SCI_I2C7
bool "Enable SCI I2C7 BUS"
default n
config BSP_USING_SCI_I2C8
bool "Enable SCI I2C8 BUS"
default n
config BSP_USING_SCI_I2C9
bool "Enable SCI I2C9 BUS"
default n
endif
config BSP_USING_HW_I2C
bool "Enable Hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
if !BSP_USING_HW_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number"
range 0x0000 0x0B0F
default 0x050C
config BSP_I2C1_SDA_PIN
hex "I2C1 sda pin number"
range 0x0000 0x0B0F
default 0x050B
endif
endif
endif
menuconfig BSP_USING_SCI_SPI
bool "Enable SCI SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SCI_SPI
config BSP_USING_SCI_SPI0
bool "Enable SCI SPI0 BUS"
default n
config BSP_USING_SCI_SPI1
bool "Enable SCI SPI1 BUS"
default n
config BSP_USING_SCI_SPI2
bool "Enable SCI SPI2 BUS"
default n
config BSP_USING_SCI_SPI3
bool "Enable SCI SPI3 BUS"
default n
config BSP_USING_SCI_SPI5
bool "Enable SCI SPI5 BUS"
default n
config BSP_USING_SCI_SPI6
bool "Enable SCI SPI6 BUS"
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
endif
endmenu
menu "Board extended module Drivers"

5
bsp/renesas/ebf_qi_min_6m5/board/SConscript
View File

@ -9,4 +9,9 @@ for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
CPPPATH = [cwd]
LOCAL_CFLAGS = ''
objs = objs + DefineGroup('Drivers', [], depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
Return('objs')

5
bsp/renesas/ebf_qi_min_6m5/buildinfo.gpdsc
View File

@ -43,10 +43,13 @@
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
@ -59,7 +62,7 @@
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>

81
bsp/renesas/ebf_qi_min_6m5/configuration.xml
View File

@ -3,12 +3,13 @@
<generalSettings>
<option key="#Board#" value="board.custom"/>
<option key="CPU" value="RA6M5"/>
<option key="Core" value="CM33"/>
<option key="#TargetName#" value="R7FA6M5BH3CFC"/>
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
<option key="#DeviceCommand#" value="R7FA6M5BH"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/>
<option key="#FSPVersion#" value="3.5.0"/>
<option key="#FSPVersion#" value="4.4.0"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration>
@ -20,6 +21,7 @@
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
<property id="config.bsp.irq_count_hidden" value="96"/>
</config>
<config id="config.bsp.ra6m5">
<property id="config.bsp.series" value="config.bsp.series.value"/>
@ -37,6 +39,7 @@
<property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
<property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
<property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
@ -70,13 +73,18 @@
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
<property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
<property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
<property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="8"/>
<property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules" value="128"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules_independent" value="0"/>
<property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="8"/>
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x03F9"/>
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
<property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/>
</config>
<config id="config.bsp.ra">
<property id="config.bsp.common.main" value="0x400"/>
@ -113,8 +121,10 @@
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/>
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
@ -125,8 +135,10 @@
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.1"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.6"/>
<node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
@ -137,41 +149,43 @@
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="3.5.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="3.5.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.8.0+renesas.0.fsp.3.5.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="3.5.0">
<description>Board support package for R7FA6M5BH3CFC</description>
<originalPack>Renesas.RA_mcu_ra6m5.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="3.5.0">
<description>Board support package for RA6M5</description>
<originalPack>Renesas.RA_mcu_ra6m5.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="3.5.0">
<description>Board support package for RA6M5 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra6m5.3.5.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="3.5.0">
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="4.4.0">
<description>Custom Board Support Files</description>
<originalPack>Renesas.RA_board_custom.3.5.0.pack</originalPack>
<originalPack>Renesas.RA_board_custom.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="3.5.0">
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="4.4.0">
<description>Board support package for R7FA6M5BH3CFC</description>
<originalPack>Renesas.RA_mcu_ra6m5.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="4.4.0">
<description>Board support package for RA6M5</description>
<originalPack>Renesas.RA_mcu_ra6m5.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="4.4.0">
<description>Board support package for RA6M5 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra6m5.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.9.0+renesas.0.fsp.4.4.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.9.0+renesas.0.fsp.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="4.4.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="4.4.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.4.4.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="4.4.0">
<description>SCI UART</description>
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
<originalPack>Renesas.RA.4.4.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
@ -183,10 +197,6 @@
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioportb" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioportc" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioportd" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioporte" value="_disabled"/>
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
</module>
<module id="module.driver.uart_on_sci_uart.582032887">
@ -205,6 +215,10 @@
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
<property id="module.driver.uart.rs485.de_enable" value="module.driver.uart.rs485.de_enable.disabled"/>
<property id="module.driver.uart.rs485.de_polarity" value="module.driver.uart.rs485.de_polarity.high"/>
<property id="module.driver.uart.rs485.de_port_number" value="module.driver.uart.rs485.de_port_number.PORT_DISABLE"/>
<property id="module.driver.uart.rs485.de_pin_number" value="module.driver.uart.rs485.de_pin_number.PIN_DISABLE"/>
<property id="module.driver.uart.callback" value="user_uart4_callback"/>
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
@ -223,6 +237,7 @@
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
<property id="config.driver.sci_uart.rs485" value="config.driver.sci_uart.rs485.disabled"/>
</config>
</raModuleConfiguration>
<raPinConfiguration>

2
bsp/renesas/ebf_qi_min_6m5/script/memory_regions.scat → bsp/renesas/ebf_qi_min_6m5/memory_regions.scat
View File

@ -12,7 +12,7 @@
#define OPTION_SETTING_S_LENGTH 0x100
#define ID_CODE_START 0x00000000
#define ID_CODE_LENGTH 0x0
#define SDRAM_START 0x90000000
#define SDRAM_START 0x80010000
#define SDRAM_LENGTH 0x0
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x4000000

2
bsp/renesas/ebf_qi_min_6m5/project.uvprojx
View File

@ -335,7 +335,7 @@
<MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal</MiscControls>
<Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Undefine />
<IncludePath>..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;.</IncludePath>
<IncludePath>..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;.</IncludePath>
</VariousControls>
</Cads>
<Aads>

8
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h
View File

@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
* @version V5.0.5
* @date 02. February 2022
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@ -33,7 +33,7 @@
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

29
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv81mml.h
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
* @version V1.4.1
* @date 04. June 2021
* @version V1.4.2
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@ -526,7 +526,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@ -535,7 +535,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
@ -1490,15 +1493,14 @@ typedef struct
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
uint32_t RESERVED12[4];
uint32_t RESERVED12[3];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
__IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
uint32_t RESERVED14[3];
__IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
@ -3158,6 +3160,15 @@ typedef struct
/*@} */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer

20
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
* @version V5.2.2
* @date 04. June 2021
* @version V5.2.3
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@ -2182,6 +2185,15 @@ typedef struct
/*@} */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer

20
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
* @version V5.2.2
* @date 04. June 2021
* @version V5.2.3
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@ -2257,6 +2260,15 @@ typedef struct
/*@} */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer

20
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm35p.h
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
* @version V1.1.2
* @date 04. June 2021
* @version V1.1.3
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@ -2257,6 +2260,15 @@ typedef struct
/*@} */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer

603
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h
View File

@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm55.h
* @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
* @version V1.2.1
* @date 04. June 2021
* @version V1.2.4
* @date 21. April 2022
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
* Copyright (c) 2018-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@ -58,7 +58,7 @@
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_CM55
\ingroup Cortex_M55
@{
*/
@ -303,9 +303,11 @@
Core Register contain:
- Core Register
- Core NVIC Register
- Core EWIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core PMU Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
@ -526,7 +528,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@ -535,7 +537,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
@ -987,13 +992,13 @@ typedef struct
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
\defgroup CMSIS_ICB Implementation Control Block register (ICB)
\brief Type definitions for the Implementation Control Block Register
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
\brief Structure type to access the Implementation Control Block (ICB).
*/
typedef struct
{
@ -1001,13 +1006,56 @@ typedef struct
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
} SCnSCB_Type;
} ICB_Type;
/* Auxiliary Control Register Definitions */
#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */
#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */
#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */
#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */
#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */
#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */
#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */
#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */
#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */
#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */
#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */
#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */
#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */
#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */
#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */
#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */
#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */
#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */
#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
/*@} end of group CMSIS_ICB */
/**
@ -1349,6 +1397,133 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED)
\brief Type definitions for the Memory System Control Registers (MEMSYSCTL)
@{
*/
/**
\brief Structure type to access the Memory System Control Registers (MEMSYSCTL).
*/
typedef struct
{
__IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */
__IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */
uint32_t RESERVED1[2U];
__IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */
__IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */
__IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */
uint32_t RESERVED2[313U];
__IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */
__IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */
uint32_t RESERVED3[2U];
__IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */
uint32_t RESERVED4[44U];
__IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */
__IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */
uint32_t RESERVED5[2U];
__IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */
} MemSysCtl_Type;
/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */
#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */
#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */
#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */
#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */
#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */
#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */
#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */
#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */
#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */
#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */
#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */
#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */
#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */
#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */
/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */
#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */
#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */
#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */
#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */
#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */
#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */
#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */
#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */
/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */
#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */
#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */
#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */
#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */
/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */
#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */
#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */
#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */
#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */
/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */
#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */
#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */
#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */
#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */
/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */
/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */
/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */
/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */
/*@}*/ /* end of group MemSysCtl_Type */
/**
\ingroup CMSIS_core_register
\defgroup PwrModCtl_Type Power Mode Control Registers
@ -1361,26 +1536,315 @@ typedef struct
*/
typedef struct
{
__IOM uint32_t CPDLPSTATE;
__IOM uint32_t DPDLPSTATE;
__IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */
__IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */
} PwrModCtl_Type;
/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE CLPSTATE Position */
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE CLPSTATE Mask */
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE ELPSTATE Position */
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE ELPSTATE Mask */
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE RLPSTATE Position */
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk 3UL /*!< PWRMODCTL CPDLPSTATE RLPSTATE Mask */
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */
/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE DLPSTATE Position */
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk 3UL /*!< PWRMODCTL DPDLPSTATE DLPSTATE Mask */
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */
/*@}*/ /* end of group CMSIS_PWRMODCTL */
/*@}*/ /* end of group PwrModCtl_Type */
/**
\ingroup CMSIS_core_register
\defgroup EWIC_Type External Wakeup Interrupt Controller Registers
\brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
@{
*/
/**
\brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
*/
typedef struct
{
__OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */
uint32_t RESERVED0[31U];
__IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */
__IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */
} EWIC_Type;
/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */
#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */
#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */
#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */
#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */
#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */
#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */
/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */
#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */
#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */
#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */
#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */
#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */
#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */
/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */
#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */
#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */
/*@}*/ /* end of group EWIC_Type */
/**
\ingroup CMSIS_core_register
\defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED)
\brief Type definitions for the Error Banking Registers (ERRBNK)
@{
*/
/**
\brief Structure type to access the Error Banking Registers (ERRBNK).
*/
typedef struct
{
__IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */
__IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */
uint32_t RESERVED0[2U];
__IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */
__IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */
uint32_t RESERVED1[2U];
__IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */
} ErrBnk_Type;
/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */
#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */
#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */
#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */
#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */
#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */
#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */
#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */
#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */
#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */
#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */
/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */
#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */
#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */
#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */
#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */
#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */
#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */
#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */
#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */
#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */
#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */
/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */
#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */
#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */
#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */
#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */
#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */
#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */
#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */
#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */
#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */
#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */
#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */
#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */
/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */
#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */
#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */
#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */
#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */
#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */
#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */
#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */
#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */
#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */
#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */
#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */
#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */
/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */
#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */
#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */
#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */
#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */
#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */
#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */
#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */
#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */
#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */
#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */
#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */
#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */
#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */
#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */
/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */
#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */
#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */
#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */
#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */
#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */
#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */
#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */
#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */
#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */
#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */
#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */
#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */
#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */
#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */
/*@}*/ /* end of group ErrBnk_Type */
/**
\ingroup CMSIS_core_register
\defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED)
\brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
@{
*/
/**
\brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).
*/
typedef struct
{
__OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */
__IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */
} PrcCfgInf_Type;
/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */
/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */
/*@}*/ /* end of group PrcCfgInf_Type */
/**
\ingroup CMSIS_core_register
\defgroup STL_Type Software Test Library Observation Registers
\brief Type definitions for the Software Test Library Observation Registerss (STL)
@{
*/
/**
\brief Structure type to access the Software Test Library Observation Registerss (STL).
*/
typedef struct
{
__IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */
__IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */
uint32_t RESERVED0[2U];
__OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */
__IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */
__IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */
__IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */
} STL_Type;
/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */
#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */
#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */
#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */
#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */
#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */
#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */
#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */
#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */
/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */
#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */
#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */
#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */
#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */
#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */
#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */
#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */
#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */
/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */
#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */
#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */
#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */
#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */
#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */
#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */
/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */
#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */
#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */
#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */
#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */
/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */
#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */
#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */
#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */
#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */
/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */
#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */
#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */
#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */
#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */
/*@}*/ /* end of group STL_Type */
/**
@ -1524,15 +1988,14 @@ typedef struct
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
uint32_t RESERVED12[4];
uint32_t RESERVED12[3];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
__IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
uint32_t RESERVED14[3];
__IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
@ -3127,7 +3590,12 @@ typedef struct
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */
#define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */
#define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */
#define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */
#define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */
#define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
@ -3136,14 +3604,19 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */
#define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */
#define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */
#define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */
#define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */
#define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
@ -3175,7 +3648,7 @@ typedef struct
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
@ -3195,6 +3668,69 @@ typedef struct
/*@} */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/* 'SCnSCB' is deprecated and replaced by 'ICB' */
typedef ICB_Type SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos)
#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk)
#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos)
#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk)
#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos)
#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk)
#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos)
#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk)
#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos)
#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk)
#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos)
#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk)
#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos)
#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk)
#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos)
#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk)
#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos)
#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk)
#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos)
#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk)
#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos)
#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk)
#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos)
#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk)
#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos)
#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk)
#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos)
#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk)
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos)
#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk)
#define SCnSCB (ICB)
#define SCnSCB_NS (ICB_NS)
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
@ -3888,6 +4424,9 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */
#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */
#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */
#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */

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206
bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h Normal file
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@ -0,0 +1,206 @@
/******************************************************************************
* @file pac_armv81.h
* @brief CMSIS PAC key functions for Armv8.1-M PAC extension
* @version V1.0.0
* @date 23. March 2022
******************************************************************************/
/*
* Copyright (c) 2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef PAC_ARMV81_H
#define PAC_ARMV81_H
/* ################### PAC Key functions ########################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
\brief Functions that access the PAC keys.
@{
*/
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
/**
\brief read the PAC key used for privileged mode
\details Reads the PAC key stored in the PAC_KEY_P registers.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_p_0\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_p_1\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_p_2\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_p_3\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for privileged mode
\details writes the given PAC key to the PAC_KEY_P registers.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_p_0, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_p_1, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_p_2, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_p_3, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief read the PAC key used for unprivileged mode
\details Reads the PAC key stored in the PAC_KEY_U registers.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_u_0\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_u_1\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_u_2\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_u_3\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for unprivileged mode
\details writes the given PAC key to the PAC_KEY_U registers.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_u_0, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_u_1, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_u_2, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_u_3, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief read the PAC key used for privileged mode (non-secure)
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_p_0_ns\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_p_1_ns\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_p_2_ns\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_p_3_ns\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for privileged mode (non-secure)
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_p_0_ns, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_p_1_ns, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_p_2_ns, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_p_3_ns, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief read the PAC key used for unprivileged mode (non-secure)
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_u_0_ns\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_u_1_ns\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_u_2_ns\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_u_3_ns\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for unprivileged mode (non-secure)
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_u_0_ns, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_u_1_ns, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_u_2_ns, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_u_3_ns, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
/*@} end of CMSIS_Core_PacKeyFunctions */
#endif /* PAC_ARMV81_H */

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/bsp_api.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

45
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_ioport_api.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -16,8 +16,7 @@
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
@ -70,6 +69,12 @@ typedef enum e_ioport_peripheral
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
@ -119,6 +124,9 @@ typedef enum e_ioport_peripheral
/** Pin will function as an SCI DEn peripheral pin */
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CEU peripheral pin */
IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAN peripheral pin */
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
@ -175,24 +183,14 @@ typedef enum e_ioport_peripheral
/** Pin will function as a PGAOUT peripheral pin */
IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a MIPI peripheral pin */
IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a ULPT peripheral pin */
IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
} ioport_peripheral_t;
/* DEPRECATED Superset of Ethernet channels. */
typedef enum e_ioport_eth_ch
{
IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1
IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
} ioport_ethernet_channel_t;
/* DEPRECATED Superset of Ethernet PHY modes. */
typedef enum e_ioport_eth_mode
{
IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII
IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking
} ioport_ethernet_mode_t;
/** Options to configure pin functions */
typedef enum e_ioport_cfg_options
{
@ -294,15 +292,6 @@ typedef struct st_ioport_api
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
/* DEPRECATED Configure the PHY mode of the Ethernet channels.
* @par Implemented as
* - @ref R_IOPORT_EthernetModeCfg()
* @param[in] channel Channel configuration will be set for.
* @param[in] mode PHY mode to set the channel to.
*/
fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
ioport_ethernet_mode_t mode);
/** Read level of a pin.
* @par Implemented as
* - @ref R_IOPORT_PinRead()

5
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_transfer_api.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -213,7 +213,8 @@ typedef struct st_transfer_info
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
};
} transfer_settings_word_b;
uint32_t transfer_settings_word;
};

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/api/r_uart_api.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

30
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_common_api.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -57,8 +57,11 @@
#endif
/** FSP Header and Footer definitions */
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
@ -153,6 +156,9 @@ typedef enum e_fsp_err
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
/* Start of IIRFA Specific */
FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity.
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
@ -187,6 +193,10 @@ typedef enum e_fsp_err
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
/* Start of IIRFA specific */
FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected
FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
@ -287,6 +297,17 @@ typedef enum e_fsp_err
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
@ -361,4 +382,7 @@ typedef enum e_fsp_err
* Function prototypes
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

12
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_features.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -44,6 +44,9 @@
* @{
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
@ -118,6 +121,7 @@ typedef enum e_fsp_ip
FSP_IP_TFU = 74, ///< Trigonometric Function Unit
FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
FSP_IP_CANFD = 76, ///< CAN-FD
FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
@ -285,10 +289,16 @@ typedef enum e_fsp_signal
FSP_SIGNAL_USB_RESUME, ///< USB RESUME
FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A
FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B
FSP_SIGNAL_ULPT_INT, ///< ULPT INT
} fsp_signal_t;
typedef void (* fsp_vector_t)(void);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

34
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/fsp_version.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -19,41 +19,45 @@
**********************************************************************************************************************/
#ifndef FSP_VERSION_H
#define FSP_VERSION_H
#define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
#define FSP_VERSION_MAJOR (3U)
#define FSP_VERSION_MAJOR (4U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (5U)
#define FSP_VERSION_MINOR (4U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
#define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("3.5.0")
#define FSP_VERSION_STRING ("4.4.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.5.0")
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.4.0")
/**********************************************************************************************************************
* Typedef definitions
@ -65,16 +69,22 @@ typedef union st_fsp_pack_version
/** Version id */
uint32_t version_id;
/** Code version parameters, little endian order. */
struct
/**
* Code version parameters, little endian order.
*/
struct version_id_b_s
{
uint8_t build; ///< Build version of FSP Pack
uint8_t patch; ///< Patch version of FSP Pack
uint8_t minor; ///< Minor version of FSP Pack
uint8_t major; ///< Major version of FSP Pack
};
} version_id_b;
} fsp_pack_version_t;
/** @} */
#ifdef __cplusplus
}
#endif
#endif

5
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_ioport.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -345,9 +345,6 @@ fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl,
ioport_ethernet_channel_t channel,
ioport_ethernet_mode_t mode);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)

33
bsp/renesas/ebf_qi_min_6m5/ra/fsp/inc/instances/r_sci_uart.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -107,11 +107,11 @@ typedef enum e_sci_uart_rx_fifo_trigger
} sci_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
typedef enum e_sci_uart_start_bit_detect
typedef enum e_sci_uart_start_bit_t
{
SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
} sci_uart_start_bit_detect_t;
} sci_uart_start_bit_t;
/** Noise cancellation configuration. */
typedef enum e_sci_uart_noise_cancellation
@ -120,6 +120,20 @@ typedef enum e_sci_uart_noise_cancellation
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation
} sci_uart_noise_cancellation_t;
/** RS-485 Enable/Disable. */
typedef enum e_sci_uart_rs485_enable
{
SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled.
SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled.
} sci_uart_rs485_enable_t;
/** The polarity of the RS-485 DE signal. */
typedef enum e_sci_uart_rs485_de_polarity
{
SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress.
} sci_uart_rs485_de_polarity_t;
/** Register settings to acheive a desired baud rate and modulation duty. */
typedef struct st_baud_setting_t
{
@ -136,23 +150,32 @@ typedef struct st_baud_setting_t
uint8_t : 1;
uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
uint8_t : 1;
};
} semr_baudrate_bits_b;
};
uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
uint8_t brr; ///< Bit Rate Register setting
uint8_t mddr; ///< Modulation Duty Register setting
} baud_setting_t;
/** Configuration settings for controlling the DE signal for RS-485. */
typedef struct st_sci_uart_rs485_setting
{
sci_uart_rs485_enable_t enable; ///< Enable the DE signal.
sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin.
} sci_uart_rs485_setting_t;
/** UART on SCI device Configuration */
typedef struct st_sci_uart_extended_cfg
{
sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
sci_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge
sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge
sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used.
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin
sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings.
} sci_uart_extended_cfg_t;
/**********************************************************************************************************************

28147
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h Normal file
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623
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h
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@ -1,623 +0,0 @@
#ifndef __BASE_ADDRESSES_H
#define __BASE_ADDRESSES_H
#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers)
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
#define R_ACMPHS0_BASE 0x400F4000
#define R_ACMPHS1_BASE 0x400F4100
#define R_ACMPHS2_BASE 0x400F4200
#define R_ACMPHS3_BASE 0x400F4300
#define R_MPU_BASE 0x40000000
#define R_TZF_BASE 0x40000E00
#define R_SRAM_BASE 0x40002000
#define R_BUS_BASE 0x40003000
#define R_DMAC0_BASE 0x40005000
#define R_DMAC1_BASE 0x40005040
#define R_DMAC2_BASE 0x40005080
#define R_DMAC3_BASE 0x400050C0
#define R_DMAC4_BASE 0x40005100
#define R_DMAC5_BASE 0x40005140
#define R_DMAC6_BASE 0x40005180
#define R_DMAC7_BASE 0x400051C0
#define R_DMA_BASE 0x40005200
#define R_DTC_BASE 0x40005400
#define R_ICU_BASE 0x40006000
#define R_CACHE_BASE 0x40007000
#define R_CPSCU_BASE 0x40008000
#define R_DBG_BASE 0x4001B000
#define R_FCACHE_BASE 0x4001C000
#define R_SYSC_BASE 0x4001E000
#define R_TSN_CAL_BASE 0x407FB17C
#define R_TSN_CTRL_BASE 0x400F3000
#define R_ELC_BASE 0x40082000
#define R_TC_BASE 0x40083000
#define R_IWDT_BASE 0x40083200
#define R_WDT_BASE 0x40083400
#define R_CAC_BASE 0x40083600
#define R_MSTP_BASE 0x40084000
#define R_KINT_BASE 0x40085000
#define R_POEG_BASE 0x4008A000
#define R_USB_FS0_BASE 0x40090000
#define R_USB_HS0_BASE 0x40111000
#define R_SDHI0_BASE 0x40092000
#define R_SSI0_BASE 0x4009D000
#define R_IIC0_BASE 0x4009F000
#define R_IIC0WU_BASE 0x4009F014
#define R_IIC1_BASE 0x4009F100
#define R_OSPI_BASE 0x400A6000
#define R_CAN0_BASE 0x400A8000
#define R_CAN1_BASE 0x400A9000
#define R_CEC_BASE 0x400AC000
#define R_CANFD_BASE 0x400B0000
#define R_CTSU_BASE 0x400D0000
#define R_PSCU_BASE 0x400E0000
#define R_AGT0_BASE 0x400E8000
#define R_AGT1_BASE 0x400E8100
#define R_AGT2_BASE 0x400E8200
#define R_AGT3_BASE 0x400E8300
#define R_AGT4_BASE 0x400E8400
#define R_AGT5_BASE 0x400E8500
#define R_AGTW0_BASE 0x400E8000
#define R_AGTW1_BASE 0x400E8100
#define R_TSN_CTRL_BASE 0x400F3000
#define R_CRC_BASE 0x40108000
#define R_DOC_BASE 0x40109000
#define R_ETHERC_EDMAC_BASE 0x40114000
#define R_ETHERC0_BASE 0x40114100
#define R_SCI0_BASE 0x40118000
#define R_SCI1_BASE 0x40118100
#define R_SCI2_BASE 0x40118200
#define R_SCI3_BASE 0x40118300
#define R_SCI4_BASE 0x40118400
#define R_SCI5_BASE 0x40118500
#define R_SCI6_BASE 0x40118600
#define R_SCI7_BASE 0x40118700
#define R_SCI8_BASE 0x40118800
#define R_SCI9_BASE 0x40118900
#define R_SPI0_BASE 0x4011A000
#define R_SPI1_BASE 0x4011A100
#define R_SPI_B0_BASE 0x4011A000
#define R_SPI_B1_BASE 0x4011A100
#define R_GPT320_BASE 0x40169000
#define R_GPT321_BASE 0x40169100
#define R_GPT322_BASE 0x40169200
#define R_GPT323_BASE 0x40169300
#define R_GPT164_BASE 0x40169400
#define R_GPT165_BASE 0x40169500
#define R_GPT166_BASE 0x40169600
#define R_GPT167_BASE 0x40169700
#define R_GPT168_BASE 0x40169800
#define R_GPT169_BASE 0x40169900
#define R_GPT_OPS_BASE 0x40169A00
#define R_GPT_ODC_BASE 0x4016A000
#define R_GPT_GTCLK_BASE 0x40169B00
#define R_ADC120_BASE 0x40170000
#define R_ADC121_BASE 0x40170200
/* Not included in SVD */
#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
#define R_DAC120_BASE 0x40172000
#define R_DAC121_BASE 0x40172100
#else
#define R_DAC12_BASE 0x40171000
#endif
#define R_FLAD_BASE 0x407FC000
#define R_FACI_HP_CMD_BASE 0x407E0000
#define R_FACI_HP_BASE 0x407FE000
#define R_QSPI_BASE 0x64000000
#define R_TFU_BASE 0x40021000
/* Not included in SVD */
#if (2U == BSP_FEATURE_IOPORT_VERSION)
#define R_PORT0_BASE 0x4001F000
#define R_PORT1_BASE 0x4001F020
#define R_PORT2_BASE 0x4001F040
#define R_PORT10_BASE 0x4001F140
#define R_PORT11_BASE 0x4001F160
#define R_PORT12_BASE 0x4001F180
#define R_PORT13_BASE 0x4001F1A0
#define R_PORT14_BASE 0x4001F1C0
#define R_PFS_BASE 0x4001F800
#define R_PMISC_BASE 0x4001FD00
#else
#define R_PORT0_BASE 0x40080000
#define R_PORT1_BASE 0x40080020
#define R_PORT2_BASE 0x40080040
#define R_PORT3_BASE 0x40080060
#define R_PORT4_BASE 0x40080080
#define R_PORT5_BASE 0x400800A0
#define R_PORT6_BASE 0x400800C0
#define R_PORT7_BASE 0x400800E0
#define R_PORT8_BASE 0x40080100
#define R_PORT9_BASE 0x40080120
#define R_PORT10_BASE 0x40080140
#define R_PORT11_BASE 0x40080160
#define R_PFS_BASE 0x40080800
#define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this
#endif
#define R_GPT_POEG0_BASE 0x4008A000
#define R_GPT_POEG1_BASE 0x4008A100
#define R_GPT_POEG2_BASE 0x4008A200
#define R_GPT_POEG3_BASE 0x4008A300
#define R_RTC_BASE 0x40083000
#define R_I3C0_BASE 0x4011F000
#define R_I3C1_BASE 0x4011F400
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
// #define R_MPU ((R_MPU_Type *) R_MPU_BASE)
#define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
#define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
#define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
#define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
#define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
#define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
#define R_TZF ((R_TZF_Type *) R_TZF_BASE)
#define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
#define R_BUS ((R_BUS_B_Type *) R_BUS_BASE)
#define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
#define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
#define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
#define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
#define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
#define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
#define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
#define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
#define R_DMA ((R_DMA_Type *) R_DMA_BASE)
#define R_DTC ((R_DTC_Type *) R_DTC_BASE)
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
#define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
#define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
#define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE)
#define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
#define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE)
#define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
#define R_ELC ((R_ELC_Type *) R_ELC_BASE)
#define R_TC ((R_TC_Type *) R_TC_BASE)
#define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
#define R_KINT ((R_KINT_Type *) R_KINT_BASE)
#define R_WDT ((R_WDT_Type *) R_WDT_BASE)
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
#define R_POEG ((R_POEG_Type *) R_POEG_BASE)
#define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
#define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
#define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
#define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE)
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
#define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
#define R_CEC ((R_CEC_Type *) R_CEC_BASE)
#if BSP_FEATURE_CANFD_LITE
#define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE)
#else
#define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
#endif
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
#define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
#if BSP_FEATURE_AGT_HAS_AGTW
#define R_AGT0 ((R_AGTW0_Type *) R_AGT0_BASE)
#define R_AGT1 ((R_AGTW0_Type *) R_AGT1_BASE)
#define R_AGT2 ((R_AGTW0_Type *) R_AGT2_BASE)
#define R_AGT3 ((R_AGTW0_Type *) R_AGT3_BASE)
#define R_AGT4 ((R_AGTW0_Type *) R_AGT4_BASE)
#define R_AGT5 ((R_AGTW0_Type *) R_AGT5_BASE)
#else
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
#define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE)
#define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE)
#define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE)
#define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE)
#endif
#define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
#define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
#if (2U == BSP_FEATURE_DOC_VERSION)
#define R_DOC_B ((R_DOC_B_Type *) R_DOC_BASE)
#else
#define R_DOC ((R_DOC_Type *) R_DOC_BASE)
#endif
#define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
#define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
#if (2U == BSP_FEATURE_SCI_VERSION)
#define R_SCI0 ((R_SCI_B0_Type *) R_SCI0_BASE)
#define R_SCI1 ((R_SCI_B0_Type *) R_SCI1_BASE)
#define R_SCI2 ((R_SCI_B0_Type *) R_SCI2_BASE)
#define R_SCI3 ((R_SCI_B0_Type *) R_SCI3_BASE)
#define R_SCI4 ((R_SCI_B0_Type *) R_SCI4_BASE)
#define R_SCI9 ((R_SCI_B0_Type *) R_SCI9_BASE)
#else
#define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
#define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
#define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
#define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
#define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
#define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
#define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
#define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
#define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
#define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
#endif
#define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
#define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
#define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE)
#define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE)
#define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE)
#define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE)
#define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE)
#define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE)
#define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE)
#define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE)
#define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE)
#define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE)
#define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE)
#define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE)
#define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
#define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
#define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE)
#define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE)
#define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE)
#define R_ADC_B ((R_ADC_B0_Type *) R_ADC120_BASE)
#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U)
#define R_DAC0 ((R_DAC_Type *) R_DAC120_BASE)
#define R_DAC1 ((R_DAC_Type *) R_DAC121_BASE)
#else
#define R_DAC ((R_DAC_Type *) R_DAC12_BASE)
#endif
#define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
#define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
#define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
#define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
#define R_TFU ((R_TFU_Type *) R_TFU_BASE)
#define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
#define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE)
/* Not in SVD. */
#define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
#define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
#define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
#define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
#define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
#define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
#define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
#define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
#define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
#define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
#define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
#if (2U == BSP_FEATURE_IOPORT_VERSION)
#define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
#define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE)
#define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE)
#define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE)
#endif
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
#define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
#define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
#define R_RTC ((R_RTC_Type *) R_RTC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
#else
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
#define R_ACMPHS0_BASE 0x40085000
#define R_ACMPHS1_BASE 0x40085100
#define R_ACMPHS2_BASE 0x40085200
#define R_ACMPHS3_BASE 0x40085300
#define R_ACMPHS4_BASE 0x40085400
#define R_ACMPHS5_BASE 0x40085500
#define R_ACMPLP_BASE 0x40085E00
#define R_ADC0_BASE 0x4005C000
#define R_ADC1_BASE 0x4005C200
#define R_AGT0_BASE 0x40084000
#define R_AGT1_BASE 0x40084100
#define R_AGTW0_BASE 0x40084000
#define R_AGTW1_BASE 0x40084100
#define R_BUS_BASE 0x40003000
#define R_CAC_BASE 0x40044600
#define R_CAN0_BASE 0x40050000
#define R_CAN1_BASE 0x40051000
#define R_CRC_BASE 0x40074000
#define R_CTSU_BASE 0x40081000
#define R_CTSU2_BASE 0x40082000
#define R_DAC_BASE 0x4005E000
#define R_DAC8_BASE 0x4009E000
#define R_DALI0_BASE 0x4008F000
#define R_DEBUG_BASE 0x4001B000
#define R_DMA_BASE 0x40005200
#define R_DMAC0_BASE 0x40005000
#define R_DMAC1_BASE 0x40005040
#define R_DMAC2_BASE 0x40005080
#define R_DMAC3_BASE 0x400050C0
#define R_DMAC4_BASE 0x40005100
#define R_DMAC5_BASE 0x40005140
#define R_DMAC6_BASE 0x40005180
#define R_DMAC7_BASE 0x400051C0
#define R_DOC_BASE 0x40054100
#define R_DRW_BASE 0x400E4000
#define R_DTC_BASE 0x40005400
#define R_ELC_BASE 0x40041000
#define R_ETHERC0_BASE 0x40064100
#define R_ETHERC_EDMAC_BASE 0x40064000
#define R_PTP_EDMAC_BASE 0x40064400
#define R_ETHERC_EPTPC_BASE 0x40065800
#define R_ETHERC_EPTPC1_BASE 0x40065C00
#define R_ETHERC_EPTPC_CFG_BASE 0x40064500
#define R_ETHERC_EPTPC_COMMON_BASE 0x40065000
#define R_FACI_HP_CMD_BASE 0x407E0000
#define R_FACI_HP_BASE 0x407FE000
#define R_FACI_LP_BASE 0x407EC000
#define R_CTSUTRIM_BASE 0x407EC000
#define R_FCACHE_BASE 0x4001C000
#define R_GLCDC_BASE 0x400E0000
#define R_GPT0_BASE 0x40078000
#define R_GPT1_BASE 0x40078100
#define R_GPT2_BASE 0x40078200
#define R_GPT3_BASE 0x40078300
#define R_GPT4_BASE 0x40078400
#define R_GPT5_BASE 0x40078500
#define R_GPT6_BASE 0x40078600
#define R_GPT7_BASE 0x40078700
#define R_GPT8_BASE 0x40078800
#define R_GPT9_BASE 0x40078900
#define R_GPT10_BASE 0x40078A00
#define R_GPT11_BASE 0x40078B00
#define R_GPT12_BASE 0x40078C00
#define R_GPT13_BASE 0x40078D00
#define R_GPT_ODC_BASE 0x4007B000
#define R_GPT_OPS_BASE 0x40078FF0
#define R_GPT_POEG0_BASE 0x40042000
#define R_GPT_POEG1_BASE 0x40042100
#define R_GPT_POEG2_BASE 0x40042200
#define R_GPT_POEG3_BASE 0x40042300
#define R_I3C0_BASE 0x40083000
#define R_ICU_BASE 0x40006000
#define R_IIC0_BASE 0x40053000
#define R_IIC1_BASE 0x40053100
#define R_IIC2_BASE 0x40053200
#define R_IRDA_BASE 0x40070F00
#define R_IWDT_BASE 0x40044400
#define R_JPEG_BASE 0x400E6000
#define R_KINT_BASE 0x40080000
#define R_MMF_BASE 0x40001000
#define R_MPU_MMPU_BASE 0x40000000
#define R_MPU_SMPU_BASE 0x40000C00
#define R_MPU_SPMON_BASE 0x40000D00
#define R_MSTP_BASE (0x40047000 - 4U) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */
#define R_OPAMP_BASE 0x40086000
#define R_OPAMP2_BASE 0x400867F8
#define R_PDC_BASE 0x40094000
#define R_PORT0_BASE 0x40040000
#define R_PORT1_BASE 0x40040020
#define R_PORT2_BASE 0x40040040
#define R_PORT3_BASE 0x40040060
#define R_PORT4_BASE 0x40040080
#define R_PORT5_BASE 0x400400A0
#define R_PORT6_BASE 0x400400C0
#define R_PORT7_BASE 0x400400E0
#define R_PORT8_BASE 0x40040100
#define R_PORT9_BASE 0x40040120
#define R_PORT10_BASE 0x40040140
#define R_PORT11_BASE 0x40040160
#define R_PFS_BASE 0x40040800
#define R_PMISC_BASE 0x40040D00
#define R_QSPI_BASE 0x64000000
#define R_RTC_BASE 0x40044000
#define R_SCI0_BASE 0x40070000
#define R_SCI1_BASE 0x40070020
#define R_SCI2_BASE 0x40070040
#define R_SCI3_BASE 0x40070060
#define R_SCI4_BASE 0x40070080
#define R_SCI5_BASE 0x400700A0
#define R_SCI6_BASE 0x400700C0
#define R_SCI7_BASE 0x400700E0
#define R_SCI8_BASE 0x40070100
#define R_SCI9_BASE 0x40070120
#define R_SDADC0_BASE 0x4009C000
#define R_SDHI0_BASE 0x40062000
#define R_SDHI1_BASE 0x40062400
#define R_SLCDC_BASE 0x40082000
#define R_SPI0_BASE 0x40072000
#define R_SPI1_BASE 0x40072100
#define R_SRAM_BASE 0x40002000
#define R_SRC_BASE 0x40048000
#define R_SSI0_BASE 0x4004E000
#define R_SSI1_BASE 0x4004E100
#define R_SYSTEM_BASE 0x4001E000
#define R_TSN_BASE 0x407EC000
#define R_TSN_CAL_BASE 0x407FB17C
#define R_TSN_CTRL_BASE 0x4005D000
#define R_USB_FS0_BASE 0x40090000
#define R_USB_HS0_BASE 0x40060000
#define R_WDT_BASE 0x40044200
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
#define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
#define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
#define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
#define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
#define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
#define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE)
#define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE)
#define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
#define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE)
#define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE)
#define R_BUS ((R_BUS_Type *) R_BUS_BASE)
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
#if (2U == BSP_FEATURE_CTSU_VERSION)
#define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE)
#else
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
#endif
#define R_DAC ((R_DAC_Type *) R_DAC_BASE)
#define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE)
#define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE)
#define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE)
#define R_DMA ((R_DMA_Type *) R_DMA_BASE)
#define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
#define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
#define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
#define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
#define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
#define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
#define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
#define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
#define R_DOC ((R_DOC_Type *) R_DOC_BASE)
#define R_DRW ((R_DRW_Type *) R_DRW_BASE)
#define R_DTC ((R_DTC_Type *) R_DTC_BASE)
#define R_ELC ((R_ELC_Type *) R_ELC_BASE)
#define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
#define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
#define R_PTP_EDMAC ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE)
#define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE)
#define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC0_Type *) R_ETHERC_EPTPC1_BASE)
#define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE)
#define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE)
#define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
#define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
#define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE)
#define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE)
#define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
#define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE)
#define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE)
#define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE)
#define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE)
#define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE)
#define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE)
#define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE)
#define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE)
#define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE)
#define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE)
#define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE)
#define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE)
#define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE)
#define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE)
#define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE)
#define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
#define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
#define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
#define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
#define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE)
#define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE)
#define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
#define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE)
#define R_KINT ((R_KINT_Type *) R_KINT_BASE)
#define R_MMF ((R_MMF_Type *) R_MMF_BASE)
#define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
#define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
#define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
#if (2U == BSP_FEATURE_OPAMP_BASE_ADDRESS)
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE)
#else
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE)
#endif
#define R_PDC ((R_PDC_Type *) R_PDC_BASE)
#define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
#define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
#define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
#define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
#define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
#define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
#define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
#define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
#define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
#define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
#define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
#define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
#define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
#define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
#define R_RTC ((R_RTC_Type *) R_RTC_BASE)
#define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
#define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
#define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
#define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
#define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
#define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
#define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
#define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
#define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
#define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
#define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE)
#define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
#define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE)
#define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE)
#define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
#define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
#define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
#define R_SRC ((R_SRC_Type *) R_SRC_BASE)
#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
#define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE)
#define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE)
#define R_TSN ((R_TSN_Type *) R_TSN_BASE)
#define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
#define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
#define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
#define R_WDT ((R_WDT_Type *) R_WDT_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
#endif
#endif

46628
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
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File diff suppressed because it is too large Load Diff

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

7
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -64,12 +64,7 @@ void Reset_Handler (void)
SystemInit();
/* Call user application. */
#ifdef __ARMCC_VERSION
main();
#elif defined(__GNUC__)
extern int entry(void);
entry();
#endif
while (1)
{

93
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -36,6 +36,9 @@
/* Mask to select CP bits( 0xF00000 ) */
#define CP_MASK (0xFU << 20)
/* Startup value for CCR to enable instruction cache, branch prediction and LOB extension */
#define CCR_CACHE_ENABLE (0x000E0201)
/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U)
@ -43,19 +46,8 @@
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
#if defined(__ICCARM__)
#define BSP_PRV_STACK_LIMIT ((uint32_t) __section_begin(".stack"))
#define BSP_PRV_STACK_TOP ((uint32_t) __section_end(".stack"))
#elif defined(__ARMCC_VERSION)
#define BSP_PRV_STACK_LIMIT ((uint32_t) &Image$$STACK$$ZI$$Base)
#define BSP_PRV_STACK_TOP ((uint32_t) &Image$$STACK$$ZI$$Base + \
(uint32_t) &Image$$STACK$$ZI$$Length)
#elif defined(__GNUC__)
#define BSP_PRV_STACK_LIMIT ((uint32_t) &__StackLimit)
#define BSP_PRV_STACK_TOP ((uint32_t) &__StackTop)
#endif
#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES)
#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0])
#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5)
/***********************************************************************************************************************
@ -77,6 +69,11 @@ extern uint32_t Image$$DATA$$Base;
extern uint32_t Image$$DATA$$Length;
extern uint32_t Image$$STACK$$ZI$$Base;
extern uint32_t Image$$STACK$$ZI$$Length;
#if BSP_FEATURE_BSP_HAS_DTCM == 1
extern uint32_t Load$$DTCM_DATA_INIT$$Base;
extern uint32_t Image$$DTCM_DATA_INIT$$Base;
extern uint32_t Image$$DTCM_DATA_INIT$$Length;
#endif
#elif defined(__GNUC__)
/* Generated by linker. */
@ -87,11 +84,20 @@ extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackLimit;
extern uint32_t __StackTop;
#if BSP_FEATURE_BSP_HAS_DTCM == 1
extern uint32_t __dtcm_data_init_start;
extern uint32_t __dtcm_data_start__;
extern uint32_t __dtcm_data_end__;
#endif
#elif defined(__ICCARM__)
#pragma section=".bss"
#pragma section=".data"
#pragma section=".data_init"
#pragma section=".stack"
#if BSP_FEATURE_BSP_HAS_DTCM == 1
#pragma section=".dtcm_data"
#pragma section=".dtcm_data_init"
#endif
#endif
/* Initialize static constructors */
@ -145,6 +151,15 @@ static void bsp_init_uninitialized_vars(void);
**********************************************************************************************************************/
void SystemInit (void)
{
#if defined(RENESAS_CORTEX_M85)
/* Enable the ARM core instruction cache, branch prediction and low-overhead-branch extension.
* See Section 5.5 of the Cortex-M55 TRM and Section D1.2.9 in the ARMv8-M Architecture Reference Manual */
SCB->CCR = (uint32_t) CCR_CACHE_ENABLE;
__DSB();
__ISB();
#endif
#if __FPU_USED
/* Enable the FPU only when it is used.
@ -221,6 +236,16 @@ void SystemInit (void)
#endif
#endif
#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN
/* Turn on graphics power domain.
* This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
R_SYSTEM->PDCTRGD = 0;
(void) R_SYSTEM->PDCTRGD;
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
#endif
/* Call post clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
@ -247,9 +272,14 @@ void SystemInit (void)
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE
#if 33U == __CORTEX_M
/* Use CM33 stack monitor. */
__set_MSPLIM(BSP_PRV_STACK_LIMIT);
#else
/* CM85 stack monitor not yet supported. */
#endif
#endif
#if BSP_CFG_C_RUNTIME_INIT
@ -267,10 +297,21 @@ void SystemInit (void)
/* Copy initialized RAM data from ROM to RAM. */
#if defined(__ARMCC_VERSION)
memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);
#if BSP_FEATURE_BSP_HAS_DTCM == 1
memcpy((uint8_t *) &Image$$DTCM_DATA_INIT$$Base,
(uint8_t *) &Load$$DTCM_DATA_INIT$$Base,
(uint32_t) &Image$$DTCM_DATA_INIT$$Length);
#endif
#elif defined(__GNUC__)
memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));
#if BSP_FEATURE_BSP_HAS_DTCM == 1
memcpy(&__dtcm_data_start__,
&__dtcm_data_init_start,
((uint32_t) &__dtcm_data_end__ - (uint32_t) &__dtcm_data_start__));
#endif
#elif defined(__ICCARM__)
memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),
memcpy((uint32_t *) __section_begin(".data"),
(uint32_t *) __section_begin(".data_init"),
(uint32_t) __section_size(".data"));
/* Copy functions to be executed from RAM. */
@ -283,8 +324,14 @@ void SystemInit (void)
/* Copy main thread TLS to RAM. */
#pragma section="__DLIB_PERTHREAD_init"
#pragma section="__DLIB_PERTHREAD"
memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"),
(uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
(uint32_t) __section_size("__DLIB_PERTHREAD_init"));
#if BSP_FEATURE_BSP_HAS_DTCM == 1
memcpy((uint32_t *) __section_begin(".dtcm_data"),
(uint32_t *) __section_begin(".dtcm_data_init"),
(uint32_t) __section_size(".dtcm_data"));
#endif
#endif
/* Initialize static constructors */
@ -296,14 +343,12 @@ void SystemInit (void)
(void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);
p_init_func();
}
#elif defined(__GNUC__)
int32_t count = __init_array_end - __init_array_start;
for (int32_t i = 0; i < count; i++)
{
__init_array_start[i]();
}
#elif defined(__ICCARM__)
void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
void const * ilimit = __section_end("SHT$$INIT_ARRAY");
@ -314,8 +359,18 @@ void SystemInit (void)
/* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate();
#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
/* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */
#if !BSP_TZ_NONSECURE_BUILD
/* Perform RTC reset sequence to avoid unintended operation. */
R_BSP_Init_RTC();
#endif
#endif
#if !BSP_CFG_PFS_PROTECT
#if BSP_TZ_SECURE_BUILD
#if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else

12
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -21,7 +21,11 @@
/** @} (end addtogroup BSP_MCU) */
#ifndef BSP_ARM_EXCEPTIONS_H
#define BSP_ARM_EXCEPTIONS_H
#define BSP_ARM_EXCEPTIONS_H
#ifdef __cplusplus
extern "C" {
#endif
/***********************************************************************************************************************
* Macro definitions
@ -47,4 +51,8 @@ typedef enum IRQn
SysTick_IRQn = -1, /* 15 System Tick Timer */
} IRQn_Type;
#ifdef __cplusplus
}
#endif
#endif

1031
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
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File diff suppressed because it is too large Load Diff

1030
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
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File diff suppressed because it is too large Load Diff

13
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.c
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -75,10 +75,13 @@ void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); ///
/* FSP pack version structure. */
static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
{
.minor = FSP_VERSION_MINOR,
.major = FSP_VERSION_MAJOR,
.build = FSP_VERSION_BUILD,
.patch = FSP_VERSION_PATCH
.version_id_b =
{
.minor = FSP_VERSION_MINOR,
.major = FSP_VERSION_MAJOR,
.build = FSP_VERSION_BUILD,
.patch = FSP_VERSION_PATCH
}
};
/* Public FSP version name. */

125
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_common.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -125,6 +125,12 @@ FSP_HEADER
#define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
#endif
#ifndef FSP_REGISTER_READ
/* Read a register and discard the result. */
#define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A));
#endif
/****************************************************************
*
* This check is performed to select suitable ASM API with respect to core
@ -180,11 +186,15 @@ FSP_HEADER
/** Used to signify that the requested IRQ vector is not defined in this system. */
#define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
/* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */
#define FSP_PRIV_SCKDIVCR_DIV_MASK (7)
/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */
#if (BSP_CFG_MCU_PART_SERIES == 8)
#define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU)
#else
#define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
#endif
/* Use the secure registers for secure projects and flat projects. */
#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE && !(BSP_CFG_MCU_PART_SERIES == 8)
#define FSP_PRIV_TZ_USE_SECURE_REGS (1)
#else
#define FSP_PRIV_TZ_USE_SECURE_REGS (0)
@ -246,7 +256,6 @@ typedef struct st_bsp_unique_id
* Exported global variables
**********************************************************************************************************************/
uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
/***********************************************************************************************************************
* Global variables (defined in other files)
**********************************************************************************************************************/
@ -276,10 +285,68 @@ __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
{
uint32_t sckdivcr = R_SYSTEM->SCKDIVCR;
uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK;
uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK;
#if BSP_FEATURE_CGC_HAS_CPUCLK
/* Get CPUCLK divisor */
uint32_t cpuclk_div = R_SYSTEM->SCKDIVCR2 & FSP_PRV_SCKDIVCR_DIV_MASK;
/* Determine if either divisor is a multiple of 3 */
if ((cpuclk_div | clock_div) & 8U)
{
/* Convert divisor settings to their actual values */
cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div);
clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div);
/* Calculate clock with multiplication and division instead of shifting */
return (SystemCoreClock * cpuclk_div) / clock_div;
}
else
{
return (SystemCoreClock << cpuclk_div) >> clock_div;
}
#else
uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
return (SystemCoreClock << iclk_div) >> clock_div;
#endif
}
/*******************************************************************************************************************//**
* Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
*
* @return Clock Divider
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
{
if (2U >= ckdivcr)
{
/* clock_div:
* - Clock Divided by 1: 0
* - Clock Divided by 2: 1
* - Clock Divided by 4: 2
*/
return 1 << ckdivcr;
}
else if (3U == ckdivcr)
{
/* Clock Divided by 6 */
return 6U;
}
else if (4U == ckdivcr)
{
/* Clock Divided by 8 */
return 8U;
}
else if (5U == ckdivcr)
{
/* Clock Divided by 3 */
return 3U;
}
/* Clock Divided by 5 */
return 5U;
}
#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
@ -292,10 +359,44 @@ __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
{
uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
uint32_t clock_div = (scispidivcr & FSP_PRIV_SCKDIVCR_DIV_MASK);
uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
return R_BSP_SourceClockHzGet(scispicksel) >> clock_div;
return R_BSP_SourceClockHzGet(scispicksel) / clock_div;
}
#endif
#if BSP_FEATURE_BSP_HAS_SPI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SPI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void)
{
uint32_t spidivcr = R_SYSTEM->SPICKDIVCR;
uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t spicksel = (fsp_priv_source_clock_t) R_SYSTEM->SPICKCR_b.CKSEL;
return R_BSP_SourceClockHzGet(spicksel) / clock_div;
}
#endif
#if BSP_FEATURE_BSP_HAS_SCI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SCI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void)
{
uint32_t scidivcr = R_SYSTEM->SCICKDIVCR;
uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCICKCR_b.SCICKSEL;
return R_BSP_SourceClockHzGet(scicksel) / clock_div;
}
#endif
@ -305,7 +406,7 @@ __STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
*
* @return A pointer to the unique identifier structure
**********************************************************************************************************************/
__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet ()
__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
{
return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
}
@ -313,7 +414,7 @@ __STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet ()
/*******************************************************************************************************************//**
* Disables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheDisable ()
__STATIC_INLINE void R_BSP_FlashCacheDisable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
R_FCACHE->FCACHEE = 0U;
@ -329,7 +430,7 @@ __STATIC_INLINE void R_BSP_FlashCacheDisable ()
/*******************************************************************************************************************//**
* Enables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheEnable ()
__STATIC_INLINE void R_BSP_FlashCacheEnable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE

106
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -24,72 +24,84 @@
**********************************************************************************************************************/
#ifndef BSP_COMPILER_SUPPORT_H
#define BSP_COMPILER_SUPPORT_H
#define BSP_COMPILER_SUPPORT_H
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
#include "arm_cmse.h"
#endif
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
#include "arm_cmse.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ARMCC_VERSION) /* AC6 compiler */
#if defined(__ARMCC_VERSION) /* AC6 compiler */
/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load
* memory (ROM) is reserved unnecessarily. */
#define BSP_UNINIT_SECTION_PREFIX ".bss"
#define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__GNUC__) /* GCC compiler */
#define BSP_UNINIT_SECTION_PREFIX
#define BSP_SECTION_HEAP ".heap"
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__ICCARM__) /* IAR compiler */
#define BSP_UNINIT_SECTION_PREFIX
#define BSP_SECTION_HEAP "HEAP"
#define BSP_DONT_REMOVE __root
#define BSP_ATTRIBUTE_STACKLESS __stackless
#define BSP_FORCE_INLINE _Pragma("inline=forced")
#endif
#define BSP_UNINIT_SECTION_PREFIX ".bss"
#ifndef BSP_SECTION_HEAP
#define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
#endif
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__GNUC__) /* GCC compiler */
#define BSP_UNINIT_SECTION_PREFIX
#ifndef BSP_SECTION_HEAP
#define BSP_SECTION_HEAP ".heap"
#endif
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__ICCARM__) /* IAR compiler */
#define BSP_UNINIT_SECTION_PREFIX
#ifndef BSP_SECTION_HEAP
#define BSP_SECTION_HEAP "HEAP"
#endif
#define BSP_DONT_REMOVE __root
#define BSP_ATTRIBUTE_STACKLESS __stackless
#define BSP_FORCE_INLINE _Pragma("inline=forced")
#endif
#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack"
#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
#define BSP_SECTION_ROM_REGISTERS ".rom_registers"
#define BSP_SECTION_ID_CODE ".id_code"
#ifndef BSP_SECTION_STACK
#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack"
#endif
#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
#define BSP_SECTION_ROM_REGISTERS ".rom_registers"
#define BSP_SECTION_ID_CODE ".id_code"
/* Compiler neutral macros. */
#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
#define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED
#define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED
#define BSP_WEAK_REFERENCE __attribute__((weak))
#define BSP_WEAK_REFERENCE __attribute__((weak))
/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
#define BSP_STACK_ALIGNMENT (8)
#define BSP_STACK_ALIGNMENT (8)
/***********************************************************************************************************************
* TrustZone definitions
**********************************************************************************************************************/
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__)
#if defined(__ICCARM__) /* IAR compiler */
#define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call
#define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__)
#if defined(__ICCARM__) /* IAR compiler */
#define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call
#define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry
#else
#define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call))
#define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
#endif
#else
#define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call))
#define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
#define BSP_CMSE_NONSECURE_CALL
#define BSP_CMSE_NONSECURE_ENTRY
#endif
#else
#define BSP_CMSE_NONSECURE_CALL
#define BSP_CMSE_NONSECURE_ENTRY
#endif
/***********************************************************************************************************************
* Exported global variables
@ -101,4 +113,8 @@
/** @} (end of addtogroup BSP_MCU) */
#ifdef __cplusplus
}
#endif
#endif

24
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -160,23 +160,29 @@ void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
* prologue/epilogue sequences generated by the compiler.
* @param[in] loop_cnt The number of loops to iterate.
**********************************************************************************************************************/
BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__(
(unused)) uint32_t loop_cnt)
{
__asm volatile ("sw_delay_loop: \n"
__asm volatile (
#if defined(RENESAS_CORTEX_M85) && (defined(__ARMCC_VERSION) || defined(__GNUC__))
/* Optimize inner loop execution time on CM85 cores (Alignment allows for instruction fusion). */
".align 8\n"
#endif
"sw_delay_loop: \n"
#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
" subs r0, #1 \n" ///< 1 cycle
" subs r0, #1 \n" ///< 1 cycle
#elif defined(__GNUC__)
" sub r0, r0, #1 \n" ///< 1 cycle
" sub r0, r0, #1 \n" ///< 1 cycle
#endif
" cmp r0, #0 \n" ///< 1 cycle
" cmp r0, #0 \n" ///< 1 cycle
/* CM0 and CM23 have a different instruction set */
#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
" bne sw_delay_loop \n" ///< 2 cycles
" bne sw_delay_loop \n" ///< 2 cycles
#else
" bne.n sw_delay_loop \n" ///< 2 cycles
" bne.n sw_delay_loop \n" ///< 2 cycles
#endif
" bx lr \n"); ///< 2 cycles
" bx lr \n"); ///< 2 cycles
}

16
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_delay.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -41,7 +41,19 @@ FSP_HEADER
/* The number of cycles required per software delay loop. */
#ifndef BSP_DELAY_LOOP_CYCLES
#define BSP_DELAY_LOOP_CYCLES (4)
#if defined(RENESAS_CORTEX_M85)
/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for
* GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in
* this case. */
#if defined(__ICCARM__)
#define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1)
#else
#define BSP_DELAY_LOOP_CYCLES (1)
#endif
#else
#define BSP_DELAY_LOOP_CYCLES (4)
#endif
#endif
/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle

4
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -105,7 +105,7 @@ void NMI_Handler (void)
uint16_t nmisr = R_ICU->NMISR;
/* Loop over all NMI status flags */
for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_CACHE_PARITY; irq++)
for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_GRP_IRQ_TOTAL_ITEMS - 1); irq++)
{
/* If the current irq status register is set call the irq callback. */
if (0U != (nmisr & (1U << irq)))

6
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -38,6 +38,8 @@ FSP_HEADER
* Typedef definitions
**********************************************************************************************************************/
#ifndef BSP_OVERRIDE_GROUP_IRQ_T
/** Which interrupts can have callbacks registered. */
typedef enum e_bsp_grp_irq
{
@ -57,6 +59,8 @@ typedef enum e_bsp_grp_irq
BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error
} bsp_grp_irq_t;
#endif
/* Callback type. */
typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq);

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_guard.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

6
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_io.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -409,7 +409,7 @@ __STATIC_INLINE void R_BSP_PinAccessEnable (void)
/** If this is first entry then allow writing of PFS. */
if (0 == g_protect_pfswe_counter)
{
#if BSP_TZ_SECURE_BUILD
#if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else
@ -448,7 +448,7 @@ __STATIC_INLINE void R_BSP_PinAccessDisable (void)
/** Is it safe to disable writing of PFS? */
if (0 == g_protect_pfswe_counter)
{
#if BSP_TZ_SECURE_BUILD
#if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8)
R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled
#else

9
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -74,7 +74,12 @@ void bsp_irq_cfg (void)
#if !BSP_TZ_SECURE_BUILD
/* Set the DMAC channels to secure access. */
#ifdef BSP_TZ_CFG_ICUSARC
R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk;
#endif
#ifdef BSP_TZ_CFG_DMASARA
R_CPSCU->DMASARA = ~R_CPSCU_DMASARA_DMASARAn_Msk;
#endif
#endif
/* Place all vectors in non-secure state unless they are used in the secure project. */
@ -105,7 +110,7 @@ void bsp_irq_cfg (void)
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++)
for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++)
{
R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i];
}

14
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_irq.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -71,6 +71,10 @@ __STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
{
/* Clear the IR bit in the selected IELSR register. */
R_ICU->IELSR_b[irq].IR = 0U;
/* Read back the IELSR register to ensure that the IR bit is cleared.
* MREF_INTERNAL_001 */
FSP_REGISTER_READ(R_ICU->IELSR[irq]);
}
/*******************************************************************************************************************//**
@ -86,6 +90,9 @@ __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
/* Clear the IR bit in the selected IELSR register. */
R_BSP_IrqStatusClear(irq);
/* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */
__DMB();
/* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
* exceptions every time an interrupt is cleared in the NVIC. */
uint32_t _irq = (uint32_t) irq;
@ -133,7 +140,10 @@ __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
/* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
* every time an interrupt is enabled in the NVIC. */
uint32_t _irq = (uint32_t) irq;
NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
__COMPILER_BARRIER();
NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
__COMPILER_BARRIER();
}
/*******************************************************************************************************************//**

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

43
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -24,6 +24,10 @@
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#if __has_include("internal/bsp_module_stop_internal.h")
#include "internal/bsp_module_stop_internal.h"
#endif
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
@ -48,7 +52,7 @@ FSP_HEADER
#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \
BSP_MSTP_REG_ ## ip(channel); \
FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \
FSP_CRITICAL_SECTION_EXIT;}
/*******************************************************************************************************************//**
@ -60,7 +64,7 @@ FSP_HEADER
#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \
BSP_MSTP_REG_ ## ip(channel); \
FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \
FSP_CRITICAL_SECTION_EXIT;}
/** @} (end addtogroup BSP_MCU) */
@ -69,20 +73,35 @@ FSP_HEADER
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \
channel) ? (1U << 5U) : (1U << 6U));
#define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
#ifndef BSP_MSTP_REG_FSP_IP_AGT
#define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
#endif
#ifndef BSP_MSTP_BIT_FSP_IP_AGT
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
#endif
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U));
#else
#if (2U == BSP_FEATURE_ELC_VERSION)
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31);
#define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
#if BSP_MCU_GROUP_RA6T2
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31);
#define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
#else
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
#define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel));
#endif
#define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U);
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
#define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel));
#else
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
@ -104,6 +123,8 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel));
#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U));
#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel));
#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel));
#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB
@ -150,12 +171,14 @@ FSP_HEADER
#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel));
#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel));
#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel));
#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel));
#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel));
#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U));
#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel));
#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel));
#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

92
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -62,7 +62,28 @@
#if !BSP_CFG_BOOT_IMAGE
#if 33U != __CORTEX_M // NOLINT(readability-magic-numbers)
#if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
/** ID code definitions defined here. */
BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
{
BSP_CFG_ID_CODE_LONG_1,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_2,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_3,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_4
};
#endif
#if 33U != __CORTEX_M && 85U != __CORTEX_M // NOLINT(readability-magic-numbers)
/** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) =
@ -84,23 +105,25 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION
(uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
};
/** ID code definitions defined here. */
BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
{
BSP_CFG_ID_CODE_LONG_1,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#elif BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
#if !BSP_TZ_NONSECURE_BUILD
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
BSP_CFG_ROM_REG_OFS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
BSP_ROM_REG_OFS1_SETTING;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
BSP_CFG_ROM_REG_BPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
BSP_CFG_ROM_REG_PBPS0;
#endif
BSP_CFG_ID_CODE_LONG_2,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_3,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_4
};
#else /* CM33 parts */
@ -109,6 +132,11 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
BSP_CFG_ROM_REG_OFS0;
#if BSP_FEATURE_BSP_HAS_OFS2
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_rom_ofs2 =
BSP_CFG_ROM_REG_OFS2;
#endif
#if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_rom_dualsel =
BSP_CFG_ROM_REG_DUALSEL;
@ -121,6 +149,12 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas"
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_rom_ofs1 =
BSP_ROM_REG_OFS1_SETTING;
#if BSP_FEATURE_BSP_HAS_OFS3
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3") g_bsp_rom_ofs3 =
BSP_CFG_ROM_REG_OFS3;
#endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_rom_banksel =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps0") g_bsp_rom_bps0 =
@ -129,12 +163,16 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps1
BSP_CFG_ROM_REG_BPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps2") g_bsp_rom_bps2 =
BSP_CFG_ROM_REG_BPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps3") g_bsp_rom_bps3 =
BSP_CFG_ROM_REG_BPS3;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps0") g_bsp_rom_pbps0 =
BSP_CFG_ROM_REG_PBPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps1") g_bsp_rom_pbps1 =
BSP_CFG_ROM_REG_PBPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps2") g_bsp_rom_pbps2 =
BSP_CFG_ROM_REG_PBPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps3") g_bsp_rom_pbps3 =
BSP_CFG_ROM_REG_PBPS3;
#endif
@ -142,6 +180,12 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1_sec =
BSP_ROM_REG_OFS1_SETTING;
#if BSP_FEATURE_BSP_HAS_OFS3
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sec") g_bsp_rom_ofs3_sec =
BSP_CFG_ROM_REG_OFS3;
#endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_rom_banksel_sec =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps_sec0 =
@ -150,14 +194,24 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_
BSP_CFG_ROM_REG_BPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec2") g_bsp_rom_bps_sec2 =
BSP_CFG_ROM_REG_BPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec3") g_bsp_rom_bps_sec3 =
BSP_CFG_ROM_REG_BPS3;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps_sec0 =
BSP_CFG_ROM_REG_PBPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec1") g_bsp_rom_pbps_sec1 =
BSP_CFG_ROM_REG_PBPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec2") g_bsp_rom_pbps_sec2 =
BSP_CFG_ROM_REG_PBPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec3") g_bsp_rom_pbps_sec3 =
BSP_CFG_ROM_REG_PBPS3;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_rom_ofs1_sel =
BSP_CFG_ROM_REG_OFS1_SEL;
#if BSP_FEATURE_BSP_HAS_OFS3
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sel") g_bsp_rom_ofs3_sel =
BSP_CFG_ROM_REG_OFS3_SEL;
#endif
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_rom_banksel_sel =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel0") g_bsp_rom_bps_sel0 =
@ -166,6 +220,8 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_
BSP_CFG_ROM_REG_BPS_SEL1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel2") g_bsp_rom_bps_sel2 =
BSP_CFG_ROM_REG_BPS_SEL2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel3") g_bsp_rom_bps_sel3 =
BSP_CFG_ROM_REG_BPS_SEL3;
#endif

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

153
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.c
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@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -32,6 +32,9 @@
#define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U)
#define RA_NOT_DEFINED (0)
/* Branch T3 Instruction (IMM11=-2) */
#define BSP_PRV_INFINITE_LOOP (0xE7FE)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
@ -55,39 +58,34 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
#endif
#if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD
#pragma section=".tz_flash_nsc_start"
#pragma section=".tz_flash_ns_start"
#pragma section=".tz_ram_nsc_start"
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start");
#pragma section="Veneer$$CMSE"
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) __section_begin(
"Veneer$$CMSE");
#pragma section=".tz_ram_ns_start"
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) __section_begin(".tz_ram_ns_start");
#pragma section=".tz_ram_nsc_start"
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) __section_begin(
".tz_ram_nsc_start");
#pragma section=".tz_data_flash_ns_start"
#pragma section=".tz_sdram_ns_start"
#pragma section=".tz_qspi_flash_ns_start"
#pragma section=".tz_ospi_device_0_ns_start"
#pragma section=".tz_ospi_device_1_ns_start"
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) __section_begin(
".tz_data_flash_ns_start");
/* &__tz_<REGION>_C is the address of the non-secure callable section. Must assign value to this variable or
* linker will give error. */
/* &__tz_<REGION>_N is the start address of the non-secure region. */
BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
BSP_DONT_REMOVE void const * const __tz_FLASH_N BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start" = 0;
BSP_DONT_REMOVE void * __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
BSP_DONT_REMOVE void * __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
BSP_DONT_REMOVE void * __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
#if BSP_FEATURE_SDRAM_START_ADDRESS
BSP_DONT_REMOVE void * __tz_SDRAM_N @".tz_sdram_ns_start";
#endif
BSP_DONT_REMOVE void * __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
#if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS
BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
#endif
#if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS
BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
#endif
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N;
#elif defined(__ARMCC_VERSION)
#if BSP_FEATURE_BSP_HAS_ITCM
extern const uint32_t Image$$__tz_ITCM_N$$Base;
extern const uint32_t Image$$__tz_ITCM_S$$Base;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern const uint32_t Image$$__tz_DTCM_N$$Base;
extern const uint32_t Image$$__tz_DTCM_S$$Base;
#endif
#if BSP_FEATURE_BSP_HAS_STBRAMSABAR
extern const uint32_t Image$$__tz_STANDBY_SRAM_N$$Base;
extern const uint32_t Image$$__tz_STANDBY_SRAM_S$$Base;
#endif
extern const uint32_t Image$$__tz_FLASH_N$$Base;
extern const uint32_t Image$$__tz_FLASH_C$$Base;
extern const uint32_t Image$$__tz_FLASH_S$$Base;
@ -111,6 +109,18 @@ extern const uint32_t Image$$__tz_OPTION_SETTING_S_S$$Base;
extern const uint32_t Image$$__tz_ID_CODE_N$$Base;
extern const uint32_t Image$$__tz_ID_CODE_S$$Base;
#if BSP_FEATURE_BSP_HAS_ITCM
#define __tz_ITCM_N Image$$__tz_ITCM_N$$Base
#define __tz_ITCM_S Image$$__tz_ITCM_S$$Base
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
#define __tz_DTCM_N Image$$__tz_DTCM_N$$Base
#define __tz_DTCM_S Image$$__tz_DTCM_S$$Base
#endif
#if BSP_FEATURE_BSP_HAS_STBRAMSABAR
#define __tz_STANDBY_SRAM_N Image$$__tz_STANDBY_SRAM_N$$Base
#define __tz_STANDBY_SRAM_S Image$$__tz_STANDBY_SRAM_S$$Base
#endif
#define __tz_FLASH_N Image$$__tz_FLASH_N$$Base
#define __tz_FLASH_C Image$$__tz_FLASH_C$$Base
#define __tz_FLASH_S Image$$__tz_FLASH_S$$Base
@ -136,6 +146,18 @@ extern const uint32_t Image$$__tz_ID_CODE_S$$Base;
/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the
* start addresses of Secure, Non-secure and Non-secure Callable regions. */
#if BSP_FEATURE_BSP_HAS_ITCM
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_itcm = &__tz_ITCM_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_itcm = &__tz_ITCM_S;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_dtcm = &__tz_DTCM_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_dtcm = &__tz_DTCM_S;
#endif
#if BSP_FEATURE_BSP_HAS_STBRAMSABAR
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_standby_sram = &__tz_STANDBY_SRAM_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_standby_sram = &__tz_STANDBY_SRAM_S;
#endif
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = &__tz_FLASH_C;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_flash = &__tz_FLASH_S;
@ -165,8 +187,19 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_id_code =
#endif
#elif defined(__GNUC__)
extern const uint32_t FLASH_NS_IMAGE_START;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START;
extern const uint32_t __tz_FLASH_C;
extern const uint32_t __tz_DATA_FLASH_N;
extern const uint32_t __tz_RAM_N;
extern const uint32_t __tz_RAM_C;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) &__tz_FLASH_C;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) &__tz_DATA_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) &__tz_RAM_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) &__tz_RAM_C;
#endif
#if BSP_TZ_SECURE_BUILD
@ -192,6 +225,31 @@ void R_BSP_NonSecureEnter (void)
uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t));
bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address);
#if BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
/* Check if the NS application exists. If the address of the Reset_Handler is all '1's, then assume that
* the NS application has not been programmed.
*
* If the secure application attempts to jump to an invalid instruction, a HardFault will occur. If the
* MCU is in NSECSD state, then the debugger will be unable to connect and program the NS Application. Jumping to
* a valid instruction ensures that the debugger will be able to connect.
*/
if (UINT32_MAX == *p_ns_reset_address)
{
p_ns_reset = (bsp_nonsecure_func_t) gp_start_of_nonsecure_ram;
/* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n <gp_start_of_nonsecure_ram>)). */
uint16_t * infinite_loop = (uint16_t *) gp_start_of_nonsecure_ram;
*infinite_loop = BSP_PRV_INFINITE_LOOP;
/* Set the NS stack pointer to a valid location in NS RAM. */
__TZ_set_MSP_NS((uint32_t) gp_start_of_nonsecure_ram + 0x20U);
/* Jump to the infinite loop. */
p_ns_reset();
}
#endif
/* Set the NS vector table address */
SCB_NS->VTOR = (uint32_t) p_ns_vector_table;
@ -213,6 +271,19 @@ void R_BSP_NonSecureEnter (void)
**********************************************************************************************************************/
void R_BSP_SecurityInit (void)
{
/* Disable PRCR for SARs. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
#if 0 == BSP_FEATURE_TZ_HAS_DLM
/* If DLM is not implemented, then the TrustZone partitions must be set at run-time. */
R_PSCU->CFSAMONA = (uint32_t) gp_start_of_nonsecure_flash & R_PSCU_CFSAMONA_CFS2_Msk;
R_PSCU->CFSAMONB = (uint32_t) gp_start_of_nonsecure_callable_flash & R_PSCU_CFSAMONB_CFS1_Msk;
R_PSCU->DFSAMON = (uint32_t) gp_start_of_nonsecure_data_flash & R_PSCU_DFSAMON_DFS_Msk;
R_PSCU->SSAMONA = (uint32_t) gp_start_of_nonsecure_ram & R_PSCU_SSAMONA_SS2_Msk;
R_PSCU->SSAMONB = (uint32_t) gp_start_of_nonsecure_callable_ram & R_PSCU_SSAMONB_SS1_Msk;
#endif
/* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the
* system. */
SAU->CTRL = SAU_CTRL_ALLNS_Msk;
@ -247,11 +318,11 @@ void R_BSP_SecurityInit (void)
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk);
#endif
/* Disable PRCR for SARs. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
#if BSP_FEATURE_BSP_HAS_TZFSAR
/* Set TrustZone filter to Secure. */
R_TZF->TZFSAR = ~R_TZF_TZFSAR_TZFSA0_Msk;
#endif
/* Set TrustZone filter exception response. */
R_TZF->TZFPT = BSP_PRV_TZ_REG_KEY + 1U;
@ -266,7 +337,9 @@ void R_BSP_SecurityInit (void)
R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR;
/* Initialize Type 2 SARs. */
R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
#ifdef BSP_TZ_CFG_CSAR
R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
#endif
R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */
R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */
R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */
@ -277,11 +350,21 @@ void R_BSP_SecurityInit (void)
#endif
R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */
R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */
#ifdef BSP_TZ_CFG_ICUSARC
R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */
#endif
#ifdef BSP_TZ_CFG_DMASARA
R_CPSCU->DMASARA = BSP_TZ_CFG_DMASARA; /* DMAC Channel Security Attribution. */
#endif
#ifdef BSP_TZ_CFG_ICUSARD
R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */
#endif
R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */
#ifdef BSP_TZ_CFG_ICUSARF
R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */
#endif
#ifdef BSP_TZ_CFG_TEVTRCR
R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */
#endif
R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */
R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */
@ -290,7 +373,9 @@ void R_BSP_SecurityInit (void)
R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */
R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */
#if BSP_TZ_CFG_ICUSARC != UINT32_MAX
#if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \
(defined(BSP_TZ_CFG_DMASARA) && (BSP_TZ_CFG_DMASARA != UINT32_MAX))
R_BSP_MODULE_START(FSP_IP_DMAC, 0);
/* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_security.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/bsp_tfu.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

561
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -52,289 +52,366 @@
* Private global variables and functions
**********************************************************************************************************************/
#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U)
#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC)
#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U)
#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
#define BSP_FEATURE_ADC_HAS_PGA (0U)
#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U)
#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU)
#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU
#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_SLOPE (4000)
#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FF) // 0 to 10, 12, 13
#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007) // 0 to 2, 16 to 28
#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
#define BSP_FEATURE_ADC_HAS_ADBUF (1U)
#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U)
#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U)
#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U)
#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC)
#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U)
#define BSP_FEATURE_ADC_HAS_ADBUF (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U)
#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U)
#define BSP_FEATURE_ADC_HAS_PGA (0U)
#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U)
#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU)
#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU
#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_SLOPE (4000)
#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FF) // 0 to 10, 12, 13
#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007) // 0 to 2, 16 to 28
#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U)
#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U)
#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0)
#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5)
#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL
#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F)
#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F)
#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5)
#define BSP_FEATURE_AGT_HAS_AGTW (0U)
#define BSP_FEATURE_BSP_FLASH_CACHE (1)
#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0)
#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1)
#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U)
#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock
#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0)
#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U)
#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_OFS2 (0)
#define BSP_FEATURE_BSP_HAS_OFS3 (0)
#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE
#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U)
#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_SP_MON (0U)
#define BSP_FEATURE_BSP_HAS_SYRACCR (0U)
#define BSP_FEATURE_BSP_HAS_TZFSAR (1)
#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU
#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock.
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U)
#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U)
#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU
#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid.
#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U)
#define BSP_FEATURE_BSP_NUM_PMSAR (12U)
#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU)
#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U)
#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U)
#define BSP_FEATURE_BSP_OSIS_PADDING (0U)
#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U)
#define BSP_FEATURE_BSP_RESET_TRNG (0U)
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option).
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option).
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle.
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles.
#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U)
#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U)
#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U)
#define BSP_FEATURE_BSP_FLASH_CACHE (1)
#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0)
#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0)
#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1)
#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U)
#define BSP_FEATURE_BSP_HAS_SP_MON (0U)
#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock.
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U)
#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U)
#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU
#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid.
#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U)
#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU)
#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U)
#define BSP_FEATURE_BSP_OSIS_PADDING (0U)
#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U)
#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U)
#define BSP_FEATURE_BSP_RESET_TRNG (0U)
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle.
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles.
#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U)
#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U)
#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U)
#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B')
#define BSP_FEATURE_CANFD_LITE (0U)
#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U)
#define BSP_FEATURE_CANFD_NUM_INSTANCES (1U)
#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U)
#define BSP_FEATURE_CAN_CLOCK (0U)
#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U)
#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA6M5 has CAN-FD
#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U)
#define BSP_FEATURE_CAN_CLOCK (0U)
#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U)
#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA6M5 has CAN-FD
#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U)
#define BSP_FEATURE_CANFD_LITE (0U)
#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1)
#define BSP_FEATURE_CGC_HAS_BCLK (1U)
#define BSP_FEATURE_CGC_HAS_CPUCLK (0U)
#define BSP_FEATURE_CGC_HAS_FCLK (1U)
#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U)
#define BSP_FEATURE_CGC_HAS_FLL (1U)
#define BSP_FEATURE_CGC_HAS_FLWT (1U)
#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U)
#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U)
#define BSP_FEATURE_CGC_HAS_PCLKA (1U)
#define BSP_FEATURE_CGC_HAS_PCLKB (1U)
#define BSP_FEATURE_CGC_HAS_PCLKC (1U)
#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
#define BSP_FEATURE_CGC_HAS_PCLKE (0U)
#define BSP_FEATURE_CGC_HAS_PLL (1U)
#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M5 there is another PLL that can be used as a clock source for USB and OCTASPI.
#define BSP_FEATURE_CGC_HAS_SOPCCR (1U)
#define BSP_FEATURE_CGC_HAS_SOSC (1U)
#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC.
#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U)
#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0)
#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U)
#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4)
#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U)
#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode
#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode
#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U)
#define BSP_FEATURE_CGC_MODRV_MASK (0x30U)
#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U)
#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U)
#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U)
#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000U)
#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP
#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0)
#define BSP_FEATURE_CGC_SODRV_MASK (0x02U)
#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U)
#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1)
#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78)
#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0)
#define BSP_FEATURE_CGC_HAS_BCLK (1U)
#define BSP_FEATURE_CGC_HAS_FCLK (1U)
#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U)
#define BSP_FEATURE_CGC_HAS_FLWT (1U)
#define BSP_FEATURE_CGC_HAS_FLL (1U)
#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U)
#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U)
#define BSP_FEATURE_CGC_HAS_PCLKA (1U)
#define BSP_FEATURE_CGC_HAS_PCLKB (1U)
#define BSP_FEATURE_CGC_HAS_PCLKC (1U)
#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
#define BSP_FEATURE_CGC_HAS_PLL (1U)
#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M5 there is another PLL that can be used as a clock source for USB and OCTASPI.
#define BSP_FEATURE_CGC_HAS_SOSC (1U)
#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC.
#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U)
#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4)
#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U)
#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode
#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode
#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U)
#define BSP_FEATURE_CGC_MODRV_MASK (0x30U)
#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U)
#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U)
#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP
#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U)
#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0)
#define BSP_FEATURE_CGC_SODRV_MASK (0x02U)
#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U)
#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0)
#define BSP_FEATURE_CRYPTO_HAS_AES (1)
#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1)
#define BSP_FEATURE_CRYPTO_HAS_ECC (1)
#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_HASH (1)
#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU TODO_CHECK_FEATURE
#define BSP_FEATURE_CRYPTO_HAS_RSA (1)
#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0)
#define BSP_FEATURE_CRYPTO_HAS_SCE5 (0)
#define BSP_FEATURE_CRYPTO_HAS_SCE5B (0)
#define BSP_FEATURE_CRYPTO_HAS_SCE7 (0)
#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1)
#define BSP_FEATURE_CRYPTO_HAS_AES (1)
#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_ECC (1)
#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_HASH (1)
#define BSP_FEATURE_CRYPTO_HAS_RSA (1)
#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1)
#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1)
#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U)
#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U)
#define BSP_FEATURE_CTSU_HAS_TXVSEL (1)
#define BSP_FEATURE_CTSU_VERSION (1)
#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U)
#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U)
#define BSP_FEATURE_CTSU_HAS_TXVSEL (1)
#define BSP_FEATURE_CTSU_VERSION (1)
#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U)
#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U)
#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U)
#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U)
#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U)
#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U)
#define BSP_FEATURE_DAC_MAX_CHANNELS (2U)
#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U)
#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U)
#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U)
#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U)
#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U)
#define BSP_FEATURE_DAC_MAX_CHANNELS (2U)
#define BSP_FEATURE_DMAC_HAS_DELSR (0U)
#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U)
#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
#define BSP_FEATURE_DOC_VERSION (1U)
#define BSP_FEATURE_DOC_VERSION (1U)
#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U)
#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register
#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register
#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU
#define BSP_FEATURE_ELC_VERSION (1U)
#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU
#define BSP_FEATURE_ELC_VERSION (1U)
#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U)
#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0U) // Feature not available on this MCU
#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U)
#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U)
#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U)
#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U)
#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U)
#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U)
#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U)
#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1)
#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1)
#define BSP_FEATURE_FLASH_HP_VERSION (40U)
#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U)
#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U)
#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U)
#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U)
#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1)
#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1)
#define BSP_FEATURE_FLASH_HP_VERSION (40U)
#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU
#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0)
#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0)
#define BSP_FEATURE_GPTE_CHANNEL_MASK (0)
#define BSP_FEATURE_GPTE_CHANNEL_MASK (0)
#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU)
#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U)
#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U)
#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_TPCS_SHIFT (0U)
#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU)
#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU)
#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU)
#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK)
#define BSP_FEATURE_GPT_HAS_GTCLKCR (0U)
#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU
#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U)
#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U)
#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU
#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU
#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU
#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU
#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U)
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register
#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U)
#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U)
#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U)
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register
#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U)
#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U)
#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07)
#define BSP_FEATURE_IIC_VERSION (1U)
#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U)
#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U)
#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U)
#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE
#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU TODO_CHECK_FEATURE
#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U)
#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07)
#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU TODO_CHECK_FEATURE
#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU
#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU
#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU
#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU)
#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
#define BSP_FEATURE_IOPORT_VERSION (1U)
#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU)
#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL)
#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0U) // Feature not available on this MCU
#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U)
#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U)
#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU)
#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU)
#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
#define BSP_FEATURE_LPM_HAS_STCONR (0U)
#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0)
#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register
#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register
#define BSP_FEATURE_KINT_HAS_MSTP (0U)
#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U)
#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U)
#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize
#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U)
#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U)
#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU)
#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU)
#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U)
#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U)
#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U)
#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U)
#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U)
#define BSP_FEATURE_LPM_HAS_LPSCR (0U)
#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U)
#define BSP_FEATURE_LPM_HAS_SNOOZE (1U)
#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
#define BSP_FEATURE_LPM_HAS_STCONR (0U)
#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0)
#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register
#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register
#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U)
#define BSP_FEATURE_IOPORT_VERSION (1U)
#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U)
#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U)
#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize
#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U)
#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U)
#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U)
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U)
#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U)
#define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U)
#define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U)
#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U)
#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U)
#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U)
#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U)
#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U)
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U)
#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U)
#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU)
#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U)
#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U)
#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U)
#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU)
#define BSP_FEATURE_SCI_VERSION (1U)
#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_CHANNELS (0x3FFU)
#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature
#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U)
#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U)
#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U)
#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U)
#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB)
#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported
#define BSP_FEATURE_RTC_IS_AVAILABLE (1U)
#define BSP_FEATURE_RTC_IS_IRTC (0U)
#define BSP_FEATURE_RTC_HAS_ROPSEL (0U)
#define BSP_FEATURE_RTC_HAS_TCEN (0U)
#define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U)
#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U)
#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U)
#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_CHANNELS (0x3FFU)
#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature
#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
#define BSP_FEATURE_SCI_VERSION (1U)
#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU
#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB)
#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U)
#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported
#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U)
#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U)
#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SPI_HAS_SPCR3 (1U)
#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U)
#define BSP_FEATURE_SPI_MAX_CHANNEL (2U)
#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U)
#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U)
#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0)
#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U)
#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U)
#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SPI_HAS_SPCR3 (1U)
#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U)
#define BSP_FEATURE_SPI_MAX_CHANNEL (2U)
#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x3U)
#define BSP_FEATURE_TFU_SPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU
#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U)
#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U)
#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U)
#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U)
#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U)
#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU
#define BSP_FEATURE_BSP_NUM_PMSAR (12U)
#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U)
#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U)
#define BSP_FEATURE_TZ_HAS_DLM (1U)
#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0)
#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U)
#define BSP_FEATURE_CRC_HAS_SNOOP (0U)
#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x0U)
#endif

2
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are

135
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_ioport/r_ioport.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -46,10 +46,6 @@
/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
#define IOPORT_PRV_PORT_OFFSET (8U)
#ifndef BSP_MCU_VBATT_SUPPORT
#define BSP_MCU_VBATT_SUPPORT (0U)
#endif
#define IOPORT_PRV_PORT_BITS (0xFF00U)
#define IOPORT_PRV_PIN_BITS (0x00FFU)
@ -84,7 +80,7 @@ static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t port,
static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value);
#if BSP_MCU_VBATT_SUPPORT
#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP
#endif
@ -106,7 +102,6 @@ const ioport_api_t g_ioport_on_ioport =
.pinCfg = R_IOPORT_PinCfg,
.pinEventInputRead = R_IOPORT_PinEventInputRead,
.pinEventOutputWrite = R_IOPORT_PinEventOutputWrite,
.pinEthernetModeCfg = R_IOPORT_EthernetModeCfg,
.pinRead = R_IOPORT_PinRead,
.pinWrite = R_IOPORT_PinWrite,
.portDirectionSet = R_IOPORT_PortDirectionSet,
@ -116,7 +111,7 @@ const ioport_api_t g_ioport_on_ioport =
.portWrite = R_IOPORT_PortWrite,
};
#if BSP_MCU_VBATT_SUPPORT
#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
static const bsp_io_port_pin_t g_vbatt_pins_input[] =
{
BSP_IO_PORT_04_PIN_02, ///< Associated with VBTICTLR->VCH0INEN
@ -238,7 +233,7 @@ fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin,
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
#if BSP_MCU_VBATT_SUPPORT
#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
/* Create temporary structure for handling VBATT pins. */
ioport_cfg_t temp_cfg;
@ -673,39 +668,6 @@ fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_por
return FSP_SUCCESS;
}
/***********************************************************************************************************************
* DEPRECATED Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg.
*
* @retval FSP_SUCCESS Ethernet PHY mode set
* @retval FSP_ERR_INVALID_ARGUMENT Channel or mode not valid
* @retval FSP_ERR_UNSUPPORTED Ethernet configuration not supported on this device.
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is not re-entrant.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const p_ctrl,
ioport_ethernet_channel_t channel,
ioport_ethernet_mode_t mode)
{
FSP_ERROR_RETURN(1U == BSP_FEATURE_IOPORT_HAS_ETHERNET, FSP_ERR_UNSUPPORTED);
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(channel < IOPORT_ETHERNET_CHANNEL_END, FSP_ERR_INVALID_ARGUMENT);
FSP_ERROR_RETURN(mode < IOPORT_ETHERNET_MODE_END, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
FSP_PARAMETER_NOT_USED(channel);
#endif
R_PMISC->PFENET = (uint8_t) mode;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* @} (end addtogroup IOPORT)
**********************************************************************************************************************/
@ -721,7 +683,7 @@ fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const p_ctrl,
**********************************************************************************************************************/
void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
{
#if BSP_MCU_VBATT_SUPPORT
#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
/* Handle any VBATT domain pin configuration. */
bsp_vbatt_init(p_cfg);
@ -812,7 +774,7 @@ static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value)
R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value;
}
#if BSP_MCU_VBATT_SUPPORT
#if BSP_FEATURE_SYSC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN
/*******************************************************************************************************************//**
* @brief Initializes VBTICTLR register based on pin configuration.
@ -826,12 +788,6 @@ static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
{
uint32_t pin_index;
uint32_t vbatt_index;
uint8_t local_vbtictlr_set; ///< Will hold bits to set in VBTICTLR
uint8_t local_vbtictlr_clear; ///< Will hold bits to clear in VBTICTLR
/* Make no changes unless required. */
local_vbtictlr_set = 0U;
local_vbtictlr_clear = 0U;
/* Must loop over all pins as pin configuration table is unordered. */
for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++)
@ -850,29 +806,78 @@ static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value))
{
/* Bit should be set to 1. */
local_vbtictlr_set |= (uint8_t) (1U << vbatt_index);
#if BSP_FEATURE_SYSC_HAS_VBTICTLR
if (0 == (R_SYSTEM->VBTICTLR & (uint8_t) (1U << vbatt_index)))
{
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
R_SYSTEM->VBTICTLR |= (uint8_t) (1U << vbatt_index);
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
else
{
/* Do nothing: it is already enabled. */
}
#endif
#if BSP_FEATURE_RTC_HAS_TCEN
#if BSP_TZ_NONSECURE_BUILD
if (0 == R_PSCU->PSARE_b.PSARE2)
{
/* Do nothing: non secure build can't configure secure RTC registers. */
}
else
#endif
{
if (0 == R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN)
{
R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN = 1;
R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
}
else
{
/* Do nothing: it is already enabled. */
}
}
#endif
}
else
{
/* Bit should be cleared to 0. */
local_vbtictlr_clear |= (uint8_t) (1U << vbatt_index);
#if BSP_FEATURE_SYSC_HAS_VBTICTLR
if ((R_SYSTEM->VBTICTLR & (uint8_t) (1U << vbatt_index)) > 0)
{
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
R_SYSTEM->VBTICTLR &= (uint8_t) ~(1U << vbatt_index);
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
else
{
/* Do nothing: it is already disabled. */
}
#endif
#if BSP_FEATURE_RTC_HAS_TCEN
#if BSP_TZ_NONSECURE_BUILD
if (0 == R_PSCU->PSARE_b.PSARE2)
{
/* Do nothing: non secure build can't configure secure RTC registers. */
}
else
#endif
{
if (R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN > 0)
{
R_RTC->RTCCR[vbatt_index].RTCCR_b.TCEN = 0;
R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
}
else
{
/* Do nothing: it is already disabled. */
}
}
#endif
}
}
}
}
/* Disable write protection on VBTICTLR. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
/* Read value, set and clear bits as needed and write back. */
uint8_t local_vbtictlr = R_SYSTEM->VBTICTLR;
local_vbtictlr |= local_vbtictlr_set; ///< Set appropriate bits
local_vbtictlr &= (uint8_t) ~local_vbtictlr_clear; ///< Clear appropriate bits
R_SYSTEM->VBTICTLR = local_vbtictlr;
/* Enable write protection on VBTICTLR. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif

180
bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/r_sci_uart/r_sci_uart.c
View File

@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
@ -93,6 +93,7 @@
#define SCI_SSR_ORER_MASK (0x20U) ///< overflow error
#define SCI_SSR_FER_MASK (0x10U) ///< framing error
#define SCI_SSR_PER_MASK (0x08U) ///< parity err
#define SCI_SSR_FIFO_RESERVED_MASK (0x02U) ///< Reserved bit mask for SSR_FIFO register
#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK)
#define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE)
@ -168,6 +169,9 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_uart_prv_ns_callback)(uart_c
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
static void r_sci_negate_de_pin(sci_uart_instance_ctrl_t const * const p_ctrl);
#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * const p_ctrl,
@ -316,7 +320,7 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
/* Check parameters. */
FSP_ASSERT(p_ctrl);
FSP_ASSERT(p_cfg);
FSP_ASSERT(p_cfg->p_callback);
FSP_ASSERT(p_cfg->p_extend);
FSP_ASSERT(((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting);
FSP_ERROR_RETURN(SCI_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
@ -337,6 +341,15 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
FSP_ERR_INVALID_ARGUMENT);
}
#if (SCI_UART_CFG_RS485_SUPPORT)
if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.enable == SCI_UART_RS485_ENABLE)
{
FSP_ERROR_RETURN(
((sci_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.de_control_pin != SCI_UART_INVALID_16BIT_PARAM,
FSP_ERR_INVALID_ARGUMENT);
}
#endif
FSP_ASSERT(p_cfg->rxi_irq >= 0);
FSP_ASSERT(p_cfg->txi_irq >= 0);
FSP_ASSERT(p_cfg->tei_irq >= 0);
@ -378,6 +391,9 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co
FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
#endif
/* Negate driver enable if RS-485 mode is enabled. */
r_sci_negate_de_pin(p_ctrl);
/* Enable the SCI channel and reset the registers to their initial state. */
R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel);
@ -488,6 +504,9 @@ fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_api_ctrl)
/* Remove power to the channel. */
R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel);
/* Negate driver enable if RS-485 mode is enabled. */
r_sci_negate_de_pin(p_ctrl);
return FSP_SUCCESS;
}
@ -583,6 +602,22 @@ fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons
FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE);
#endif
#if (SCI_UART_CFG_RS485_SUPPORT)
sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
/* If RS-485 is enabled, then assert the driver enable pin at the start of a write transfer. */
if (p_extend->rs485_setting.enable)
{
R_BSP_PinAccessEnable();
bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH ==
p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW;
R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level);
R_BSP_PinAccessDisable();
}
#endif
/* Transmit interrupts must be disabled to start with. */
p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
@ -844,6 +879,9 @@ fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communica
#endif
p_ctrl->tx_src_bytes = 0U;
/* Negate driver enable if RS-485 mode is enabled. */
r_sci_negate_de_pin(p_ctrl);
FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
}
#endif
@ -915,17 +953,6 @@ fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remain
*remaining_bytes = transfer_info.transfer_length_remaining;
}
#endif
#if SCI_UART_CFG_FIFO_SUPPORT
if (0U != p_ctrl->fifo_depth)
{
/* Reset the receive fifo */
p_ctrl->p_reg->FCR_b.RFRST = 1U;
/* Wait until RFRST cleared after 1 PCLK according to section 34.2.26 "FIFO Control Register (FCR) in the
* RA6M3 manual R01UH0886EJ0100 or the relevant section for the MCU being used.*/
FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.RFRST, 0U);
}
#endif
#else
return FSP_ERR_UNSUPPORTED;
@ -940,14 +967,14 @@ fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remain
*
* @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc.
* @param[in] bitrate_modulation Enable bitrate modulation
* @param[in] baud_rate_error_x_1000 &lt;baud_rate_percent_error&gt; x 1000 required for module to function.
* Absolute max baud_rate_error is 15000 (15%).
* @param[in] baud_rate_error_x_1000 Max baud rate error. At most &lt;baud_rate_percent_error&gt; x 1000 required
* for module to function. Absolute max baud_rate_error is 15000 (15%).
* @param[out] p_baud_setting Baud setting information stored here if successful
*
* @retval FSP_SUCCESS Baud rate is set successfully
* @retval FSP_ERR_ASSERTION Null pointer
* @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', source clock frequency could not be read, or error in
* calculated baud rate is larger than 10%.
* @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested
* max error, or requested max error in baud rate is larger than 15%.
**********************************************************************************************************************/
fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
bool bitrate_modulation,
@ -956,12 +983,12 @@ fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
{
#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(p_baud_setting);
FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 > baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT);
FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 >= baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT);
FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT);
#endif
p_baud_setting->brr = SCI_UART_BRR_MAX;
p_baud_setting->brme = 0U;
p_baud_setting->brr = SCI_UART_BRR_MAX;
p_baud_setting->semr_baudrate_bits_b.brme = 0U;
p_baud_setting->mddr = SCI_UART_MDDR_MIN;
/* Find the best BRR (bit rate register) value.
@ -1059,18 +1086,18 @@ fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
*/
if (bit_err < hit_bit_err)
{
p_baud_setting->bgdm = g_async_baud[i].bgdm;
p_baud_setting->abcs = g_async_baud[i].abcs;
p_baud_setting->abcse = g_async_baud[i].abcse;
p_baud_setting->cks = g_async_baud[i].cks;
p_baud_setting->brr = (uint8_t) temp_brr;
hit_bit_err = bit_err;
hit_mddr = mddr;
p_baud_setting->semr_baudrate_bits_b.bgdm = g_async_baud[i].bgdm;
p_baud_setting->semr_baudrate_bits_b.abcs = g_async_baud[i].abcs;
p_baud_setting->semr_baudrate_bits_b.abcse = g_async_baud[i].abcse;
p_baud_setting->cks = g_async_baud[i].cks;
p_baud_setting->brr = (uint8_t) temp_brr;
hit_bit_err = bit_err;
hit_mddr = mddr;
}
if (bitrate_modulation)
{
p_baud_setting->brme = 1U;
p_baud_setting->semr_baudrate_bits_b.brme = 1U;
p_baud_setting->mddr = (uint8_t) hit_mddr;
}
else
@ -1096,6 +1123,33 @@ fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate,
* Private Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Negate the DE pin if it is enabled.
*
* @param[in] p_ctrl Pointer to the control block for the channel.
**********************************************************************************************************************/
static void r_sci_negate_de_pin (sci_uart_instance_ctrl_t const * const p_ctrl)
{
#if (SCI_UART_CFG_RS485_SUPPORT)
sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
/* If RS-485 is enabled, then negate the driver enable pin at the end of a write transfer. */
if (p_extend->rs485_setting.enable)
{
R_BSP_PinAccessEnable();
bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH ==
p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH;
R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level);
R_BSP_PinAccessDisable();
}
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
}
#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE)
/*******************************************************************************************************************//**
@ -1172,7 +1226,7 @@ static fsp_err_t r_sci_uart_transfer_configure (sci_uart_instance_ctrl_t * const
if (UART_DATA_BITS_9 == p_ctrl->p_cfg->data_bits)
{
p_info->size = TRANSFER_SIZE_2_BYTE;
p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE;
/* Casting for compatibility with 7 or 8 bit mode. */
*p_transfer_reg = sci_buffer_address + SCI_UART_9BIT_TRANSFER_BUFFER_OFFSET;
@ -1554,7 +1608,7 @@ static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_ctrl, uint32_
void sci_uart_txi_isr (void)
{
/* Save context if RTOS is used */
FSP_CONTEXT_SAVE;
FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
@ -1589,7 +1643,12 @@ void sci_uart_txi_isr (void)
}
/* Clear TDFE flag */
p_ctrl->p_reg->SSR_FIFO_b.TDFE = 0U;
/* Don't acess the flag via bit fields because bit 1 is reserved. It must be written as '1' and has an */
/* undefined read value. Bit fields will attempt to do a read-modify-write which could have unintended */
/* side effects provided the undefined read behavior. */
uint8_t ssr_fifo =
(uint8_t) ((p_ctrl->p_reg->SSR_FIFO | SCI_SSR_FIFO_RESERVED_MASK) & ~R_SCI0_SSR_FIFO_TDFE_Msk);
p_ctrl->p_reg->SSR_FIFO = ssr_fifo;
}
else
#endif
@ -1620,11 +1679,16 @@ void sci_uart_txi_isr (void)
p_ctrl->p_reg->SCR = scr_temp;
p_ctrl->p_tx_src = NULL;
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY);
/* If a callback was provided, call it with the argument */
if (NULL != p_ctrl->p_callback)
{
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY);
}
}
/* Restore context if RTOS is used */
FSP_CONTEXT_RESTORE;
FSP_CONTEXT_RESTORE
}
#endif
@ -1647,7 +1711,7 @@ void sci_uart_txi_isr (void)
void sci_uart_rxi_isr (void)
{
/* Save context if RTOS is used */
FSP_CONTEXT_SAVE;
FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
@ -1701,8 +1765,12 @@ void sci_uart_rxi_isr (void)
if (0 == p_ctrl->rx_dest_bytes)
{
/* Call user callback with the data. */
r_sci_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR);
/* If a callback was provided, call it with the argument */
if (NULL != p_ctrl->p_callback)
{
/* Call user callback with the data. */
r_sci_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR);
}
}
else
{
@ -1712,7 +1780,11 @@ void sci_uart_rxi_isr (void)
if (0 == p_ctrl->rx_dest_bytes)
{
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
/* If a callback was provided, call it with the argument */
if (NULL != p_ctrl->p_callback)
{
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
}
}
}
@ -1744,13 +1816,17 @@ void sci_uart_rxi_isr (void)
p_ctrl->p_rx_dest = NULL;
/* Call callback */
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
/* If a callback was provided, call it with the argument */
if (NULL != p_ctrl->p_callback)
{
/* Call callback */
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE);
}
}
#endif
/* Restore context if RTOS is used */
FSP_CONTEXT_RESTORE;
FSP_CONTEXT_RESTORE
}
#endif
@ -1765,7 +1841,7 @@ void sci_uart_rxi_isr (void)
void sci_uart_tei_isr (void)
{
/* Save context if RTOS is used */
FSP_CONTEXT_SAVE;
FSP_CONTEXT_SAVE
IRQn_Type irq = R_FSP_CurrentIrqGet();
@ -1775,13 +1851,20 @@ void sci_uart_tei_isr (void)
/* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */
p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE);
/* Negate driver enable if RS-485 mode is enabled. */
r_sci_negate_de_pin(p_ctrl);
/* If a callback was provided, call it with the argument */
if (NULL != p_ctrl->p_callback)
{
r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE);
}
/* Clear pending IRQ to make sure it doesn't fire again after exiting */
R_BSP_IrqStatusClear(irq);
/* Restore context if RTOS is used */
FSP_CONTEXT_RESTORE;
FSP_CONTEXT_RESTORE
}
#endif
@ -1833,8 +1916,15 @@ void sci_uart_eri_isr (void)
/* Clear error condition. */
p_ctrl->p_reg->SSR &= (uint8_t) (~SCI_RCVR_ERR_MASK);
/* Call callback. */
r_sci_uart_call_callback(p_ctrl, data, event);
/* Negate driver enable if RS-485 mode is enabled. */
r_sci_negate_de_pin(p_ctrl);
/* If a callback was provided, call it with the argument */
if (NULL != p_ctrl->p_callback)
{
/* Call callback. */
r_sci_uart_call_callback(p_ctrl, data, event);
}
/* Clear pending IRQ to make sure it doesn't fire again after exiting */
R_BSP_IrqStatusClear(irq);

10
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/board_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
void bsp_init(void * p_args);
#ifdef __cplusplus
extern "C" {
#endif
void bsp_init(void * p_args);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_CFG_H_ */

14
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
View File

@ -1,7 +1,11 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#include "bsp_clock_cfg.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
@ -14,6 +18,9 @@
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
@ -30,7 +37,6 @@
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) // DEPRECATED, replace with BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
@ -49,4 +55,8 @@
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */

1
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
View File

@ -2,6 +2,7 @@
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA6M5BH3CFC
#define BSP_MCU_FEATURE_SET ('B')
#define BSP_ROM_SIZE_BYTES (2097152)
#define BSP_RAM_SIZE_BYTES (524288)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)

28
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
View File

@ -1,7 +1,11 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#include "bsp_mcu_device_pn_cfg.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
@ -23,7 +27,6 @@
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
#define BSP_MCU_VBATT_SUPPORT (1)
#if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
@ -294,6 +297,11 @@
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
#endif
/* Enable Uninitialized Non-Secure Application Fallback. */
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
#endif
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
@ -332,6 +340,10 @@
/* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
#endif
/* Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_BPS3
#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
#endif
/* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
@ -344,6 +356,10 @@
/* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
#endif
/* Permanent Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_PBPS3
#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
#endif
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
@ -356,8 +372,16 @@
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
#endif
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
View File

@ -2,7 +2,15 @@
#ifndef BSP_PIN_CFG_H_
#define BSP_PIN_CFG_H_
#include "r_ioport.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
void BSP_PinConfigSecurityInit();
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif /* BSP_PIN_CFG_H_ */

8
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_ioport_cfg.h
View File

@ -1,5 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */

11
bsp/renesas/ebf_qi_min_6m5/ra_cfg/fsp_cfg/r_sci_uart_cfg.h
View File

@ -1,8 +1,17 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
extern "C" {
#endif
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#define SCI_UART_CFG_RS485_SUPPORT (0)
#ifdef __cplusplus
}
#endif
#endif /* R_SCI_UART_CFG_H_ */

10
bsp/renesas/ebf_qi_min_6m5/ra_gen/bsp_clock_cfg.h
View File

@ -7,25 +7,29 @@
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCLK Disabled */
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* BCLK/2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
#endif /* BSP_CLOCK_CFG_H_ */

11
bsp/renesas/ebf_qi_min_6m5/ra_gen/hal_data.c
View File

@ -4,7 +4,7 @@ sci_uart_instance_ctrl_t g_uart4_ctrl;
baud_setting_t g_uart4_baud_setting =
{
/* Baud rate calculated with 0.469% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .brme = false
/* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
@ -21,6 +21,15 @@ sci_uart_instance_ctrl_t g_uart4_ctrl;
#else
.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
#endif
.rs485_setting = {
.enable = SCI_UART_RS485_DISABLE,
.polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
#if 0xFF != 0xFF
.de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
#else
.de_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
#endif
},
};
/** UART interface configuration */

6
bsp/renesas/ebf_qi_min_6m5/ra_gen/vector_data.h
View File

@ -1,6 +1,9 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (4)
@ -20,4 +23,7 @@
#define SCI4_TEI_IRQn ((IRQn_Type) 2) /* SCI4 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 3) /* SCI4 ERI (Receive error) */
#define SCI4_ERI_IRQn ((IRQn_Type) 3) /* SCI4 ERI (Receive error) */
#ifdef __cplusplus
}
#endif
#endif /* VECTOR_DATA_H */

387
bsp/renesas/ebf_qi_min_6m5/template.uvoptx
View File

@ -1,180 +1,213 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>1</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U-O78 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>1</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA6M5_2M -FS00 -FL0200000 -FF1RA6M5_DATA_C2M -FS18000000 -FL12000 -FF2RA6M5_CONF -FS2100A000 -FL2300 -FP0($$Device:R7FA6M5BH$Flash\RA6M5_2M.FLM) -FP1($$Device:R7FA6M5BH$Flash\RA6M5_DATA_C2M.FLM) -FP2($$Device:R7FA6M5BH$Flash\RA6M5_CONF.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U20730543 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN3 -FF0RA6M5_2M -FS00 -FL0200000 -FP0($$Device:R7FA6M5BH$Flash\RA6M5_2M.FLM) -FF1RA6M5_CONF -FS1100A100 -FL1300 -FP1($$Device:R7FA6M5BH$Flash\RA6M5_CONF.FLM) -FF2RA6M5_DATA_C2M -FS28000000 -FL22000 -FP2($$Device:R7FA6M5BH$Flash\RA6M5_DATA_C2M.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
<Group>
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\src\hal_entry.c</PathWithFileName>
<FilenameWithoutPath>hal_entry.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

825
bsp/renesas/ebf_qi_min_6m5/template.uvprojx
View File

@ -1,407 +1,422 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>R7FA6M5BH</Device>
<Vendor>Renesas</Vendor>
<PackID>Renesas.RA_DFP.3.5.0</PackID>
<PackURL></PackURL>
<Cpu>CPUTYPE("Cortex-M33") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>template</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2&gt; "%%TEMP%%\rasc_stderr.out"""</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>2</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument/>
<IncludeLibraryModules/>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>0</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2/>
<Flash3>"" ()</Flash3>
<Flash4/>
<pFcarmOut/>
<pFcarmGrp/>
<pFcArmRoot/>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M33"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>0</RoSelD>
<RwSelD>0</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IRAM>
<IROM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>6</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange></TextAddressRange>
<DataAddressRange></DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\script\fsp.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--entry=Reset_Handler --no_startup --via=".\script\ac6\fsp_keep.via"</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings>6319,6314</DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<gpdscs>
<gpdsc name="buildinfo.gpdsc">
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</gpdsc>
</gpdscs>
<apis/>
<components>
<component Cvendor="Renesas" Cclass="Flex Software" Cgroup="RA Configuration" Cversion="1.0.0" condition="RA Device" generator="Renesas RA Smart Configurator">
<package name="RA_DFP" vendor="Renesas" version="3.5.0" url="www.renesas.com/RA/MDK_pack/" schemaVersion="1.6.0"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>R7FA6M5BH</Device>
<Vendor>Renesas</Vendor>
<PackID>Renesas.RA_DFP.4.4.0</PackID>
<PackURL>https://www2.renesas.eu/Keil_MDK_Packs/</PackURL>
<Cpu>CPUTYPE("Cortex-M33") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:R7FA6M5BH$SVD\R7FA6M5BH.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>template</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2&gt; "%%TEMP%%\rasc_stderr.out"""</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>2</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2></Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M33"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>0</RoSelD>
<RwSelD>0</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IRAM>
<IROM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>6</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange></TextAddressRange>
<DataAddressRange></DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\script\fsp.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--entry=Reset_Handler --no_startup --via=".\script\ac6\fsp_keep.via"</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings>6319,6314</DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
<Group>
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
<Files>
<File>
<FileName>hal_entry.c</FileName>
<FileType>1</FileType>
<FilePath>.\src\hal_entry.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<gpdscs>
<gpdsc name="buildinfo.gpdsc">
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</gpdsc>
</gpdscs>
<apis/>
<components>
<component Cclass="Flex Software" Cgroup="RA Configuration" Cvendor="Renesas" Cversion="1.0.0" condition="RA Device" generator="Renesas RA Smart Configurator">
<package name="RA_DFP" schemaVersion="1.7.2" url="https://www2.renesas.eu/Keil_MDK_Packs/" vendor="Renesas" version="4.4.0"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
</Project>

3
bsp/renesas/libraries/HAL_Drivers/SConscript
View File

@ -32,6 +32,9 @@ if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend(['BSP_USING_I2C', 'BSP_USING_HW_I2C']):
src += ['drv_i2c.c']
if GetDepend(['BSP_USING_I2C', 'BSP_USING_SCI_I2C']):
src += ['drv_sci_i2c.c']
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']

209
bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c Normal file
View File

@ -0,0 +1,209 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-06-04 vandoul first version
*/
#include <rtdevice.h>
#include <rtthread.h>
#include "board.h"
#include <stdlib.h>
#ifdef BSP_USING_SCI_I2C
#define DBG_TAG "drv.sci2c"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#include <hal_data.h>
struct ra_sci_i2c_handle
{
struct rt_i2c_bus_device bus;
char bus_name[RT_NAME_MAX];
const i2c_master_cfg_t *i2c_cfg;
void *i2c_ctrl;
struct rt_event event;
};
enum
{
I2C_EVENT_ABORTED = 1UL<<I2C_MASTER_EVENT_ABORTED , ///< A transfer was aborted
I2C_EVENT_RX_COMPLETE = 1UL<<I2C_MASTER_EVENT_RX_COMPLETE, ///< A receive operation was completed successfully
I2C_EVENT_TX_COMPLETE = 1UL<<I2C_MASTER_EVENT_TX_COMPLETE, ///< A transmit operation was completed successfully
};
#define I2C_EVENT_ALL (I2C_EVENT_ABORTED|I2C_EVENT_RX_COMPLETE|I2C_EVENT_TX_COMPLETE)
//static volatile = I2C_MASTER_EVENT_ABORTED;
static struct ra_sci_i2c_handle ra_sci_i2cs[] =
{
#ifdef BSP_USING_SCI_I2C0
{.bus_name = "sci2c0", .i2c_cfg = &g_sci_i2c0_cfg, .i2c_ctrl = &g_sci_i2c0_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C1
{.bus_name = "sci2c1", .i2c_cfg = &g_sci_i2c1_cfg, .i2c_ctrl = &g_sci_i2c1_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C2
{.bus_name = "sci2c2", .i2c_cfg = &g_sci_i2c2_cfg, .i2c_ctrl = &g_sci_i2c2_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C3
{.bus_name = "sci2c3", .i2c_cfg = &g_sci_i2c3_cfg, .i2c_ctrl = &g_sci_i2c3_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C4
{.bus_name = "sci2c4", .i2c_cfg = &g_sci_i2c4_cfg, .i2c_ctrl = &g_sci_i2c4_ctrl,},
#endif
#ifdef BSP_USING_SCI_I2C5
{.bus_name = "sci2c5", .i2c_cfg = &g_sci_i2c5_cfg, .i2c_ctrl = &g_sci_i2c5_ctrl,},
#endif
};
void sci_i2c_master_callback(i2c_master_callback_args_t *p_args)
{
if (NULL != p_args)
{
/* capture callback event for validating the i2c transfer event*/
struct ra_sci_i2c_handle *ra_sci_i2c = (struct ra_sci_i2c_handle *)p_args->p_context;
rt_event_send(&ra_sci_i2c->event, 1UL << p_args->event);
LOG_D("event:%x", p_args->event);
}
LOG_D("p_args:%p", p_args);
}
static rt_err_t validate_i2c_event(struct ra_sci_i2c_handle *handle)
{
rt_uint32_t event = 0;
if(RT_EOK != rt_event_recv(&handle->event, I2C_EVENT_ALL, RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(10), &event))
{
return -RT_ETIMEOUT;
}
if(event != I2C_EVENT_ABORTED)
{
return RT_EOK;
}
return -RT_ERROR;
}
static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
rt_size_t i;
struct rt_i2c_msg *msg = msgs;
RT_ASSERT(bus != RT_NULL);
struct ra_sci_i2c_handle *ra_sci_i2c = rt_container_of(bus, struct ra_sci_i2c_handle, bus);
i2c_master_ctrl_t *master_ctrl = ra_sci_i2c->i2c_ctrl;
fsp_err_t err = FSP_SUCCESS;
bool restart = false;
for (i = 0; i < num; i++)
{
if (msg[i].flags & RT_I2C_NO_START)
{
restart = true;
}
if (msg[i].flags & RT_I2C_ADDR_10BIT)
{
//LOG_E("10Bit not support");
//break;
R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT);
}
else
{
//master_ctrl->slave = msg[i].addr;
R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT);
}
if (msg[i].flags & RT_I2C_RD)
{
err = R_SCI_I2C_Read(master_ctrl, msg[i].buf, msg[i].len, restart);
if (FSP_SUCCESS == err)
{
/* handle error */
if(RT_EOK != validate_i2c_event(ra_sci_i2c))
{
//LOG_E("POWER_CTL reg I2C read failed,%d", ra_sci_i2c->event);
break;
}
}
/* handle error */
else
{
/* Write API returns itself is not successful */
//LOG_E("R_IIC_MASTER_Write API failed");
break;
}
}
else
{
err = R_SCI_I2C_Write(master_ctrl, msg[i].buf, msg[i].len, restart);
if (FSP_SUCCESS == err)
{
if(RT_EOK != validate_i2c_event(ra_sci_i2c))
{
//LOG_E("POWER_CTL reg I2C write failed,%d", ra_sci_i2c->event);
break;
}
}
/* handle error */
else
{
/* Write API returns itself is not successful */
//LOG_E("R_IIC_MASTER_Write API failed");
break;
}
}
}
return (rt_ssize_t)i;
}
static const struct rt_i2c_bus_device_ops ra_i2c_ops =
{
.master_xfer = ra_i2c_mst_xfer,
.slave_xfer = RT_NULL,
.i2c_bus_control = RT_NULL
};
int ra_hw_i2c_init(void)
{
fsp_err_t err = FSP_SUCCESS;
for(rt_uint32_t i=0; i<sizeof(ra_sci_i2cs)/sizeof(ra_sci_i2cs[0]); i++)
{
ra_sci_i2cs[i].bus.ops = &ra_i2c_ops;
ra_sci_i2cs[i].bus.priv = 0;
if(RT_EOK != rt_event_init(&ra_sci_i2cs[i].event, ra_sci_i2cs[i].bus_name, RT_IPC_FLAG_FIFO))
{
LOG_E("init event failed");
continue;
}
/* opening IIC master module */
err = R_SCI_I2C_Open(ra_sci_i2cs[i].i2c_ctrl, ra_sci_i2cs[i].i2c_cfg);
if(err != FSP_SUCCESS)
{
LOG_E("R_IIC_MASTER_Open API failed,%d", err);
continue;
}
err = R_SCI_I2C_CallbackSet(ra_sci_i2cs[i].i2c_ctrl, sci_i2c_master_callback, &ra_sci_i2cs[i], RT_NULL);
/* handle error */
if (FSP_SUCCESS != err)
{
LOG_E("R_SCI_I2C_CallbackSet API failed,%d", err);
continue;
}
rt_i2c_bus_device_register(&ra_sci_i2cs[i].bus, ra_sci_i2cs[i].bus_name);
}
return 0;
}
INIT_DEVICE_EXPORT(ra_hw_i2c_init);
#endif /* BSP_USING_I2C */